 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| to all our customers regarding the change of names ment ioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomput er, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitac hi, ltd., hitachi semiconductors, and other hitachi brand names are m entioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. ex cept for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: www.renesas.com renesas technology corp. customer support dept. april 1, 2003 renesas technology corp.
hitachi superh? risc engine sh7705 hardware manual ade-602-276 rev. 1.0 11/29/02 hitachi, ltd. rev. 1.0, 11/02, page ii of xxxviii cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi?s or any third party?s patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party?s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi?s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi?s sales office for any questions regarding this document or hitachi semiconductor products. rev. 1.0, 11/02, page iii of xxxviii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product?s state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. do not access these registers; the system?s operation is not guaranteed if they are accessed. rev. 1.0, 11/02, page iv of xxxviii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. index rev. 1.0, 11/02, page v of xxxviii preface the sh7705 single-chip risc (reduced instruction set computer) microprocessor includes a hitachi-original risc cpu as its core, and the peripheral functions required to configure a system. target users: this manual was written for users who will be using the sh7705 micro-computer unit (mcu) in the design of application systems. users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the sh7705 mcu to the above users. refer to the sh-3/sh-3e/sh3-dsp programming manual for a detailed description of the instruction set. notes on reading this manual: ? product names the following products are covered in this manual. product classifications and abbreviations basic classification product code sh7705 HD6417705 ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripheral functions and electrical characteristics. ? in order to understand the details of the cpu's functions read the sh-3/sh-3e/sh3-dsp programming manual. rev. 1.0, 11/02, page vi of xxxviii rules: register name: the following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb (most significant bit) is on the left and the lsb (least significant bit) is on the right. number notation: binary is b?xxxx, hexadecimal is h?xxxx, decimal is xxxx signal notation: an overbar is added to a low-active signal: xxxx related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com/ sh7705 manuals: manual title ade no. sh7705 hardware manual this manual sh-3/sh-3e/sh3-dsp programming manual ade-602-096 users manuals for development tools: manual title ade no. sh series c/c++ compiler, assembler, optimizing linkage editor user's manual ade-702-246 sh series simulator/debugger (for windows) user's manual ade-702-186 sh series simulator/debugger (for unix) user's manual ade-702-203 hitachi embedded workshop user's manual ade-702-201 sh series hitachi embedded workshop, hitachi debugging interface tutorial ade-702-230 rev. 1.0, 11/02, page vii of xxxviii abbreviations adc analog to digital converter alu arithmetic logic unit ase adaptive system evaluator asid address space identifier aud advanced user debugger bcd binary coded decimal bps bit per second bsc bus state controller ccn cache memory controller cmt compare match timer cpg clock pulse generator cpu central processing unit dmac direct memory access controller etu elementary time unit fifo first-in first-out hi-z high impedance h-udi hitachi user debugging interface intc interrupt controller irda infrared data association jtag joint test action group lqfp low profile qfp lru least recently used lsb least significant bit mmu memory management unit mpx multiplex msb most significant bit pc program counter pfc pin function controller pll phase locked loop pwm pulse width modulation ram random access memory risc reduced instruction set computer rom read only memory rtc realtime clock scif serial communication interface with fifo rev. 1.0, 11/02, page viii of xxxviii sdram synchronous dram tap test access port t.b.d to be determined tlb translation lookaside buffer tmu timer unit tpu timer pulse unit uart universal asynchronous receiver/transmitter ubc user break controller usb universal serial bus wdt watchdog timer rev. 1.0, 11/02, page ix of xxxviii contents section 1 overview........................................................................................... 1 1.1 sh7705 features ............................................................................................................. ..1 1.2 block diagram ............................................................................................................... ...6 1.3 pin assignment .............................................................................................................. ...7 1.4 pin functions ............................................................................................................... .....17 section 2 cpu................................................................................................... 25 2.1 processing states and processing modes ..........................................................................25 2.1.1 processing states..................................................................................................25 2.1.2 processing modes ................................................................................................26 2.2 memory map .................................................................................................................. ..27 2.2.1 logical address space.........................................................................................27 2.2.2 external memory space.......................................................................................28 2.3 register descriptions ....................................................................................................... .29 2.3.1 general registers .................................................................................................32 2.3.2 system registers ..................................................................................................33 2.3.3 program counter..................................................................................................34 2.3.4 control registers .................................................................................................35 2.4 data formats ................................................................................................................ .....37 2.4.1 register data format ...........................................................................................37 2.4.2 memory data formats .........................................................................................38 2.5 features of cpu core instructions....................................................................................40 2.5.1 instruction execution method..............................................................................40 2.5.2 cpu instruction addressing modes.....................................................................42 2.5.3 cpu instruction formats .....................................................................................45 2.6 instruction set ............................................................................................................. ......48 2.6.1 cpu instruction set based on functions .............................................................48 2.6.2 operation code map............................................................................................62 section 3 memory management unit (mmu) ................................................. 65 3.1 role of mmu................................................................................................................. ...65 3.1.1 mmu of this lsi ................................................................................................67 3.2 register descriptions ....................................................................................................... .72 3.2.1 page table entry register high (pteh) .............................................................72 3.2.2 page table entry register low (ptel) ..............................................................73 3.2.3 translation table base register (ttb) ...............................................................73 3.2.4 mmu control register (mmucr) .....................................................................73 3.3 tlb functions ............................................................................................................... ...75 3.3.1 configuration of the tlb ....................................................................................75 rev. 1.0, 11/02, page x of xxxviii 3.3.2 tlb indexing....................................................................................................... 77 3.3.3 tlb address comparison ................................................................................... 78 3.3.4 page management information............................................................................ 80 3.4 mmu functions............................................................................................................... .81 3.4.1 mmu hardware management ............................................................................. 81 3.4.2 mmu software management .............................................................................. 81 3.4.3 mmu instruction (ldtlb)................................................................................. 82 3.4.4 avoiding synonym problems .............................................................................. 83 3.5 mmu exceptions.............................................................................................................. 85 3.5.1 tlb miss exception ............................................................................................ 85 3.5.2 tlb protection violation exception ................................................................... 86 3.5.3 tlb invalid exception ........................................................................................ 87 3.5.4 initial page write exception................................................................................ 88 3.6 memory-mapped tlb...................................................................................................... 90 3.6.1 address array ...................................................................................................... 90 3.6.2 data array ........................................................................................................... 90 3.6.3 usage examples................................................................................................... 92 3.7 usage note.................................................................................................................. ...... 92 section 4 cache .................................................................................................93 4.1 features.................................................................................................................... ......... 93 4.1.1 cache structure.................................................................................................... 93 4.2 register descriptions ....................................................................................................... .95 4.2.1 cache control register 1 (ccr1) ....................................................................... 96 4.2.2 cache control register 2 (ccr2) ....................................................................... 97 4.2.3 cache control register 3 (ccr3) ....................................................................... 100 4.3 operation ................................................................................................................... ....... 101 4.3.1 searching the cache............................................................................................. 101 4.3.2 read access......................................................................................................... 102 4.3.3 prefetch operation ............................................................................................... 102 4.3.4 write access ........................................................................................................ 102 4.3.5 write-back buffer ............................................................................................... 103 4.3.6 coherency of cache and external memory ......................................................... 103 4.4 memory-mapped cache ................................................................................................... 104 4.4.1 address array ...................................................................................................... 104 4.4.2 data array ........................................................................................................... 105 4.4.3 usage examples................................................................................................... 107 4.5 usage note.................................................................................................................. ...... 108 section 5 exception handling ...........................................................................109 5.1 register descriptions ....................................................................................................... . 109 5.1.1 trapa exception register (tra) ..................................................................... 110 rev. 1.0, 11/02, page xi of xxxviii 5.1.2 exception event register (expevt)..................................................................111 5.1.3 interrupt event register (intevt) .....................................................................111 5.1.4 interrupt event register 2 (intevt2) ................................................................112 5.1.5 exception address register (tea)......................................................................112 5.2 exception handling function ...........................................................................................113 5.2.1 exception handling flow ....................................................................................113 5.2.2 exception vector addresses ................................................................................114 5.2.3 exception codes ..................................................................................................114 5.2.4 exception request and bl bit (multiple exception prevention) ........................114 5.2.5 exception source acceptance timing and priority .............................................115 5.3 individual exception operations.......................................................................................118 5.3.1 resets ...................................................................................................................1 18 5.3.2 general exceptions ..............................................................................................118 5.3.3 general exceptions (mmu exceptions)..............................................................121 5.4 usage notes ................................................................................................................. .....124 section 6 interrupt controller (intc) .............................................................. 125 6.1 features .................................................................................................................... .........125 6.2 input/output pins ........................................................................................................... ...127 6.3 register descriptions ....................................................................................................... .127 6.3.1 interrupt priority level setting registers a to h (ipra to iprh)......................128 6.3.2 interrupt control register 0 (icr0).....................................................................129 6.3.3 interrupt control register 1 (icr1).....................................................................130 6.3.4 interrupt control register 2 (icr2).....................................................................132 6.3.5 pint interrupt enable register (pinter)..........................................................132 6.3.6 interrupt request register 0 (irr0) ....................................................................133 6.3.7 interrupt request register 1 (irr1) ....................................................................134 6.3.8 interrupt request register 2 (irr2) ....................................................................135 6.4 interrupt sources ........................................................................................................... ....136 6.4.1 nmi interrupt.......................................................................................................136 6.4.2 irq interrupts ......................................................................................................136 6.4.3 irl interrupts ......................................................................................................137 6.4.4 pint interrupt......................................................................................................138 6.4.5 on-chip peripheral module interrupts ................................................................138 6.4.6 interrupt exception handling and priority...........................................................139 6.5 operation................................................................................................................... ........144 6.5.1 interrupt sequence ...............................................................................................144 6.5.2 multiple interrupts ...............................................................................................147 6.6 usage note.................................................................................................................. ......147 section 7 bus state controller (bsc)............................................................... 149 7.1 overview.................................................................................................................... .......149 7.1.1 features................................................................................................................14 9 rev. 1.0, 11/02, page xii of xxxviii 7.1.2 block diagram..................................................................................................... 150 7.2 pin configuration........................................................................................................... ... 151 7.3 area overview ............................................................................................................... ... 152 7.3.1 address map ........................................................................................................ 152 7.3.2 memory bus width ............................................................................................. 154 7.3.3 shadow space ...................................................................................................... 155 7.4 register descriptions ....................................................................................................... . 155 7.4.1 common control register (cmncr) ................................................................. 156 7.4.2 csn space bus control register (csnbcr) (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) .... 158 7.4.3 csn space wait control register (csnwcr) (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b).. 161 7.4.4 sdram control register (sdcr)...................................................................... 174 7.4.5 refresh timer control/status register (rtcsr)................................................ 177 7.4.6 refresh timer counter (rtcnt)........................................................................ 179 7.4.7 refresh time constant register (rtcor) ......................................................... 179 7.4.8 reset wait counter (rwtcnt).......................................................................... 180 7.5 endian/access size and data alignment.......................................................................... 180 7.6 normal space interface..................................................................................................... 1 87 7.6.1 basic timing........................................................................................................ 187 7.6.2 access wait control ............................................................................................ 192 7.6.3 csn assert period expansion .............................................................................. 194 7.7 address/data multiplex i/o interface............................................................................... 195 7.8 sdram interface ............................................................................................................. 198 7.8.1 sdram direct connection................................................................................. 198 7.8.2 address multiplexing .......................................................................................... 200 7.8.3 burst read............................................................................................................ 212 7.8.4 single read .......................................................................................................... 214 7.8.5 burst write........................................................................................................... 215 7.8.6 single write ......................................................................................................... 217 7.8.7 bank active ......................................................................................................... 218 7.8.8 refreshing............................................................................................................ 225 7.8.9 low-frequency mode.......................................................................................... 228 7.8.10 power-on sequence............................................................................................. 229 7.9 burst rom interface......................................................................................................... 231 7.10 byte-selection sram interface ....................................................................................... 233 7.11 wait between access cycles ............................................................................................ 235 7.12 bus arbitration............................................................................................................ ...... 235 7.13 others..................................................................................................................... ........... 237 section 8 direct memory access controller (dmac) .....................................239 8.1 features.................................................................................................................... ......... 239 8.2 input/output pins ........................................................................................................... ... 241 8.3 register descriptions ....................................................................................................... . 241 rev. 1.0, 11/02, page xiii of xxxviii 8.3.1 dma source address registers (sar) ...............................................................242 8.3.2 dma destination address registers (dar) .......................................................242 8.3.3 dma transfer count registers (dmatcr).......................................................243 8.3.4 dma channel control registers (chcr)...........................................................243 8.3.5 dma operation register (dmaor)...................................................................248 8.3.6 dma extended resource selectors 0, 1 (dmars0, dmars1) ........................250 8.4 operation................................................................................................................... ........252 8.4.1 transfer flow.......................................................................................................252 8.4.2 dma transfer requests ......................................................................................254 8.4.3 channel priority ...................................................................................................257 8.4.4 dma transfer types...........................................................................................260 8.4.5 number of bus cycle states and dreq pin sampling timing ..........................267 section 9 clock pulse generator (cpg)........................................................... 271 9.1 features .................................................................................................................... .........271 9.2 input/output pins ........................................................................................................... ...274 9.3 clock operating modes ....................................................................................................275 9.4 register descriptions ....................................................................................................... .279 9.4.1 frequency control register (frqcr).................................................................279 9.4.2 usb clock frequency control register (uclkcr) ..........................................281 9.4.3 usage notes .........................................................................................................281 9.5 changing frequency .........................................................................................................2 82 9.5.1 changing multiplication rate..............................................................................282 9.5.2 changing division ratio......................................................................................282 9.5.3 modification of clock operating mode...............................................................282 9.6 usage notes ................................................................................................................. .....283 section 10 watchdog timer (wdt)................................................................. 285 10.1 features ................................................................................................................... ..........285 10.2 register descriptions ...................................................................................................... ..286 10.2.1 watchdog timer counter (wtcnt)...................................................................286 10.2.2 watchdog timer control/status register (wtcsr)...........................................287 10.2.3 notes on register access.....................................................................................289 10.3 operation.................................................................................................................. .........290 10.3.1 canceling software standbys ..............................................................................290 10.3.2 changing frequency ............................................................................................291 10.3.3 using watchdog timer mode..............................................................................291 10.3.4 using interval timer mode..................................................................................291 section 11 power-down modes ....................................................................... 293 11.1 features ................................................................................................................... ..........293 11.2 input/output pins .......................................................................................................... ....295 11.3 register descriptions ...................................................................................................... ..295 rev. 1.0, 11/02, page xiv of xxxviii 11.3.1 standby control register (stbcr)..................................................................... 296 11.3.2 standby control register 2 (stbcr2)................................................................ 297 11.3.3 standby control register 3 (stbcr3)................................................................ 298 11.4 sleep mode ................................................................................................................. ...... 299 11.4.1 transition to sleep mode..................................................................................... 299 11.4.2 canceling sleep mode ......................................................................................... 299 11.5 software standby mode.................................................................................................... 30 0 11.5.1 transition to software standby mode ................................................................. 300 11.5.2 canceling software standby mode...................................................................... 300 11.6 module standby function................................................................................................. 301 11.6.1 transition to module standby function .............................................................. 301 11.6.2 canceling module standby function................................................................... 302 11.7 hardware standby mode .................................................................................................. 302 11.7.1 transition to hardware standby mode................................................................ 302 11.7.2 canceling hardware standby mode .................................................................... 302 11.8 timing of status pin changes ..................................................................................... 303 section 12 timer unit (tmu)...........................................................................309 12.1 features................................................................................................................... .......... 309 12.2 input/output pin........................................................................................................... ..... 311 12.3 register descriptions ...................................................................................................... .. 311 12.3.1 timer start register (tstr)................................................................................ 312 12.3.2 timer control registers (tcr) ........................................................................... 313 12.3.3 timer constant registers (tcor) ...................................................................... 317 12.3.4 timer counters (tcnt) ...................................................................................... 317 12.3.5 input capture register_2 (tcpr_2).................................................................... 317 12.4 operation .................................................................................................................. ........ 318 12.4.1 counter operation................................................................................................ 318 12.4.2 input capture function ........................................................................................ 320 12.5 interrupts................................................................................................................. .......... 321 12.5.1 status flag set timing......................................................................................... 321 12.5.2 status flag clear timing ..................................................................................... 321 12.5.3 interrupt sources and priorities............................................................................ 322 12.6 usage notes ................................................................................................................ ...... 322 12.6.1 writing to registers ............................................................................................. 322 12.6.2 reading registers ................................................................................................ 322 section 13 compare match timer (cmt) ........................................................323 13.1 features................................................................................................................... .......... 323 13.2 register descriptions ...................................................................................................... .. 324 13.2.1 compare match timer start register (cmstr) ................................................. 324 13.2.2 compare match timer control/status register (cmcsr) ................................. 325 rev. 1.0, 11/02, page xv of xxxviii 13.2.3 compare match counter (cmcnt) ....................................................................326 13.2.4 compare match constant register (cmcor) ....................................................326 13.3 operation.................................................................................................................. .........326 13.3.1 period count operation .......................................................................................326 13.3.2 cmcnt count timing........................................................................................327 13.3.3 compare match flag set timing.........................................................................327 section 14 16-bit timer pulse unit (tpu)....................................................... 329 14.1 features ................................................................................................................... ..........329 14.2 input/output pins .......................................................................................................... ....332 14.3 register descriptions ...................................................................................................... ..332 14.3.1 timer control registers (tcr) ...........................................................................334 14.3.2 timer mode registers (tmdr)...........................................................................337 14.3.3 timer i/o control registers (tior)....................................................................338 14.3.4 timer interrupt enable registers (tier).............................................................339 14.3.5 timer status registers (tsr) ..............................................................................340 14.3.6 timer counters (tcnt) ......................................................................................341 14.3.7 timer general registers (tgr)...........................................................................341 14.3.8 timer start register (tstr)................................................................................341 14.4 operation.................................................................................................................. .........342 14.4.1 overview..............................................................................................................342 14.4.2 basic functions....................................................................................................343 14.4.3 buffer operation ..................................................................................................346 14.4.4 pwm modes ........................................................................................................348 section 15 realtime clock (rtc) .................................................................... 351 15.1 features ................................................................................................................... ..........351 15.2 input/output pins .......................................................................................................... ....353 15.3 register descriptions ...................................................................................................... ..353 15.3.1 64-hz counter (r64cnt) ...................................................................................354 15.3.2 second counter (rseccnt) ..............................................................................354 15.3.3 minute counter (rmincnt) ..............................................................................355 15.3.4 hour counter (rhrcnt)....................................................................................355 15.3.5 day of week counter (rwkcnt)......................................................................356 15.3.6 date counter (rdaycnt) .................................................................................357 15.3.7 month counter (rmoncnt)..............................................................................357 15.3.8 year counter (ryrcnt) ....................................................................................358 15.3.9 second alarm register (rsecar) .....................................................................358 15.3.10 minute alarm register (rminar) .....................................................................359 15.3.11 hour alarm register (rhrar)...........................................................................360 15.3.12 day of week alarm register (rwkar) ............................................................361 15.3.13 date alarm register (rdayar) ........................................................................362 15.3.14 month alarm register (rmonar) ....................................................................363 rev. 1.0, 11/02, page xvi of xxxviii 15.3.15 year alarm register (ryrar)........................................................................... 364 15.3.16 rtc control register 1 (rcr1).......................................................................... 365 15.3.17 rtc control register 2 (rcr2).......................................................................... 366 15.3.18 rtc control register 3 (rcr3).......................................................................... 368 15.4 operation .................................................................................................................. ........ 369 15.4.1 initial settings of registers after power-on ........................................................ 369 15.4.2 setting time......................................................................................................... 369 15.4.3 reading the time................................................................................................. 370 15.4.4 alarm function .................................................................................................... 371 15.4.5 crystal oscillator circuit ..................................................................................... 372 15.5 notes for usage............................................................................................................ ..... 373 15.5.1 register writing during rtc count.................................................................... 373 15.5.2 use of realtime clock (rtc) periodic interrupts ............................................... 373 15.5.3 standby mode after register setting ................................................................... 373 section 16 serial communication interface with fifo (scif) ........................375 16.1 features................................................................................................................... .......... 375 16.2 input/output pins .......................................................................................................... .... 378 16.3 register descriptions ...................................................................................................... .. 379 16.3.1 receive shift register (scrsr).......................................................................... 380 16.3.2 receive fifo data register (scfrdr) ............................................................. 380 16.3.3 transmit shift register (sctsr) ........................................................................ 380 16.3.4 transmit fifo data register (scftdr) ............................................................ 381 16.3.5 serial mode register (scsmr)........................................................................... 381 16.3.6 serial control register (scscr)......................................................................... 385 16.3.7 fifo error count register (scfer)................................................................... 389 16.3.8 serial status register (scssr)............................................................................ 390 16.3.9 bit rate register (scbrr).................................................................................. 395 16.3.10 fifo control register (scfcr) ......................................................................... 398 16.3.11 fifo data count register (scfdr) ................................................................... 401 16.3.12 transmit data stop register (sctdsr) ............................................................. 401 16.4 operation .................................................................................................................. ........ 402 16.4.1 overview.............................................................................................................. 402 16.4.2 asynchronous mode ............................................................................................ 402 16.4.3 serial operation in asynchronous mode............................................................. 404 16.4.4 clock synchronous mode.................................................................................... 415 16.4.5 serial operation in clock synchronous mode..................................................... 416 16.5 scif interrupt sources and dmac.................................................................................. 426 16.6 notes on usage ............................................................................................................. .... 428 section 17 infrared data association module (irda) ......................................431 17.1 features................................................................................................................... .......... 431 rev. 1.0, 11/02, page xvii of xxxviii 17.2 input/output pins .......................................................................................................... ....432 17.3 register description....................................................................................................... ...432 17.3.1 irda mode register (scsmr_ir) .......................................................................432 17.4 operation.................................................................................................................. .........434 17.4.1 overview..............................................................................................................434 17.4.2 transmitting.........................................................................................................434 17.4.3 receiving .............................................................................................................435 17.4.4 data format specification ...................................................................................435 section 18 usb function module .................................................................... 437 18.1 features ................................................................................................................... ..........437 18.2 input/output pins .......................................................................................................... ....439 18.3 register descriptions ...................................................................................................... ..440 18.3.1 interrupt flag register 0 (ifr0) ..........................................................................441 18.3.2 interrupt flag register 1 (ifr1) ..........................................................................442 18.3.3 interrupt select register 0 (isr0)........................................................................443 18.3.4 interrupt select register 1 (isr1)........................................................................443 18.3.5 interrupt enable register 0 (ier0) ......................................................................444 18.3.6 interrupt enable register 1 (ier1) ......................................................................444 18.3.7 ep0i data register (epdr0i) ..............................................................................445 18.3.8 ep0o data register (epdr0o) ............................................................................445 18.3.9 ep0s data register (epdr0s) .............................................................................445 18.3.10 ep1 data register (epdr1) ................................................................................446 18.3.11 ep2 data register (epdr2) ................................................................................446 18.3.12 ep3 data register (epdr3) ................................................................................446 18.3.13 ep0o receive data size register (epsz0o)........................................................447 18.3.14 ep1 receive data size register (epsz1)............................................................447 18.3.15 trigger register (trg)........................................................................................448 18.3.16 data status register (dasts).............................................................................449 18.3.17 fifo clear register (fclr) ...............................................................................449 18.3.18 dma transfer setting register (dmar)............................................................450 18.3.19 endpoint stall register (epstl) .........................................................................453 18.3.20 transceiver control register (xvercr)............................................................453 18.4 operation.................................................................................................................. .........454 18.4.1 cable connection.................................................................................................454 18.4.2 cable disconnection ............................................................................................455 18.4.3 control transfer...................................................................................................455 18.4.4 ep1 bulk-out transfer (dual fifos)..................................................................461 18.4.5 ep2 bulk-in transfer (dual fifos) ....................................................................462 18.4.6 ep3 interrupt-in transfer.....................................................................................463 18.5 processing of usb standard commands and class/vendor commands..........................464 18.5.1 processing of commands transmitted by control transfer ................................464 18.6 stall operations........................................................................................................... ......465 rev. 1.0, 11/02, page xviii of xxxviii 18.6.1 overview.............................................................................................................. 465 18.6.2 forcible stall by application ............................................................................... 465 18.6.3 automatic stall by usb function module .......................................................... 467 18.7 dma transfer............................................................................................................... .... 468 18.7.1 overview.............................................................................................................. 468 18.7.2 dma transfer for endpoint 1 ............................................................................. 468 18.7.3 dma transfer for endpoint 2 ............................................................................. 469 18.8 example of usb external circuitry ................................................................................. 470 18.9 usage notes ................................................................................................................ ...... 473 18.9.1 receiving setup data........................................................................................... 473 18.9.2 clearing the fifo ................................................................................................ 473 18.9.3 overreading and overwriting the data registers ................................................ 473 18.9.4 assigning interrupt sources to ep0 ..................................................................... 474 18.9.5 clearing the fifo when dma transfer is enabled ........................................... 474 18.9.6 notes on tr interrupt .......................................................................................... 474 section 19 pin function controller ...................................................................475 19.1 overview................................................................................................................... ........ 475 19.2 register descriptions ...................................................................................................... .. 479 19.2.1 port a control register (pacr) ......................................................................... 480 19.2.2 port b control register (pbcr).......................................................................... 481 19.2.3 port c control register (pccr).......................................................................... 483 19.2.4 port d control register (pdcr) ......................................................................... 485 19.2.5 port e control register (pecr) .......................................................................... 487 19.2.6 port e control register 2 (pecr2) ..................................................................... 488 19.2.7 port f control register (pfcr)........................................................................... 489 19.2.8 port f control register 2 (pfcr2)...................................................................... 490 19.2.9 port g control register (pgcr) ......................................................................... 491 19.2.10 port h control register (phcr) ......................................................................... 493 19.2.11 port j control register (pjcr) ............................................................................ 494 19.2.12 port k control register (pkcr) ......................................................................... 496 19.2.13 port l control register (plcr) .......................................................................... 498 19.2.14 port m control register (pmcr) ........................................................................ 499 19.2.15 port n control register (pncr) ......................................................................... 500 19.2.16 port n control register 2 (pncr2) .................................................................... 502 19.2.17 port sc control register (scpcr) ..................................................................... 503 section 20 i/o ports...........................................................................................507 20.1 port a..................................................................................................................... ........... 507 20.1.1 register description............................................................................................. 507 20.1.2 port a data register (padr).............................................................................. 508 20.2 port b ..................................................................................................................... ........... 508 rev. 1.0, 11/02, page xix of xxxviii 20.2.1 register description.............................................................................................509 20.2.2 port b data register (pbdr) ..............................................................................509 20.3 port c ..................................................................................................................... ...........510 20.3.1 register description.............................................................................................510 20.3.2 port c data register (pcdr) ..............................................................................510 20.4 port d ..................................................................................................................... ...........511 20.4.1 register description.............................................................................................511 20.4.2 port d data register (pddr) ..............................................................................511 20.5 port e ..................................................................................................................... ...........513 20.5.1 register description.............................................................................................513 20.5.2 port e data register (pedr)...............................................................................513 20.6 port f..................................................................................................................... ............514 20.6.1 register description.............................................................................................514 20.6.2 port f data register (pfdr) ...............................................................................514 20.7 port g ..................................................................................................................... ...........515 20.7.1 register description.............................................................................................515 20.7.2 port g data register (pgdr) ..............................................................................516 20.8 port h ..................................................................................................................... ...........516 20.8.1 register description.............................................................................................517 20.8.2 port h data register (phdr) ..............................................................................517 20.9 port j ..................................................................................................................... ............518 20.9.1 register description.............................................................................................518 20.9.2 port j data register (pjdr).................................................................................518 20.10 port k .................................................................................................................... ............519 20.10.1 register description.............................................................................................519 20.10.2 port k data register (pkdr) ..............................................................................519 20.11 port l .................................................................................................................... ............520 20.11.1 register description.............................................................................................520 20.11.2 port l data register (pldr)...............................................................................521 20.12 port m .................................................................................................................... ...........521 20.12.1 register description.............................................................................................522 20.12.2 port m data register (pmdr).............................................................................522 20.13 port n .................................................................................................................... ............523 20.13.1 register description.............................................................................................523 20.13.2 port n data register (pndr) ..............................................................................523 20.14 sc port ................................................................................................................... ...........524 20.14.1 register description.............................................................................................525 20.14.2 port sc data register (scpdr) ..........................................................................525 section 21 a/d converter................................................................................. 527 21.1 features ................................................................................................................... ..........527 21.2 input/output pins .......................................................................................................... ....529 21.3 register descriptions ...................................................................................................... ..529 rev. 1.0, 11/02, page xx of xxxviii 21.3.1 a/d data registers a to d (addra to addrd) ............................................. 530 21.3.2 a/d control/status registers (adcsr).............................................................. 530 21.4 operation .................................................................................................................. ........ 533 21.4.1 single mode......................................................................................................... 533 21.4.2 multi mode .......................................................................................................... 533 21.4.3 scan mode ........................................................................................................... 534 21.4.4 input sampling and a/d conversion time ......................................................... 534 21.5 interrupts and dmac transfer request ........................................................................... 536 21.6 definitions of a/d conversion accuracy......................................................................... 536 21.7 usage notes ................................................................................................................ ...... 538 21.7.1 allowable signal-source impedance................................................................... 538 21.7.2 influence to absolute accuracy........................................................................... 538 21.7.3 setting analog input voltage .............................................................................. 538 21.7.4 notes on board design ........................................................................................ 539 21.7.5 notes on countermeasures to noise .................................................................... 539 section 22 user break controller......................................................................541 22.1 features................................................................................................................... .......... 541 22.2 register descriptions ...................................................................................................... .. 543 22.2.1 break address register a (bara) ..................................................................... 543 22.2.2 break address mask register a (bamra)........................................................ 544 22.2.3 break bus cycle register a (bbra).................................................................. 544 22.2.4 break address register b (barb)...................................................................... 545 22.2.5 break address mask register b (bamrb) ........................................................ 546 22.2.6 break data register b (bdrb) ........................................................................... 546 22.2.7 break data mask register b (bdmrb).............................................................. 547 22.2.8 break bus cycle register b (bbrb) .................................................................. 547 22.2.9 break control register (brcr) .......................................................................... 549 22.2.10 execution times break register (betr)............................................................ 552 22.2.11 branch source register (brsr).......................................................................... 552 22.2.12 branch destination register (brdr).................................................................. 553 22.2.13 break asid register a (basra)....................................................................... 553 22.2.14 break asid register b (basrb) ....................................................................... 554 22.3 operation .................................................................................................................. ........ 554 22.3.1 flow of the user break operation ....................................................................... 554 22.3.2 break on instruction fetch cycle......................................................................... 556 22.3.3 break on data access cycle................................................................................ 557 22.3.4 sequential break .................................................................................................. 558 22.3.5 value of saved program counter ........................................................................ 558 22.3.6 pc trace .............................................................................................................. 560 22.3.7 usage examples................................................................................................... 561 22.3.8 notes .................................................................................................................... 566 rev. 1.0, 11/02, page xxi of xxxviii section 23 hitachi user debugging interface (h-udi) ................................... 567 23.1 features ................................................................................................................... ..........567 23.2 input/output pins .......................................................................................................... ....568 23.3 register descriptions ...................................................................................................... ..569 23.3.1 bypass register (sdbpr) ...................................................................................569 23.3.2 instruction register (sdir) .................................................................................569 23.3.3 boundary scan register (sdbsr).......................................................................570 23.3.4 id register (sdid) ..............................................................................................577 23.4 operation.................................................................................................................. .........578 23.4.1 tap controller.....................................................................................................578 23.4.2 reset configuration .............................................................................................579 23.4.3 tdo output timing ............................................................................................579 23.4.4 h-udi reset ........................................................................................................580 23.4.5 h-udi interrupt ...................................................................................................580 23.5 boundary scan .............................................................................................................. ....581 23.5.1 supported instructions .........................................................................................581 23.5.2 points for attention..............................................................................................582 23.6 usage notes ................................................................................................................ ......583 23.7 advanced user debugger (aud) .....................................................................................583 section 24 list of registers .............................................................................. 585 24.1 register addresses (by functional module, in order of the corresponding section numbers)...........................586 24.2 register bits.............................................................................................................. ........595 24.3 register states in each operating mode...........................................................................614 section 25 electrical characteristics ................................................................ 623 25.1 absolute maximum ratings .............................................................................................623 25.2 dc characteristics ......................................................................................................... ...625 25.3 ac characteristics ......................................................................................................... ...630 25.3.1 clock timing .......................................................................................................631 25.3.2 control signal timing .........................................................................................636 25.3.3 ac bus timing ....................................................................................................638 25.3.4 basic timing........................................................................................................640 25.3.5 burst rom timing ..............................................................................................645 25.3.6 synchronous dram timing ...............................................................................646 25.3.7 dmac signal timing..........................................................................................668 25.3.8 tmu signal timing.............................................................................................669 25.3.9 rtc signal timing..............................................................................................670 25.3.10 16-bit timer pulse unit (tpu) signal timing....................................................670 25.3.11 scif module signal timing................................................................................671 25.3.12 usb module signal timing ................................................................................672 25.3.13 usb transceiver timing .....................................................................................673 rev. 1.0, 11/02, page xxii of xxxviii 25.3.14 port input/output timing .................................................................................... 674 25.3.15 h-udi related pin timing.................................................................................. 675 25.3.16 ac characteristics measurement conditions ...................................................... 677 25.4 a/d converter characteristics .......................................................................................... 678 appendix .........................................................................................................679 a. i/o port states in each processing state........................................................................... 679 b. package dimensions ......................................................................................................... 68 5 index .........................................................................................................687 rev. 1.0, 11/02, page xxiii of xxxviii figures section 1 overview figure 1.1 block diagram of sh7705 ........................................................................................... .6 figure 1.2 pin assignment (fp-208c).......................................................................................... ..7 figure 1.3 pin assignment (tbp-208a)......................................................................................... 8 section 2 cpu figure 2.1 processing state transitions...................................................................................... ..26 figure 2.2 logical address to external memory space mapping................................................29 figure 2.3 register configuration in each processing mode .......................................................31 figure 2.4 general registers................................................................................................. ........33 figure 2.5 system registers and program counter ......................................................................34 figure 2.6 control register configuration ...................................................................................3 7 figure 2.7 data format on memory (big endian mode) .............................................................38 figure 2.8 data format on memory (little endian mode)...........................................................39 section 3 memory management unit (mmu) figure 3.1 mmu functions ..................................................................................................... .....66 figure 3.2 virtual address space (mmucr.at = 1)..................................................................68 figure 3.3 virtual address space (mmucr.at = 0)..................................................................69 figure 3.4 p4 area ........................................................................................................... .............69 figure 3.5 external memory space ............................................................................................. .70 figure 3.6 overall configuration of the tlb ...............................................................................75 figure 3.7 virtual address and tlb structure.............................................................................76 figure 3.8 tlb indexing (ix = 1) ............................................................................................. ...77 figure 3.9 tlb indexing (ix = 0) ............................................................................................. ...78 figure 3.10 objects of address comparison ................................................................................79 figure 3.11 operation of ldtlb instruction...............................................................................82 figure 3.12 synonym problem (32-kbyte cache).........................................................................84 figure 3.13 mmu exception generation flowchart ....................................................................89 figure 3.14 specifying address and data for memory-mapped tlb access .............................91 section 4 cache figure 4.1 cache structure (32-kbyte mode) ...............................................................................94 figure 4.2 cache search scheme............................................................................................... .101 figure 4.3 write-back buffer configuration..............................................................................103 figure 4.4 specifying address and data for memory-mapped cache access (32-kbyte mode) ..................................................................................................... ...106 section 5 exception handling figure 5.1 register bit configuration........................................................................................ .110 section 6 interrupt controller (intc) figure 6.1 block diagram of intc ............................................................................................1 26 rev. 1.0, 11/02, page xxiv of xxxviii figure 6.2 example of irl interrupt connection....................................................................... 137 figure 6.3 interrupt operation flowchart ................................................................................... 14 6 section 7 bus state controller (bsc) figure 7.1 bsc functional block diagram................................................................................ 150 figure 7.2 address space ..................................................................................................... ...... 154 figure 7.3 continuous access for normal space (no wait, wm bit in csnwcr = 1, 16-bit bus width, longword access, no wait state between cycles) .................... 188 figure 7.4 continuous access for normal space (no wait, one wait state between cycles).. 189 figure 7.5 example of 32-bit data-width sram connection .................................................. 190 figure 7.6 example of 16-bit data-width sram connection .................................................. 191 figure 7.7 example of 8-bit data-width sram connection .................................................... 191 figure 7.8 wait timing for normal space access (software wait only) ................................. 192 figure 7.9 wait state timing for normal space access (wait state insertion by wait signal) ..................................................................... 193 figure 7.10 csn assert period expansion.................................................................................. 194 figure 7.11 access timing for mpx space (address cycle no wait, data cycle no wait) ... 195 figure 7.12 access timing for mpx space (address cycle wait 1, data cycle no wait) ...... 196 figure 7.13 access timing for mpx space (address cycle access wait 1, data cycle wait 1, external wait 1) ...................................................................... 197 figure 7.14 example of 64-mbit synchronous dram connection (32-bit data bus) ............ 199 figure 7.15 example of 64-mbit synchronous dram (16-bit data bus)................................ 200 figure 7.16 synchronous dram burst read wait specification timing (auto pre-charge) ... 213 figure 7.17 basic timing for single read (auto pre-charge).................................................... 214 figure 7.18 basic timing for synchronous dram burst write (auto pre-charge).................. 216 figure 7.19 basic timing for single write (auto pre-charge)................................................... 217 figure 7.20 burst read timing (no auto precharge) ................................................................ 219 figure 7.21 burst read timing (bank active, same row address).......................................... 220 figure 7.22 burst read timing (bank active, different row addresses) ................................ 221 figure 7.23 single write timing (no auto precharge).............................................................. 222 figure 7.24 single write timing (bank active, same row address) ....................................... 223 figure 7.25 single write timing (bank active, different row addresses) .............................. 224 figure 7.26 auto-refresh timing.............................................................................................. . 226 figure 7.27 self-refresh timing .............................................................................................. .. 227 figure 7.28 low-frequency mode access timing .................................................................... 228 figure 7.29 synchronous dram mode write timing (based on jedec) ............................... 231 figure 7.30 burst rom access (bus width 8 bits, access size 32 bits (number of burst 4), access wait for the 1st time 2, access wait for 2nd time and after 1) ...................... 232 figure 7.31 byte-selection sram basic access timing .......................................................... 233 figure 7.32 example of connection with 32-bit data-width byte-selection sram ............... 234 figure 7.33 example of connection with 16-bit data-width byte-selection sram ............... 234 figure 7.34 bus arbitration .................................................................................................. ...... 237 rev. 1.0, 11/02, page xxv of xxxviii section 8 direct memory access controller (dmac) figure 8.1 block diagram of dmac .........................................................................................240 figure 8.2 dmac transfer flowchart .......................................................................................253 figure 8.3 round-robin mode .................................................................................................. .258 figure 8.4 channel priority in round-robin mode....................................................................259 figure 8.5 data flow of dual address mode .............................................................................261 figure 8.6 example of dma transfer timing in dual mode (source: ordinary memory, destination: ordinary memory) .......................................262 figure 8.7 data flow in single address mode...........................................................................263 figure 8.8 example of dma transfer timing in single address mode....................................263 figure 8.9 dma transfer example in cycle-steal normal mode (dual address, dreq low level detection) .................................................................264 figure 8.10 example of dma transfer in cycle steal intermittent mode (dual address, dreq low level detection) ...............................................................265 figure 8.11 dma transfer example in burst mode (dual address, dreq low level detection) ...............................................................265 figure 8.12 bus state when multiple channels are operating ...................................................267 figure 8.13 example of dreq input detection in cycle steal mode edge detection..............267 figure 8.14 example of dreq input detection in cycle steal mode level detection .............268 figure 8.15 example of dreq input detection in burst mode edge detection .......................268 figure 8.16 example of dreq input detection in burst mode level detection.......................269 figure 8.17 example of dma transfer end signal (in cycle steal level detection)...................269 figure 8.18 bsc ordinary memory access (no wait, idle cycle 1, longword access to 16-bit device) ........................................270 section 9 clock pulse generator (cpg) figure 9.1 block diagram of clock pulse generator .................................................................272 figure 9.2 points for attention when using crystal resonator..................................................283 figure 9.3 points for attention when using pll oscillator circuit...........................................284 section 10 watchdog timer (wdt) figure 10.1 block diagram of wdt ..........................................................................................286 figure 10.2 writing to wtcnt and wtcsr ............................................................................289 section 11 power-down modes figure 11.1 canceling standby mode with stby bit in stbcr...............................................301 figure 11.2 power-on reset status output...........................................................................303 figure 11.3 manual reset status output ...............................................................................303 figure 11.4 canceling software standby by interrupt status output....................................304 figure 11.5 canceling software standby by power-on reset status output .......................304 figure 11.6 canceling software standby by manual reset status output............................305 figure 11.7 canceling sleep by interrupt status output .......................................................305 figure 11.8 canceling sleep by power-on reset status output ...........................................306 figure 11.9 canceling sleep by manual reset status output ...............................................306 rev. 1.0, 11/02, page xxvi of xxxviii figure 11.10 hardware standby mode (when ca goes low in normal operation)................ 307 figure 11.11 hardware standby mode timing (when ca goes low during wdt operation while standby mode is canceled)............................................... 307 section 12 timer unit (tmu) figure 12.1 tmu block diagram............................................................................................... 3 10 figure 12.2 setting count operation .......................................................................................... 318 figure 12.3 auto-reload count operation................................................................................. 319 figure 12.4 count timing when internal clock is operating..................................................... 319 figure 12.5 count timing when external clock is operating (both edges detected) .............. 320 figure 12.6 operation timing when using input capture function (using tclk rising edge) ..................................................................................... 320 figure 12.7 unf set timing ................................................................................................... ... 321 figure 12.8 status flag clear timing......................................................................................... 321 section 13 compare match timer (cmt) figure 13.1 cmt block diagram............................................................................................... 3 23 figure 13.2 counter operation ................................................................................................ ... 326 figure 13.3 count timing ..................................................................................................... ..... 327 figure 13.4 cmf set timing................................................................................................... ... 327 section 14 16-bit timer pulse unit (tpu) figure 14.1 block diagram of tpu............................................................................................ 3 31 figure 14.2 example of counter operation setting procedure .................................................. 343 figure 14.3 free-running counter operation ............................................................................ 344 figure 14.4 periodic counter operation..................................................................................... 34 4 figure 14.5 example of setting procedure for waveform output by compare match.............. 345 figure 14.6 example of 0 output/1 output operation ............................................................... 345 figure 14.7 example of toggle output operation ..................................................................... 346 figure 14.8 compare match buffer operation........................................................................... 346 figure 14.9 example of buffer operation setting procedure..................................................... 347 figure 14.10 example of buffer operation ................................................................................ 348 figure 14.11 example of pwm mode setting procedure .......................................................... 349 figure 14.12 example of pwm mode operation (1) ................................................................. 350 figure 14.13 examples of pwm mode operation (2)................................................................ 350 section 15 realtime clock (rtc) figure 15.1 rtc block diagram................................................................................................ 352 figure 15.2 setting time ..................................................................................................... ....... 369 figure 15.3 reading the time ................................................................................................. ... 370 figure 15.4 using the alarm function ....................................................................................... 37 1 figure 15.5 example of crystal oscillator circuit connection .................................................. 372 figure 15.6 using periodic interrupt function ........................................................................... 373 section 16 serial communication interface with fifo (scif) figure 16.1 block diagram of scif........................................................................................... 3 77 rev. 1.0, 11/02, page xxvii of xxxviii figure 16.2 sample scif initialization flowchart .....................................................................406 figure 16.3 sample serial transmission flowchart ...................................................................407 figure 16.4 example of transmit operation (example with 8-bit data, parity, one stop bit).....................................................409 figure 16.5 example of transmit data stop function ...............................................................409 figure 16.6 transmit data stop function flowchart..................................................................410 figure 16.7 sample serial reception flowchart (1)...................................................................411 figure 16.8 sample serial reception flowchart (2)...................................................................412 figure 16.9 example of scif receive operation (example with 8-bit data, parity, one stop bit).....................................................414 figure 16.10 cts control operation..........................................................................................414 figure 16.11 rts control operation..........................................................................................415 figure 16.12 data format in clock synchronous communication ............................................416 figure 16.13 sample scif initialization flowchart (1) (transmission).....................................418 figure 16.13 sample scif initialization flowchart (2) (reception)..........................................419 figure 16.13 sample scif initialization flowchart (3) (simultaneous transmission and reception).........................................................420 figure 16.14 sample serial transmission flowchart (1) (first transmission after initialization)..................................................................421 figure 16.14 sample serial transmission flowchart (2) (second and subsequent transmission).................................................................421 figure 16.15 sample serial reception flowchart (1) (first reception after initialization) .......422 figure 16.15 sample serial reception flowchart (2) (second and subsequent reception).......423 figure 16.16 sample simultaneous serial transmission and reception flowchart (1) (first transfer after initialization) .........................................................................42 4 figure 16.16 sample simultaneous serial transmission and reception flowchart (2) (second and subsequent transfer).........................................................................425 section 17 infrared data association module (irda) figure 17.1 block diagram of irda...........................................................................................4 31 section 18 usb function module figure 18.1 block diagram of usb............................................................................................4 38 figure 18.2 cable connection operation....................................................................................454 figure 18.3 cable disconnection operation...............................................................................455 figure 18.4 transfer stages in control transfer ........................................................................455 figure 18.5 setup stage operation ............................................................................................ .456 figure 18.6 data stage (control-in) operation ..........................................................................457 figure 18.7 data stage (control-out) operation........................................................................458 figure 18.8 status stage (control-in) operation ........................................................................459 figure 18.9 status stage (control-out) operation .....................................................................460 figure 18.10 ep1 bulk-out transfer operation .........................................................................461 figure 18.11 ep2 bulk-in transfer operation............................................................................462 figure 18.12 operation of ep3 interrupt-in transfer .................................................................463 rev. 1.0, 11/02, page xxviii of xxxviii figure 18.13 forcible stall by application................................................................................. 46 6 figure 18.14 automatic stall by usb function module............................................................ 467 figure 18.15 rdfn bit operation for ep1 ................................................................................ 468 figure 18.16 pkte bit operation for ep2................................................................................. 469 figure 18.17 example of usb function module external circuitry (internal transceiver)...... 471 figure 18.18 example of usb function module external circuitry (external transceiver)..... 472 figure 18.19 tr interrupt flag set timing ................................................................................ 474 section 20 i/o ports figure 20.1 port a ........................................................................................................... ........... 507 figure 20.2 port b ........................................................................................................... ........... 508 figure 20.3 port c ........................................................................................................... ........... 510 figure 20.4 port d ........................................................................................................... ........... 511 figure 20.5 port e........................................................................................................... ............ 513 figure 20.6 port f........................................................................................................... ............ 514 figure 20.7 port g ........................................................................................................... ........... 515 figure 20.8 port h ........................................................................................................... ........... 516 figure 20.9 port j........................................................................................................... ............. 518 figure 20.10 port k .......................................................................................................... .......... 519 figure 20.11 port l.......................................................................................................... ........... 520 figure 20.12 port m.......................................................................................................... .......... 521 figure 20.13 port n .......................................................................................................... .......... 523 figure 20.14 sc port ......................................................................................................... ......... 524 section 21 a/d converter figure 21.1 block diagram of a/d converter ........................................................................... 528 figure 21.2 a/d conversion timing .......................................................................................... 53 5 figure 21.3 definitions of a/d conversion accuracy .............................................................. 537 figure 21.4 definitions of a/d conversion accuracy ............................................................... 537 figure 21.5 analog input circuit example................................................................................. 538 figure 21.6 example of analog input protection circuit ........................................................... 539 figure 21.7 analog input pin equivalent circuit ....................................................................... 540 section 22 user break controller figure 22.1 block diagram of user break controller................................................................ 542 section 23 hitachi user debugging interface (h-udi) figure 23.1 block diagram of h-udi........................................................................................ 567 figure 23.2 tap controller state transitions ............................................................................ 578 figure 23.3 h-udi data transfer timing .................................................................................. 580 figure 23.4 h-udi reset...................................................................................................... ...... 580 section 25 electrical characteristics figure 25.1 power on/off sequence .......................................................................................... 62 4 figure 25.2 extal clock input timing ................................................................................... 632 figure 25.3 ckio clock input timing....................................................................................... 632 rev. 1.0, 11/02, page xxix of xxxviii figure 25.4 ckio clock output timing ....................................................................................632 figure 25.5 power-on oscillation settling time .......................................................................633 figure 25.6 oscillation settling time at standby return (return by reset)..............................633 figure 25.7 oscillation settling time at standby return (return by nmi) ...............................633 figure 25.8 oscillation settling time at standby return (return by irq5 to irq0, pint15 to pint0, and irl3 to irl0 ) ..........................634 figure 25.9 pll synchronization settling time by reset or nmi ............................................634 figure 25.10 pll synchronization settling time by irq/irl, pint interrupts.......................635 figure 25.11 pll synchronization settling time when frequency multiplication ratio modified ................................................................................................. .....635 figure 25.12 reset input timing .............................................................................................. ..637 figure 25.13 interrupt signal input timing................................................................................637 figure 25.14 bus release timing.............................................................................................. .637 figure 25.15 pin drive timing at standby .................................................................................638 figure 25.16 basic bus cycle (no wait) ...................................................................................640 figure 25.17 basic bus cycle (one software wait) ..................................................................641 figure 25.18 basic bus cycle (one external wait) ...................................................................642 figure 25.19 basic bus cycle (one software wait, external wait enabled (wm bit = 0), no idle cycle setting)......................................................................................... ..643 figure 25.20 address/data multiplex i/o bus cycle (three address cycles, one software wait, one external wait) .........................644 figure 25.21 burst rom read cycle (one access wait, one external wait, one burst wait, two bursts) ..................645 figure 25.22 synchronous dram single read bus cycle (auto precharge, cas latency = 2, trcd = 1 cycle, trp = 1 cycle)................646 figure 25.23 synchronous dram single read bus cycle (auto precharge, cas latency = 2, trcd = 2 cycle, trp = 2 cycle)................647 figure 25.24 synchronous dram burst read bus cycle (single read 4), (auto precharge, cas latency = 2, trcd = 1 cycle, trp = 2 cycle)................648 figure 25.25 synchronous dram burst read bus cycle (single read 4), (auto precharge, cas latency = 2, trcd = 2 cycle, trp = 1 cycle)................649 figure 25.26 synchronous dram single write bus cycle (auto precharge, trwl = 2 cycle) ......................................................................650 figure 25.27 synchronous dram single write bus cycle (auto precharge, trcd = 3 cycle, trwl = 2 cycle) .........................................651 figure 25.28 synchronous dram burst write bus cycle (single write 4), (auto precharge, trcd = 1 cycle, trwl = 2 cycle) .........................................652 figure 25.29 synchronous dram burst write bus cycle (single write 4), (auto precharge, trcd = 2 cycle, trwl = 2 cycle) .........................................653 figure 25.30 synchronous dram burst read bus cycle (single read 4) (bank active mode: actv + read commands, cas latency = 2, trcd = 1 cycle) ................................................................................................ ..654 rev. 1.0, 11/02, page xxx of xxxviii figure 25.31 synchronous dram burst read bus cycle (single read 4) (bank active mode: read command, same row address, cas latency = 2, trcd = 1 cycle) .................................................................... 655 figure 25.32 synchronous dram burst read bus cycle (single read 4) (bank active mode: pre + actv + read commands, different row address, cas latency = 2, trcd = 1 cycle) ............................. 656 figure 25.33 synchronous dram burst write bus cycle (single write 4) (bank active mode: actv + write commands, trcd = 1 cycle, trwl = 1 cycle) ................................................................................................ . 657 figure 25.34 synchronous dram burst write bus cycle (single write 4) (bank active mode: write command, same row address, trcd = 1 cycle, trwl = 1 cycle) .................................................................... 658 figure 25.35 synchronous dram burst write bus cycle (single write 4) (bank active mode: pre + actv + write commands, different row address, trcd = 1 cycle, trwl = 1 cycle) ............................. 659 figure 25.36 synchronous dram auto-refresh timing (trp = 2 cycle)............................... 660 figure 25.37 synchronous dram self-refresh timing (trp = 2 cycle) ................................ 661 figure 25.38 synchronous dram mode register write timing (trp = 2 cycle)................... 662 figure 25.39 access timing in low-frequency mode (auto precharge).................................. 664 figure 25.40 synchronous dram auto-refresh timing (trp = 2 cycle, low-frequency mode) ............................................................... 665 figure 25.41 synchronous dram self-refresh timing (trp = 2 cycle, low-frequency mode) ............................................................... 666 figure 25.42 synchronous dram mode register write timing (trp = 2 cycle, low-frequency mode) ............................................................... 667 figure 25.43 dreq input timing .............................................................................................. 6 68 figure 25.44 dack, tend output timing .............................................................................. 668 figure 25.45 tclk input timing .............................................................................................. 6 69 figure 25.46 tclk clock input timing.................................................................................... 669 figure 25.47 oscillation settling time when rtc crystal oscillator is turned on ................. 670 figure 25.48 tpu output timing............................................................................................... 670 figure 25.49 sck input clock timing....................................................................................... 671 figure 25.50 scif input/output timing in clock synchronous mode...................................... 672 figure 25.51 usb clock timing................................................................................................ 672 figure 25.52 oscillation settling time when usb crystal oscillator is turned on ................. 673 figure 25.53 i/o port timing ................................................................................................. .... 674 figure 25.54 tck input timing................................................................................................ . 675 figure 25.55 trst input timing (reset hold).......................................................................... 676 figure 25.56 h-udi data transfer timing ................................................................................ 676 figure 25.57 asemd0 input timing......................................................................................... 676 figure 25.58 output load circuit............................................................................................. .. 677 rev. 1.0, 11/02, page xxxi of xxxviii appendix figure b.1 package dimensions (fp-208c) ...............................................................................685 figure b.2 package dimensions (tbp-208a) ............................................................................686 rev. 1.0, 11/02, page xxxii of xxxviii rev. 1.0, 11/02, page xxxiii of xxxviii tables section 1 overview table 1.1 sh7705 features....................................................................................................... ....2 table 1.2 pin functions ......................................................................................................... .......9 table 1.3 pin functions ......................................................................................................... .....17 section 2 cpu table 2.1 logical address space................................................................................................2 8 table 2.2 register initial values............................................................................................... ..30 table 2.3 addressing modes and effective addresses for cpu instructions.............................42 table 2.4 cpu instruction formats ............................................................................................45 table 2.5 cpu instruction types................................................................................................4 8 table 2.6 data transfer instructions...........................................................................................5 2 table 2.7 arithmetic operation instructions...............................................................................54 table 2.8 logic operation instructions ......................................................................................56 table 2.9 shift instructions.................................................................................................... .....57 table 2.10 branch instructions .................................................................................................5 8 table 2.11 system control instructions....................................................................................59 table 2.12 operation code map...............................................................................................62 section 3 memory management unit (mmu) table 3.1 access states designated by d, c, and pr bits .........................................................80 section 4 cache table 4.1 number of entries and size/way in each cache size................................................93 table 4.2 lru and way replacement (when cache locking mechanism is disabled)............95 table 4.3 way replacement when a pref instruction misses the cache .................................99 table 4.4 way replacement when instructions other than the pref instruction miss the cache .........................................................................99 table 4.5 lru and way replacement (when w2lock = 1 and w3lock = 0) .....................99 table 4.6 lru and way replacement (when w2lock = 0 and w3lock = 1) .....................99 table 4.7 lru and way replacement (when w2lock = 1 and w3lock = 1) ...................100 table 4.8 address format based on size of cache to be assigned to memory.......................106 section 5 exception handling table 5.1 exception event vectors...........................................................................................116 section 6 interrupt controller (intc) table 6.1 pin configuration..................................................................................................... .127 table 6.2 interrupt sources and ipra to iprh ........................................................................128 table 6.3 irl3 to irl0 pins and interrupt levels....................................................................138 table 6.4 interrupt exception handling sources and priority (irq mode) .............................140 rev. 1.0, 11/02, page xxxiv of xxxviii section 7 bus state controller (bsc) table 7.1 pin configuration..................................................................................................... . 151 table 7.2 physical address space map .................................................................................... 152 table 7.3 correspondence between external pins (md3 and md4) and memory size........... 154 table 7.4 32-bit external device/big endian access and data alignment ............................. 181 table 7.5 16-bit external device/big endian access and data alignment ............................. 182 table 7.6 8-bit external device/big endian access and data alignment ............................... 183 table 7.7 32-bit external device/little endian access and data alignment .......................... 184 table 7.8 16-bit external device/little endian access and data alignment .......................... 185 table 7.9 8-bit external device/little endian access and data alignment ............................ 186 table 7.10 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (1)-1..................................................................... 201 table 7.11 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (2)-1..................................................................... 203 table 7.12 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (3) ........................................................................ 205 table 7.13 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (4)-1..................................................................... 206 table 7.14 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (5)-1..................................................................... 208 table 7.15 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (6)-1..................................................................... 210 table 7.16 relationship between access size and number of bursts.................................... 212 table 7.17 access address in sdram mode register write ............................................... 229 table 7.18 relationship between bus width, access size, and number of bursts................ 232 section 8 direct memory access controller (dmac) table 8.1 pin configuration..................................................................................................... . 241 table 8.2 transfer request sources ......................................................................................... 251 table 8.3 selecting external request modes with rs bits ...................................................... 254 table 8.4 selecting external request detection with dl, ds bits .......................................... 255 table 8.5 selecting external request detection with do bit .................................................. 255 table 8.6 selecting on-chip peripheral module request modes with rs3 to rs0 bits ......... 256 table 8.7 selecting on-chip peripheral module request modes with rs3 to rs0 bits ......... 256 table 8.8 supported dma transfers........................................................................................ 260 table 8.9 relationship of request modes and bus modes by dma transfer category ......... 266 section 9 clock pulse generator (cpg) table 9.1 clock pulse generator pins and functions ............................................................... 274 table 9.2 clock operating modes ............................................................................................ 275 table 9.3 possible combination of clock modes and frqcr values .................................... 276 section 11 power-down modes table 11.1 states of power-down modes............................................................................... 294 rev. 1.0, 11/02, page xxxv of xxxviii table 11.2 pin configuration..................................................................................................29 5 section 12 timer unit (tmu) table 12.1 pin configuration..................................................................................................31 1 table 12.2 tmu interrupt sources .........................................................................................322 section 14 16-bit timer pulse unit (tpu) table 14.1 tpu functions ......................................................................................................33 0 table 14.2 pin configuration..................................................................................................33 2 table 14.3 tpu clock sources...............................................................................................335 table 14.4 tpsc2 to tpsc0 (1).............................................................................................335 table 14.4 tpsc2 to tpsc0 (2).............................................................................................335 table 14.4 tpsc2 to tpsc0 (3).............................................................................................336 table 14.4 tpsc2 to tpsc0 (4).............................................................................................336 table 14.5 ioa2 to ioa0 .......................................................................................................33 8 table 14.6 register combinations in buffer operation..........................................................346 section 15 realtime clock (rtc) table 15.1 pin configuration..................................................................................................35 3 table 15.2 recommended oscillator circuit constants (recommended values)..................372 section 16 serial communication interface with fifo (scif) table 16.1 pin configuration..................................................................................................37 8 table 16.2 scsmr settings for serial transfer format selection.........................................403 table 16.3 serial transfer formats.........................................................................................404 table 16.4 scif interrupt sources..........................................................................................427 section 17 infrared data association module (irda) table 17.1 pin configuration..................................................................................................43 2 section 18 usb function module table 18.1 pin configuration..................................................................................................43 9 table 18.2 command decoding on application side.............................................................464 section 19 pin function controller table 19.1 multiplex pins....................................................................................................... 475 section 20 i/o ports table 20.1 port a data register (padr) read/write operations .........................................508 table 20.2 port b data register (pbdr) read/write operations..........................................509 table 20.3 port c data register (pcdr) read/write operations..........................................511 table 20.4 port d data register (pddr) read/write operations .........................................512 table 20.5 port e data register (pedr) read/write operations ..........................................514 table 20.6 port f data register (pfdr) read/write operations...........................................515 table 20.7 port g data register (pgdr) read/write operations .........................................516 table 20.8 port h data register (phdr) read/write operations .........................................517 table 20.9 port j data register (pjdr) read/write operations............................................519 rev. 1.0, 11/02, page xxxvi of xxxviii table 20.10 port k data register (pkdr) read/write operations ......................................... 520 table 20.11 port l data register (pldr) read/write operation............................................ 521 table 20.12 port m data register (pmdr) read/write operations........................................ 522 table 20.13 port n data register (pndr) read/write operations ......................................... 524 table 20.14 sc port data register (scpdr) read/write operations ..................................... 525 section 21 a/d converter table 21.1 pin configuration.................................................................................................. 52 9 table 21.2 analog input channels and a/d data registers................................................... 530 table 21.3 a/d conversion time (single mode)................................................................... 535 table 21.4 a/d conversion time (multi mode and scan mode) .......................................... 535 table 21.5 a/d converter interrupt source............................................................................ 536 table 21.6 analog input pin ratings...................................................................................... 540 section 22 user break controller table 22.1 data access cycle addresses and operand size comparison conditions ........... 557 section 23 hitachi user debugging interface (h-udi) table 23.1 pin configuration.................................................................................................. 56 8 table 23.2 h-udi commands ................................................................................................ 570 table 23.3 sh7705 pins and boundary scan register bits.................................................... 571 table 23.4 reset configuration .............................................................................................. 579 section 25 electrical characteristics table 25.1 absolute maximum ratings ................................................................................. 623 table 25.2 dc characteristics (1) [common items] .............................................................. 625 table 25.2 dc characteristics (2-a) [excluding usb-related pins]...................................... 627 table 25.2 dc characteristics (2-b) [usb-related pins*]..................................................... 628 table 25.2 dc characteristics (2-c) [usb transceiver-related pins* 1 ]................................ 629 table 25.3 permitted output current values.......................................................................... 629 table 25.4 maximum operating frequencies......................................................................... 630 table 25.5 clock timing ........................................................................................................ 6 31 table 25.6 control signal timing .......................................................................................... 636 table 25.7 bus timing (1)...................................................................................................... 6 38 table 25.8 bus timing (2)...................................................................................................... 6 63 table 25.9 dmac signal timing........................................................................................... 668 table 25.10 tmu signal timing.............................................................................................. 669 table 25.11 rtc signal timing............................................................................................... 670 table 25.12 16-bit timer pulse unit (tpu) signal timing..................................................... 670 table 25.13 scif module signal timing................................................................................. 671 table 25.14 usb module clock timing .................................................................................. 672 table 25.15 usb transceiver timing ...................................................................................... 673 table 25.16 port input/output timing ..................................................................................... 674 table 25.17 h-udi related pin timing................................................................................... 675 table 25.18 a/d converter characteristics .............................................................................. 678 rev. 1.0, 11/02, page xxxvii of xxxviii appendix table a.1 i/o port states in each processing state...............................................................679 rev. 1.0, 11/02, page xxxviii of xxxviii rev. 1.0, 11/02, page 1 of 690 section 1 overview 1.1 sh7705 features this lsi is a microprocessor that integrates a 32-bit risc-type superh architecture cpu as its core, together with 32-kbyte cache memory as well as peripheral functions required for system configuration such as an interrupt controller. high-speed data transfers can be formed by an on-chip direct memory access controller (dmac), and an external memory access support function enables direct connection to different kinds of memory. this lsi also includes powerful peripheral functions that are essential to system configuration, such as usb (function) functionality and a serial interface with a large fifo. a powerful built-in power-management function keeps power consumption low, even during high-speed operation. this lsi is ideal for use in electronic devices such as those for applications that require both high speeds and low power consumption. the features of this lsi are listed in table 1.1. rev. 1.0, 11/02, page 2 of 690 table 1.1 sh7705 features item features cpu ? original hitachi superh architecture ? compatible with sh-1, sh-2 and sh-3 at object code level ? 32-bit internal data bus ? general-registers sixteen 32-bit general registers (eight 32-bit shadow registers) five 32-bit control registers four 32-bit system registers ? risc-type instruction set instruction length: 16-bit fixed length and improved code efficiency load/store architecture delayed branch instructions instruction set based on c language ? instruction execution time: one instruction/cycle for basic instructions ? logical address space: 4 gbytes ? five-stage pipeline memory management unit (mmu) ? 4 gbytes of address space, 256 address space identifiers (asid: 8 bits) ? page unit sharing ? supports multiple page sizes: 1 kbyte or 4 kbytes ? 128-entry, 4-way set associative tlb ? supports software selection of replacement method and random- replacement algorithms ? contents of tlb are directly accessible by address mapping cache memory ? 32-kbyte cache, mixture of instructions and data ? 512 entries, 4-way set associative, 16-byte block length ? write-back, write-through, lru replacement algorithm ? 1-stage write-back buffer interrupt controller (intc) ? seven external interrupt pins (nmi, irq5 to irq0) ? on-chip peripheral interrupt: priority level is independently selected for each module rev. 1.0, 11/02, page 3 of 690 item features bus state controller (bsc) ? physical address space is divided into eight areas: area 0, areas 2 to 4; each a maximum of 64 mbytes, and areas 5a, 5b, 6a, 6b; each a maximum of 32 mbytes ? the following features are settable for each area bus size (8, 16, or 32 bits). the supported bus size differs for each area. number of access wait cycles (numbers of wait-state cycles during reading and writing are independently selectable for some areas.) setting of idle wait cycles (for the same area or different area) specifying the memory type to be connected to each area enables direct connection to sram, byte selection sram, sdram, and burst rom. some areas support address/data multiplex i/o (mpx). outputs chip select signal ( cs0 , cs2 to cs4 , cs5a / b , cs6a / b ) for corresponding area (programs are used to select the cs assert/negate timing.) ? sdram refresh function supports auto-refresh and self-refresh modes ? sdram burst access function different sdram can be connected to area 2 or area 3 (size/latency) ? usable as either big or little endian machine direct memory access controller (dmac) ? four channels. two of these channels support external requests. ? burst mode and cycle steal mode ? outputs transfer end signal in channel with dreq (one channel) ? supports intermittent mode (supports 16 or 64 cycles) clock pulse generator (cpg) ? clock mode: input clock can be selected from external input (extal or ckio) or crystal resonator ? three types of clocks generated cpu clock: max. 133.34 mhz/100 mhz bus clock: max. 66.67 mhz peripheral clock: max. 33.34 mhz ? seven types of clock mode (selection of multiplication ratio of pll1 and pll2, and selection external clock or crystal resonator) watchdog timer (wdt) ? one-channel watchdog timer power-down mode ? supports power-down mode sleep mode software standby mode and hardware standby mode module standby mode rev. 1.0, 11/02, page 4 of 690 item features timer unit (tmu) ? three-channel auto-reload-type 32-bit timer ? input capture function (only channel 2) ? five types of counter input clocks can be selected (p /4, p /16, p /64, p /256, tclk input) compare match timer (cmt) ? 16-bit counter ? four types of clocks can be selected (p /4, p /8, p /16, p /64) 16-bit timer pulse unit (tpu) ? four pwm output (to0, to1, to2, and to3) ? supports pwm function realtime clock (rtc) ? clock and calendar functions (bcd format) ? 30-second adjust function ? alarm/periodic/carry interrupt ? automatic leap year adjustment serial communication interface (scif_0, scif_2) ? clock synchronous/asynchronous mode ? 64-byte transmit/receive fifos ? high-speed uart ? uart supports fifo stop and fifo trigger ? supports rts / cts ? supports irda 1.0 (only channel 0) usb function module (usb) ? conforms to usb 1.1 ? supports modes with an on-chip and external usb transceiver ? supports control transfer (endpoint 0), bulk transfer (endpoint 1, 2), and interrupt transfer (endpoint 3) ? the usb standard commands are supported, and class and bender commands are handled by firmware ? on-chip fifo buffer for endpoints (128 bytes/endpoint 1, 2) ? module input clock: 48 mhz i/o port ? bitwise selection of input/output for input/output port a/d converter ? 10 bits 4 lsb, four channels ? input range: 0 to avcc (max. 3.6 v) user break controller (ubc) ? address, data value, access type, and data size are available for setting as break conditions ? supports the sequential break function ? two break channels rev. 1.0, 11/02, page 5 of 690 item features hitachi user debugging interface (h-udi) ? supports the e10a emulator ? jtag-standard pin assignment ? real-time branch trace (aud) power-supply voltage ? i/o: 3.3 0.3 v, internal: 1.5 0.1 v power supply voltage product name i/o on-chip modules operating frequency product code package 133 mhz HD6417705f133 100 mhz HD6417705f100 208-pin plastic lqfp (fp- 208c) 133 mhz HD6417705bp133 sh7705 3.3 0.3 v 1.5 0.1 v 100 mhz HD6417705bp100 208-pin tfbga (tbp-208a) product lineup rev. 1.0, 11/02, page 6 of 690 1.2 block diagram figure 1.1 shows an internal block diagram of the sh7705. sh3 cpu tmu tpu rtc cmt scif0/irda scif2 usb adc h-udi ubc aud bsc dmac ccn cache mmu tlb intc cpg/wdt legend: cache: ccn: mmu: tlb: intc: cpg/wdt: cpu: ubc: aud: bsc: dmac: cache memory cache memory controller memory management unit translation look-aside buffer interrupt controller clock pulse generator/watchdog timer central processing unit user break controller advanced user debugger bus state controller direct memory access controller timer unit 16-bit timer pulse unit realtime clock compare match timer serial communication interface with fifo infrared data association module universal serial bus a/d converter hitachi user debugging interface pin function controller tmu: tpu: rtc: cmt: scif: irda: usb: adc: h-udi: pfc: i/o port (pfc) external bus interface i bus l bus peripheral bus figure 1.1 block diagram of sh7705 rev. 1.0, 11/02, page 7 of 690 1.3 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 v ss q v cc -usb d+ d- v ss -usb v cc -rtc xtal2 extal2 v ss -rtc vbus/ptm6 md6 d31/ptb7/pint15 d30/ptb6/pint14 d29/ptb5/pint13 d28/ptb4/pint12 d27/ptb3/pint11 v ss q d26/ptb2/pint10 v cc q d25/ptb1/pint9 d24/ptb0/pint8 d23/pta7/pint7 d22/pta6/pint6 d21/pta5/pint5 d20/pta4/pint4 v ss d19/pta3/pint3 v cc d18/pta2/pint2 d17/pta1/pint1 d16/pta0/pint0 v ss q d15 v cc q d14 d13 d12 d11 d10 d9 d8 d7 d6 v ss q d5 v cc q d4 d3 d2 d1 d0 v ss q 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 v ss q extal xtal md5 v cc -pll2 v ss -pll2 v ss -pll1 v cc -pll1 md2 md1 md0 /ptf7 /ptf6 tdo/ptf5 /ptg3 tms/ptg2 tck/ptg1 tdi/ptg0 v cc q ptm3 ptm2 ptm1 ptm0 v ss q v cc nf * /ptm4 v ss nf * /ptj7 nf * /ptj6 nf * /ptj5 nf * /ptj4 nf * /ptj3 nf * /ptj2 nf * /ptj1 nf * /ptj0 audata3/ptf3/to3 audata2/ptf2/to2 audata1/ptf1/to1 audata0/ptf0/to0 audsync/ptf4 tend0/pte3 dack1/pte1 dack0/pte0 v cc q /ptg7 v ss q /ptg6 /ptg5 ptd5/nf * cke/ptd4 /ptd3 v ss q index 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 /ptd2 /ptd1 /ptd0 /ptd7 /ptc7 /ptd6 /ptc6 /ptc5 /ptc4 /ptc3 rd/ /dqmuu/ /ptc2 /dqmul/ptc1 /dqmlu v cc q /dqmll v ss q /ptc0 a25/ptk7 a24/ptk6 a23/ptk5 a22/ptk4 v cc a21/ptk3 v ss a20/ptk2 a19/ptk1 a18 a17 a16 a15 v cc q a14 v ss q a13 a12 a11 a10 a9 a8 a7 a6 a5 v cc q a4 v ss q a3 a2 a1 a0/ptk0 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 status0/pte4/ status1/pte5/ v ss q ckio v cc q ptn0/suspnd ptn1/txenl ptn2/xvdata ptn3/txdmns ptn4/txdpls ptn5/dmns ptn6/dpls ptn7 tclk/pte6 pte7 txd0/scpt0/irtx sck0/scpt1 txd2/scpt2 sck2/scpt3 /scpt4 rxd0/scpt0/irrx v cc q rxd2/scpt2 v ss q /scpt5 v ss v cc irq0/ /pth0 irq1/ /pth1 irq2/ /pth2 irq3/ /pth3 irq4/pth4 irq5/pte2 audck/ptg4 nmi dreq0/pth5 dreq1/pth6 ca md3 md4 av ss an0/ptl0 an1/ptl1 an2/ptl2 an3/ptl3 av cc v ss q extal_usb xtal_usb v cc q sh7705 fp-208c (top view) note: * the initial functions of nf (no function) pins are not assigned after power-on reset. specifies the functions with pin functio n controller (pfc). figure 1.2 pin assignment (fp-208c) rev. 1.0, 11/02, page 8 of 690 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 abcdefghj klmnprtu abcdefghj klmnprtu sh7705 tbp-208a (top view) index mark note: the terminal area surrounded by the dotted line is the perspective view. figure 1.3 pin assignment (tbp-208a) rev. 1.0, 11/02, page 9 of 690 table 1.2 pin functions pin no. fp- 208c tbp- 208a pin name i/o description 1 a1 vssq ? i/o power supply (0 v) 2 b1 vcc-usb ? usb power supply (3.3 v) 3 c3 d+ i/o usb data line 4 c2 d- i/o usb data line 5 c1 vss-usb ? usb power supply (0 v) 6 d3 vcc-rtc * 5 ? rtc power supply (3.3 v) * 5 7 d2 xtal2 o crystal oscillator pin for on-chip rtc 8 d1 extal2 i crystal oscillator pin for on-chip rtc 9 e4 vss-rtc * 5 ? rtc power supply (0 v) * 5 10 e3 vbus/ptm6 i / i/o usb power supply detection / input/output port m 11 e2 md6 i connect to i/o power supply (0v) 12 e1 d31/ptb7/pint15 i/o / i/o / i data bus / input/output port b / pint interrupt 13 f4 d30/ptb6/pint14 i/o / i/o / i data bus / input/output port b / pint interrupt 14 f3 d29/ptb5/pint13 i/o / i/o / i data bus / input/output port b / pint interrupt 15 f2 d28/ptb4/pint12 i/o / i/o / i data bus / input/output port b / pint interrupt 16 f1 d27/ptb3/pint11 i/o / i/o / i data bus / input/output port b / pint interrupt 17 g4 vssq ? i/o power supply (0 v) 18 g3 d26/ptb2/pint10 i/o / i/o / i data bus / input/output port b / pint interrupt 19 g2 vccq ? i/o power supply (3.3 v) 20 g1 d25/ptb1/pint9 i/o / i/o / i data bus / input/output port b / pint interrupt 21 h4 d24/ptb0/pint8 i/o / i/o / i data bus / input/output port b / pint interrupt 22 h3 d23/pta7/pint7 i/o / i/o / i data bus / input/output port a / pint interrupt 23 h2 d22/pta6/pint6 i/o / i/o / i data bus / input/output port a / pint interrupt 24 h1 d21/pta5/pint5 i/o / i/o / i data bus / input/output port a / pint interrupt 25 j4 d20/pta4/pint4 i/o / i/o / i data bus / input/output port a / pint interrupt 26 j2 vss ? internal power supply (0 v) 27 j1 d19/pta3/pint3 i/o / i/o / i data bus / input/output port a / pint interrupt 28 j3 vcc ? internal power supply (1.5 v) 29 k1 d18/pta2/pint2 i/o / i/o / i data bus / input/output port a / pint interrupt 30 k2 d17/pta1/pint1 i/o / i/o / i data bus / input/output port a / pint interrupt 31 k3 d16/pta0/pint0 i/o / i/o / i data bus / input/output port a / pint interrupt rev. 1.0, 11/02, page 10 of 690 pin no. fp- 208c tbp- 208a pin name i/o description 32 k4 vssq ? i/o power supply (0 v) 33 l1 d15 i/o data bus 34 l2 vccq ? i/o power supply (3.3 v) 35 l3 d14 i/o data bus 36 l4 d13 i/o data bus 37 m1 d12 i/o data bus 38 m2 d11 i/o data bus 39 m3 d10 i/o data bus 40 m4 d9 i/o data bus 41 n1 d8 i/o data bus 42 n2 d7 i/o data bus 43 n3 d6 i/o data bus 44 n4 vssq ? i/o power supply (0 v) 45 p1 d5 i/o data bus 46 p2 vccq ? i/o power supply (3.3 v) 47 p3 d4 i/o data bus 48 r1 d3 i/o data bus 49 r2 d2 i/o data bus 50 p4 d1 i/o data bus 51 t1 d0 i/o data bus 52 t2 vssq ? i/o power supply (0 v) 53 u1 a0/ptk0 o / i/o address bus / input/output port k 54 u2 a1 o address bus 55 r3 a2 o address bus 56 t3 a3 o address bus 57 u3 vssq ? i/o power supply (0 v) 58 r4 a4 o address bus 59 t4 vccq ? i/o power supply (3.3 v) 60 u4 a5 o address bus 61 p5 a6 o address bus 62 r5 a7 o address bus 63 t5 a8 o address bus rev. 1.0, 11/02, page 11 of 690 pin no. fp- 208c tbp- 208a pin name i/o description 64 u5 a9 o address bus 65 p6 a10 o address bus 66 r6 a11 o address bus 67 t6 a12 o address bus 68 u6 a13 o address bus 69 p7 vssq ? i/o power supply (0 v) 70 r7 a14 o address bus 71 t7 vccq ? i/o power supply (3.3 v) 72 u7 a15 o address bus 73 p8 a16 o address bus 74 r8 a17 o address bus 75 t8 a18 o address bus 76 u8 a19/ptk1 o / i/o address bus / input/output port k 77 p9 a20/ptk2 o / i/o address bus / input/output port k 78 t9 vss ? internal power supply (0 v) 79 u9 a21/ptk3 o / i/o address bus / input/output port k 80 r9 vcc ? internal power supply (1.5 v) 81 u10 a22/ptk4 o / i/o address bus / input/output port k 82 t10 a23/ptk5 o / i/o address bus / input/output port k 83 r10 a24/ptk6 o / i/o address bus / input/output port k 84 p10 a25/ptk7 o / i/o address bus / input/output port k 85 u11 bs /ptc0 o / i/o bus cycle start signal / input/output port c 86 t11 rd o read strobe 87 r11 vssq ? i/o power supply (0 v) 88 p11 we0 /dqmll o / o d7 to d0 select signal / dqm (sdram) 89 u12 vccq ? i/o power supply (3.3 v) 90 t12 we1 /dqmlu o / o d15 to d8 select signal / dqm (sdram) 91 r12 we2 /dqmul/ptc1 o / o / i/o d23 to d16 select signal / dqm (sdram) / input/output port c 92 p12 we3 /dqmuu/ ah / ptc2 o / o / o / i/o d31 to d24 select signal / dqm (sdram) / address hold / input/output port c 93 u13 rd/ wr o read/write 94 t13 cs0 o chip select 0 rev. 1.0, 11/02, page 12 of 690 pin no. fp- 208c tbp- 208a pin name i/o description 95 r13 cs2 /ptc3 o / i/o chip select 2 / input/output port c 96 p13 cs3 /ptc4 o / i/o chip select 3 / input/output port c 97 u14 cs4 /ptc5 o / i/o chip select 4 / input/output port c 98 t14 cs5a * 3 /ptc6 o / i/o chip select 5a / input/output port c 99 r14 cs5b * 3 /ptd6 o / i/o chip select 5b / input/output port d 100 u15 cs6a * 3 /ptc7 o / i/o chip select 6a / input/output port c 101 t15 cs6b * 3 /ptd7 o / i/o chip select 6b / input/output port d 102 p14 rasl /ptd0 o / i/o lower 32 mbytes address ras (sdram) / input/output port d 103 u16 rasu * 3 /ptd1 o / i/o upper 32 mbytes address ras (sdram) / input/output port d 104 t16 casl /ptd2 o / i/o lower 32 mbytes address cas (sdram) / input/output port d 105 u17 vssq ? i/o power supply (0 v) 106 t17 casu * 3 /ptd3 o / i/o upper 32 mbytes address cas (sdram) / input/output port d 107 r15 cke/ptd4 o / i/o ck enable (sdram) / input/output port d 108 r16 ptd5/nf * 4 i input port d / nf * 4 109 r17 back /ptg5 o / i/o bus acknowledge / input/output port g 110 p15 breq /ptg6 i / i/o bus request / input/output port g 111 p16 vssq ? i/o power supply (0 v) 112 p17 wait /ptg7 i / i/o hardware wait request / input/output port g 113 n14 vccq ? i/o power supply (3.3 v) 114 n15 dack0/pte0 o / i/o dma acknowledge 0 / input/output port e 115 n16 dack1/pte1 o / i/o dma acknowledge 1 / input/output port e 116 n17 tend0/pte3 o / i/o dma transfer end notification / input/output port e 117 m14 audsync/ptf4 o / i/o aud synchronous / input/output port f 118 m15 audata0/ptf0/to0 o / i/o / o aud data output / input/output port f / timer output 119 m16 audata1/ptf1/to1 o / i/o / o aud data output / input/output port f / timer output 120 m17 audata2/ptf2/to2 o / i/o / o aud data output / input/output port f / timer output rev. 1.0, 11/02, page 13 of 690 pin no. fp- 208c tbp- 208a pin name i/o description 121 l14 audata3/ptf3/to3 o / i/o / o aud data output / input/output port f / timer output 122 l15 nf * 4 /ptj0 o nf * 4 /output port j 123 l16 nf * 4 /ptj1 o nf * 4 /output port j 124 l17 nf * 4 /ptj2 o nf * 4 /output port j 125 k14 nf * 4 /ptj3 o nf * 4 /output port j 126 k15 nf * 4 /ptj4 o nf * 4 /output port j 127 k16 nf * 4 /ptj5 o nf * 4 /output port j 128 k17 nf * 4 /ptj6 o nf * 4 /output port j 129 j14 nf * 4 /ptj7 o nf * 4 /output port j 130 j16 vss ? internal power supply (0 v) 131 j17 nf * 4 /ptm4 i nf * 4 / input port m 132 j15 vcc ? internal power supply (1.5 v) 133 h17 vssq ? i/o power supply (0 v) 134 h16 ptm0 i/o input/output port m 135 h15 ptm1 i/o input/output port m 136 h14 ptm2 i/o input/output port m 137 g17 ptm3 i/o input/output port m 138 g16 vccq ? i/o power supply (3.3 v) 139 g15 tdi/ptg0 i / i/o test data input (h-udi) / input/output port g 140 g14 tck/ptg1 i / i/o test clock (h-udi) / input/output port g 141 f17 tms/ptg2 i / i/o test mode select (h-udi) / input/output port g 142 f16 trst * 1 /ptg3 i / i/o test reset (h-udi) / input/output port g 143 f15 tdo/ptf5 o / i/o test data output (h-udi) / input/output port f 144 f14 asebrkak /ptf6 o / i/o ase break acknowledge (h-udi) / input/output port f 145 e17 asemd0 * 2 /ptf7 i / i/o ase mode (h-udi) / input/output port f 146 e16 md0 i clock mode setting 147 e15 md1 i clock mode setting 148 e14 md2 i clock mode setting 149 d17 vcc-pll1 ? pll1 power supply (1.5 v) 150 d16 vss-pll1 ? pll1 power supply (0 v) rev. 1.0, 11/02, page 14 of 690 pin no. fp- 208c tbp- 208a pin name i/o description 151 d15 vss-pll2 ? pll2 power supply (0 v) 152 c17 vcc-pll2 ? pll2 power supply (1.5 v) 153 c16 md5 i endian setting 154 d14 xtal o crystal oscillator pin 155 b17 extal i external clock / crystal oscillator pin 156 b16 vssq ? i/o power supply (0 v) 157 a17 status0/pte4/ rts0 o / i/o / o processor status / input/output port e / scif0 transmit request 158 a16 status1/pte5/ cts0 o / i/o / i processor status / input/output port e / scif0 transmit clear 159 c15 vssq ? i/o power supply (0 v) 160 b15 ckio i/o system clock input/output 161 a15 vccq ? i/o power supply (3.3 v) 162 c14 ptn0/suspnd i/o / o input/output port n / usb suspend 163 b14 ptn1/txenl i/o / o input/output port n / usb output enable 164 a14 ptn2/xvdata i/o / i input/output port n / usb differential receive input 165 d13 ptn3/txdmns i/o / o input/output port n / usb d? transmit output 166 c13 ptn4/txdpls i/o / o input/output port n / usb d+ transmit output 167 b13 ptn5/dmns i/o / i input/output port n / d? input from usb receiver 168 a13 ptn6/dpls i/o / i input/output port n / d+ input from usb receiver 169 d12 ptn7 i/o input/output port n 170 c12 tclk/pte6 i / i/o tmu clock input / input/output port e 171 b12 pte7 i/o input/output port e 172 a12 txd0/scpt0/irtx o / o / o scif0 transmit data / sc port / irda tx port 173 d11 sck0/scpt1 i/o / i/o scif0 clock / sc port 174 c11 txd2/scpt2 o / o scif2 transmit data / sc port 175 b11 sck2/scpt3 i/o / i/o scif2 clock / sc port 176 a11 rts2 /scpt4 o / i/o scif2 transmit request / sc port 177 d10 rxd0/scpt0/irrx i / i / i scif0 receive data / sc port / irda rx port 178 c10 vccq ? i/o power supply (3.3 v) 179 b10 rxd2/scpt2 i / i scif2 receive data / sc port rev. 1.0, 11/02, page 15 of 690 pin no. fp- 208c tbp- 208a pin name i/o description 180 a10 vssq ? i/o power supply (0 v) 181 d9 cts2 /scpt5 i / i/o scif2 transmit clear / sc port 182 b9 vss ? i/o power supply (0 v) 183 a9 resetm i manual reset request 184 c9 vcc ? internal power supply (1.5 v) 185 a8 irq0/ irl0 /pth0 i / i / i/o external interrupt request / input/output port h 186 b8 irq1/ irl1 /pth1 i / i / i/o external interrupt request / input/output port h 187 c8 irq2/ irl2 /pth2 i / i / i/o external interrupt request / input/output port h 188 d8 irq3/ irl3 /pth3 i / i / i/o external interrupt request / input/output port h 189 a7 irq4/pth4 i / i/o external interrupt request / input/output port h 190 b7 irq5/pte2 i / i/o external interrupt request / input/output port e 191 c7 audck/ptg4 o / i/o aud clock / input/output port g 192 d7 nmi i nonmaskable interrupt request 193 a6 dreq0/pth5 i / i/o dma request / input/output port h 194 b6 dreq1/pth6 i / i/o dma request / input/output port h 195 c6 resetp i power-on reset request 196 d6 ca i hardware standby request 197 a5 md3 i area 0 bus width setting 198 b5 md4 i area 0 bus width setting 199 c5 avss ? analog power supply (0 v) 200 d5 an0/ptl0 i / i a/d converter input / input port l 201 a4 an1/ptl1 i / i a/d converter input / input port l 202 b4 an2/ptl2 i / i a/d converter input / input port l 203 c4 an3/ptl3 i / i a/d converter input / input port l 204 a3 avcc ? analog power supply (3.3 v) 205 b3 vssq ? i/o power supply (0 v) 206 d4 extal_usb i usb clock 207 a2 xtal_usb o usb clock 208 b2 vccq ? i/o power supply (3.3 v) notes: * 1 the trst pin must be driven low for a specified period when power supply is turned on regardless of whether the h-udi function is used or not. as the same as the resetp pin, the trst pin should be driven low at the power-on set state and driven high after the power-on reset state is released. * 2 the input level of the asemd0 pin must be high if the e10a emulator is not used. for details, refer to section 23.4.2, reset configuration. rev. 1.0, 11/02, page 16 of 690 * 3 these pins are initialized to the general input port setting in which the pull-up mos is off at a power-on reset. when these pins are connected to memory and so on, their levels must be fixed externally. * 4 the initial functions of nf (no function) pins are not assigned after power-on reset. specifies the functions with pin function controller (pfc). * 5 in hardware standby mode, supply power to all power supply pins including the rtc power supply pins. * 6 the unused pins should be handled according to table a.1, i/o port states in each processing state, in appendix. rev. 1.0, 11/02, page 17 of 690 1.4 pin functions table 1.3 lists the pin functions. table 1.3 pin functions classification symbol i/o name function vcc ? power supply power supply for the internal modules and ports for the system. connect all vcc pins to the system power supply. there will be no operation if any pins are open. vss ? ground ground pin. connect all vss pins to the system power supply (0 v). there will be no operation if any pins are open. vccq ? power supply power supply for i/o pins. connect all vccq pins to the system power supply. there will be no operation if any pins are open. power supply vssq ? ground ground pin. connect all vssq pins to the system power supply (0 v). there will be no operation if any pins are open. vcc-pll1 ? pll1 power supply power supply for the on-chip pll1 oscillator. vss-pll1 ? pll1 ground ground pin for the on-chip pll1 oscillator. vcc-pll2 ? pll2 power supply power supply for the on-chip pll2 oscillator. vss-pll2 ? pll2 ground ground pin for the on-chip pll2 oscillator. extal i external clock for connection to a crystal resonator. an external clock signal may also be input to the extal pin. xtal o crystal for connection to a crystal resonator. clock ckio i/o system clock supplies the system clock to external devices. rev. 1.0, 11/02, page 18 of 690 classification symbol i/o name function operating mode control md6 to md0 i mode set sets the operating mode. do not change values on these pins during operation. md2 to md0 set the clock mode, md3 and md4 set the bus-width mode of area 0 and md5 sets the endian. md6 pin should be connected to vssq. resetp i power-on reset when low, the system enters the power-on reset state. resetm i manual reset when low, the system enters the manual reset state. status1, status0 o status output indicates the operating state. breq i bus request low when an external device requests the release of the bus mastership. back o bus request acknowledge indicates that the bus mastership has been released to an external device. reception of the back signal informs the device which has output the breq signal that it has acquired the bus. system control ca i chip active high in normal operation, and low in hardware standby mode. nmi i non-maskable interrupt non-maskable interrupt request pin. fix to high level when not in use. irq5 to irq0 i interrupt requests 5 to 0 maskable interrupt request pin. selectable as level input or edge input. the rising edge or falling edge is selectable as the detection edge. the low level or high level is selectable as the detection level. irl3 to irl0 i interrupt requests 3 to 0 maskable interrupt request pin. input a coded interrupt level. interrupts pint15 to pint0 i interrupt requests 15 to 0 pint interrupt request pin. address bus a25 to a0 o address bus outputs addresses. data bus d31 to d0 i/o data bus 32-bit bidirectional data bus. rev. 1.0, 11/02, page 19 of 690 classification symbol i/o name function cs0 , cs2 to cs4 , cs5a , cs5b , cs6a , cs6b , o chip select 0, 2 to 4, 5a, 5b, 6a, 6b chip-select signal for external memory or devices. rd o read indicates reading of data from external devices. rd/ wr o read/write read/write signal. bs o bus start bus-cycle start. we3 o highest-byte write indicates that bits 31 to 24 of the data in the external memory or device are being written. we2 o second-highest- byte write indicates that bits 23 to 16 of the data in the external memory or device are being written. we1 o second-lowest- byte write indicates that bits 15 to 8 of the data in the external memory or device are being written. we0 o lowest-byte write indicates that bits 7 to 0 of the data in the external memory or device are being written. cke o ck enable clock enable. (sdram) dqmuu o dq mask uu selects d31 to d24. (sdram) dqmul o dq mask ul selects d23 to d16. (sdram) dqmlu o dq mask lu selects d15 to d8. (sdram) dqmll o dq mask ll selects d7 to d0. (sdram) rasu o row address u specifies a row address. (sdram) rasl o row address l specifies a row address. (sdram) casu o column address u specifies a column address. (sdram) casl o column address l specifies a column address. (sdram) ah o address hold address hold signal. bus control wait i wait inserts a wait cycle into the bus cycles during access to the external space. rev. 1.0, 11/02, page 20 of 690 classification symbol i/o name function dreq0, dreq1 i dma-transfer request input pin for external requests for dma transfer. dack0, dack1 o dma-transfer strobe output strobe to external i/o, in response to external requests for dma transfer. direct memory access controller (dmac) tend0 o dma-transfer end transfer end output for dmac channel 0. timer unit (tmu) tclk i clock input external clock input pin/input capture control input pin. 16-bit timer pulse unit (tpu) to3 to to0 o timer output output compare/pwm output pin. txd0, txd2 o transmit data transmit data pin. rxd0, rxd2 i receive data receive data pin. sck0, sck2 i/o serial clock clock input/output pin. rts0 , rts2 o transmit request modem control pin. serial communication interface with fifo (scif0, scif2) cts0 , cts2 i transmit enable modem control pin. irtx o irda tx port irda transmit data output. irda irrx i irda rx port irda receive data input. extal2 i rtc clock rtc crystal oscillator pin. (32.768 khz) xtal2 o rtc clock rtc crystal oscillator pin. (32.768 khz) vcc-rtc ? rtc power supply power supply pin for the rtc. realtime clock (rtc) vss-rtc ? rtc ground ground pin for the rtc. an3 to an0 i analog input pin analog input pin. avcc ? a/d analog power supply power supply for the a/d converter. when the a/d converter is not in use, connect this pin to the port power supply (vccq). a/d converter (adc) avss ? a/d analog ground ground pin for the a/d converter. connect this pin to the system power supply (vss). rev. 1.0, 11/02, page 21 of 690 classification symbol i/o name function extal_usb i usb clock usb clock input pin. (48-mhz input) xtal_usb o usb clock usb clock pin. xvdata i data input receive data input pin from the differential receiver. vbus i usb power supply detection usb-cable connection-monitor pin. txdpls o d + output d + transmit output pin for the driver. txdmns o d ? output d ? transmit output pin for the driver. dpls i d + input d + signal input pin from the receiver to the driver. dmns i d ? input d ? signal input pin from the receiver to the driver. txenl o output enable output enable pin for the driver. suspnd o suspend suspend-state output pin for the transceiver. vcc-usb ? usb analog power supply usb power supply pin. when the usb is not in use, connect this pin to the port power supply (vccq). vss-usb ? usb analog ground usb ground pin. connect this pin to the system power supply (vss). d ? i/o d ? i/o on-chip usb transceiver d ? . usb d + i/o d + i/o on-chip usb transceiver d + . rev. 1.0, 11/02, page 22 of 690 classification symbol i/o name function pta7 to pta0 i/o general purpose port 8-bit general-purpose i/o port pins. ptb7 to ptb0 i/o general purpose port 8-bit general-purpose i/o port pins. ptc7 to ptc0 i/o general purpose port 8-bit general-purpose i/o port pins. ptd7 to ptd0 i/o general purpose port 8-bit general-purpose i/o port pins. pte7 to pte0 i/o general purpose port 8-bit general-purpose i/o port pins. ptf7 to ptf0 i/o general purpose port 8-bit general-purpose i/o port pins. ptg7 to ptg0 i/o general purpose port 8-bit general-purpose i/o port pins. pth6 to pth0 i/o general purpose port 7-bit general-purpose i/o port pins. ptj7 to ptj0 o general purpose port 8-bit general-purpose output port pins. ptk7 to ptk0 i/o general purpose port 8-bit general-purpose i/o port pins. ptl3 to ptl0 i general purpose port 4-bit general-purpose input port pins. ptm6, ptm4 to ptm0 i/o general purpose port 6-bit general-purpose i/o port pins. ptn7 to ptn0 i/o general purpose port 8-bit general-purpose i/o port pins. i/o port scpt5 to scpt0 i/o serial port 6-bit serial port pins. rev. 1.0, 11/02, page 23 of 690 classification symbol i/o name function tck i test clock test-clock input pin. tms i test mode select inputs the test-mode select signal. tdi i test data input serial input pin for instructions and data. tdo o test data output serial output pin for instructions and data. hitachi user debugging interface (h-udi) trst i test reset initial-signal input pin. audata3 to audata0 o aud data destination-address output pin in branch-trace mode. audck o aud clock synchronous clock output pin in branch-trace mode. advanced user debugger (aud) audsync o aud synchronous signal data start-position acknowledge- signal output pin in branch-trace mode. asebrkak o break mode acknowledge indicates that the e10a emulator has entered its break mode. for the connection with the e10a, see the sh7705 e10a emulator user?s manual (tentative title). e10a interface asemd0 i ase mode sets ase mode. rev. 1.0, 11/02, page 24 of 690 rev. 1.0, 11/02, page 25 of 690 section 2 cpu 2.1 processing states and processing modes 2.1.1 processing states this lsi supports four types of processing states: a reset state, an exception handling state, a program execution state, and a low-power consumption state, according to the cpu processing states. reset state: in the reset state, the cpu is reset. the lsi supports two types of resets: power-on reset and manual reset. for details on resets, refer to section 5, exception handling. in power-on reset, the registers and internal statuses of all lsi on-chip modules are initialized. in manual reset, the register contents of a part of the lsi on-chip modules, such as the bus state controller (bsc), are retained. for details, refer to section 24, list of registers. the cpu internal statuses and registers are initialized both in power-on reset and manual reset. after initialization, the program branches to address h?a0000000 to pass control to the reset processing program to be executed. exception handling state: in the exception handling state, the cpu processing flow is changed temporarily by a general exception or interrupt exception processing. the program counter (pc) and status register (sr) are saved in the save program counter (spc) and save status register (ssr), respectively. the program branches to an address obtained by adding a vector offset to the vector base register (vbr) and passes control to the exception processing program defined by the user to be executed. for details on reset, refer to section 5, exception handling. program execution state: the cpu executes programs sequentially. low-power consumption state: the cpu stops operation to reduce power consumption. the low-power consumption state can be entered by executing the sleep instruction. for details on the low-power consumption state, refer to section 11, power-down modes. figure 2.1 shows a status transition diagram. cpus3d0s_000020020300 rev. 1.0, 11/02, page 26 of 690 2.1.2 processing modes this lsi supports two processing modes: user mode and privileged mode. these processing modes can be determined by the processing mode bit (md) of the status register (sr). if the md bit is cleared to 0, the user mode is selected. if the md bit is set to 1, the privileged mode is selected. the cpu enters the privileged mode by a transition to reset state or exception handling state. in the privileged mode, any registers and resources in address spaces can be accessed. clearing the md bit of the sr to 0 puts the cpu in the user mode. in the user mode, some of the registers, including sr, and some of the address spaces cannot be accessed by the user program and system control instructions cannot be executed. this function effectively protects the system resources from the user program. to change the processing mode from user to privileged mode, a transition to exception handling state is required.* note: * to call a service routine used in privileged mode from user mode, the lsi supports an unconditional trap instruction (trapa). when a transition from user mode to privileged mode occurs, the contents of the sr and pc are saved. a program execution in user mode can be resumed by restoring the contents of the sr and pc. to return from an exception processing program, the lsi supports an rte instruction. (from any states) power-on reset manual reset reset state program execution state low-power consumption state exception handling state an exception is accepted exception handling routine starts reset processing routine starts an exception is accepted multiple exceptions sleep instruction figure 2.1 processing state transitions rev. 1.0, 11/02, page 27 of 690 2.2 memory map 2.2.1 logical address space the lsi supports 32-bit logical addresses and accesses system resources using the 4-gbytes of logical address space. user programs and data are accessed from the logical address space. the logical address space is divided into several areas as shown in table 2.1. p0/u0 area: this area is called the p0 area when the cpu is in privileged mode and the u0 area when in user mode. for the p0 and u0 areas, access using the cache is enabled. the p0 and u0 areas are handled as address translatable areas. if the cache is enabled, access to the p0 or u0 area is cached. if a p0 or u0 address is specified while the address translation unit is enabled, the p0 or u0 address is translated into a physical address based on translation information defined by the user. if the cpu is in user mode, only the u0 area can be accessed. if p1, p2, p3, or p4 is accessed in user mode, a transition to an address error exception occurs. p1 area: the p1 area is defined as a cacheable but non-address translatable area. normally, programs executed at high speed in privileged mode, such as exception processing handlers, which are at the core of the operating system (s), are assigned to the p1 area. p2 area: the p2 area is defined as a non-cacheable but non-address translatable area. a reset processing program to be called from the reset state is described at the start address (h?a0000000) of the p2 area. normally, programs such as system initialization routines and os initiation programs are assigned to the p2 area. to access a part of an on-chip module control register, its corresponding program should be assigned to the p2 area. p3 area: the p3 area is defined as a cacheable and address translatable area. this area is used if an address translation is required for a privileged program. p4 area: the p4 area is defined as a control area which is non-cacheable and non-address translatable. this area can be accessed only in privileged mode. a part of this lsi s on-chip module control register is assigned to this area. rev. 1.0, 11/02, page 28 of 690 table 2.1 logical address space address range name mode description h?00000000 to h?7fffffff p0/u0 privileged/user mode 2-gbyte physical space, cacheable, address translatable in user mode, only this address space can be accessed. h?80000000 to h?9fffffff p1 privileged mode 0.5-gbyte physical space, cacheable h?a0000000 to h?bfffffff p2 privileged mode 0.5-gbyte physical space, non-cacheable h?c0000000 to h?dfffffff p3 privileged mode 0.5-gbyte physical space, cacheable, address translatable h?e0000000 to h?ffffffff p4 privileged mode 0.5-gbyte control space, non-cacheable 2.2.2 external memory space the lsi uses 29 bits of the 32-bit logical address to access external memory. in this case, 0.5- gbyte of external memory space can be accessed. the external memory space is managed in area units. different types of memory can be connected to each area, as shown in figure 2.2. for details, please refer to section 7, bus state controller (bsc). in addition, area 1 in the external memory space is used as an on-chip i/o space where most of this lsi s on-chip module control registers are mapped. * 1 normally, the upper three bits of the 32-bit logical address are masked and the lower 29 bits are used for external memory addresses.* 2 for example, address h?00000100 in the p0 area, address h?80000100 in the p1 area, address h?a0000100 in the p2 area, and address h?c0000100 in the p3 area of the logical address space are mapped into address h?00000100 of area 0 in the external memory space. the p4 area in the logical address space is not mapped into the external memory address. if an address in the p4 area is accessed, an external memory cannot be accessed. notes: *1 to access an on-chip module control register mapped into area 1 in the external memory space, access the address from the p2 area which is not cached in the logical address space. *2 if the address translation unit is enabled, arbitrary mapping in page units can be specified. for details, refer to section 3, memory management unit (mmu). rev. 1.0, 11/02, page 29 of 690 p0 area privileged mode user mode external memory space area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 h'0000 0000 h'0000 0000 h'8000 0000 h'ffff ffff h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff u0 area address error p1 area p2 area p3 area p4 area figure 2.2 logical address to external memory space mapping 2.3 register descriptions this lsi provides thirty-three 32-bit registers: 24 general registers, five control registers, three system registers, and one program counter. general registers: this lsi incorporates 24 general registers: r0_bank0 to r7_bank0, r0_bank1 to r7_bank1 and r8 to r15. r0 to r7 are banked. the process mode and the register bank (rb) bit in the status register (sr) define which set of banked registers (r0_bank0 to r7_bank0 or r0_bank1 to r7_bank1) are accessed as general registers. system registers: this lsi incorporates the multiply and accumulate registers (mach/macl) and procedure register (pr) as system registers. these registers can be accessed regardless of the processing mode. program counter: the program counter stores the value obtained by adding 4 to the current instruction address. control registers: this lsi incorporates the status register (sr), global base register (gbr), save status register (ssr), save program counter (spc), and vector base register as control register. only the gbr can be accessed in user mode. control registers other than the gbr can be accessed only in privileged mode. rev. 1.0, 11/02, page 30 of 690 table 2.2 shows the register values after reset. figure 2.3 shows the register configurations in each process mode. table 2.2 register initial values register type registers initial values general registers r0_bank0 to r7_bank0, r0_bank1 to r7_bank1, r8 to r15 undefined system registers mach, macl, pr undefined program counter pc h?a0000000 sr md bit = 1, rb bit = 1, bl bit = 1, i3 to i0 bits = h?f (1111), reserved bits = all 0, other bits = undefined gbr, ssr, spc undefined control registers vbr h?00000000 note: * initialized by a power-on or manual reset. rev. 1.0, 11/02, page 31 of 690 31 r0_bank0 * 1, * 2 r1_bank0 * 2 r2_bank0 * 2 r3_bank0 * 2 r4_bank0 * 2 r5_bank0 * 2 r6_bank0 * 2 r7_bank0 * 2 r8 r9 r10 r11 r12 r13 r14 r15 sr gbr mach macl pr pc 0 31 r0_bank1 * 1, * 3 r1_bank1 * 3 r2_bank1 * 3 r3_bank1 * 3 r4_bank1 * 3 r5_bank1 * 3 r6_bank1 * 3 r7_bank1 * 3 r0_bank0 * 1, * 4 r1_bank0 * 4 r2_bank0 * 4 r3_bank0 * 4 r4_bank0 * 4 r5_bank0 * 4 r6_bank0 * 4 r7_bank0 * 4 r8 r9 r10 r11 r12 r13 r14 r15 sr ssr gbr mach macl vbr pr pc spc 0 31 r0_bank0 * 1, * 4 r1_bank0 * 4 r2_bank0 * 4 r3_bank0 * 4 r4_bank0 * 4 r5_bank0 * 4 r6_bank0 * 4 r7_bank0 * 4 r0_bank1 * 1, * 3 r1_bank1 * 3 r2_bank1 * 3 r3_bank1 * 3 r4_bank1 * 3 r5_bank1 * 3 r6_bank1 * 3 r7_bank1 * 3 r8 r9 r10 r11 r12 r13 r14 r15 sr ssr gbr mach macl vbr pr pc spc 0 (a) user mode register configuration (b) privileged mode register configuration (rb = 1) (c) privileged mode register configuration (rb = 0) notes: * 1 the r0 register is used as an index register in indexed register indirect addressing mode and indexed gbr indirect addressing mode. * 2 bank register * 3 bank register accessed as a general register when the rb bit is set to 1 in the sr register. accessed only by ldc/stc instructions when the rb bit is cleared to 0. * 4 bank register accessed as a general register when the rb bit is cleared to 0 in the sr register. accessed only by ldc/stc instructions when the rb bit is set to 1. figure 2.3 register configuration in each processing mode rev. 1.0, 11/02, page 32 of 690 2.3.1 general registers there are twenty-four 32-bit general registers: r0_bank0 to r7_bank0, r0_bank1 to r7_bank1, and r8 to r15. r0 to r7 are banked. the process mode and the register bank (rb) bit in the status register (sr) define which set of banked registers (r0_bank0 to r7_bank0 or r0_bank1 to r7_bank1) are accessed as general registers. r0 to r7 registers in the selected bank are accessed as r0 to r7. r0 to r7 in the non-selected bank is accessed as r0_bank to r7_bank by the control register load instruction (ldc) and control register store instruction (stc). in user mode, bank 0 is selected regardless of he rb bit value. sixteen registers: r0_bank0 to r7_bank0 and r8 to r15 are accessed as general registers r0 to r15. the r0_bank1 to r7_bank1 registers in bank 1 cannot be accessed. in privileged mode that is entered by a transition to exception handling state, the rb bit is set to 1 to select bank 1. in privileged mode, sixteen registers: r0_bank1 to r7_bank1 and r8 to r15 are accessed as general registers r0 to r15. a bank is switched automatically when an exception handling state is entered, registers r0 to r7 need not be saved by the exception handling routine. the r0_bank0 to r7_bank0 registers in bank 0 can be accessed as r0_bank to r7_bank by the ldc and stc instructions. in privileged mode, bank 0 can also be used as general registers by clearing the rb bit to 0. in this case, sixteen registers: r0_bank0 to r7_bank0 and r8 to r15 are accessed as general registers r0 to r15. the r0_bank1 to r7_bank1 registers in bank 1 can be accessed as r0_bank to r7_bank by the ldc and stc instructions. the general registers r0 to r15 are used as equivalent registers for almost all instructions. in some instructions, the r0 register is automatically used or only the r0 register can be used as source or destination registers. rev. 1.0, 11/02, page 33 of 690 31 r0 * 1, * 2 r1 * 2 r2 * 2 r3 * 2 r4 * 2 r5 * 2 r6 * 2 r7 * 2 r8 r9 r10 r11 r12 r13 r14 r15 0 general registers: undefined after reset notes: * 1 r0 functions as an index register in the indexed register-indirect addressing mode and indexed gbr-indirect addressing mode. in some instructions, only r0 can be used as the source or destination register. * 2 r0?r7 are banked registers. in user mode, bank0 is used. in privileged mode, either r0_bank0 to r7_bank0 or r0_bank1 to r7_bank1 is selected by the rb bit of the sr register. figure 2.4 general registers 2.3.2 system registers the system registers: multiply and accumulate registers (mach/macl) and procedure register (pr) as system registers can be accessed by the lds and sts instructions. multiply and accumulate registers) (mach/macl: the multiply and accumulate registers (mach/macl) store the results of multiplication and accumulation instructions or multiplication instructions. the mach/macl registers also store addition values for the multiplication and accumulations. after reset, these registers are undefined. the mach and macl registers store upper 32 bits and lower 32 bits, respectively. procedure register (pr): the procedure register (pr) stores the return address for a subroutine call using the bsr, bsrf, or jsr instruction. the return address stored in the pr register is restored to the program counter (pc) by the rts (return from the subroutine) instruction. after reset, this register is undefined. rev. 1.0, 11/02, page 34 of 690 2.3.3 program counter the program counter (pc) stores the value obtained by adding 4 to the current instruction address. there is no instruction to read the pc directly. before an exception handling state is entered, the pc is saved in the save program counter (spc). before a subroutine call is executed, the pc is saved in the procedure register (pr). in addition, the pc can be used for pc relative addressing mode. figure 2.5 shows the system register and program counter configurations. mach macl 31 0 pr 31 0 pc 31 0 multiply and accumulate high and low registers (mach/macl) procedure register (pr) program counter (pc) figure 2.5 system registers and program counter rev. 1.0, 11/02, page 35 of 690 2.3.4 control registers the control registers (sr, gbr, ssr, spc, and vbr) can be accessed by the ldc or stc instruction in privileged mode. the gbr register can be accessed in the user mode. the control registers are described below. status register (sr): the status register (sr) indicates the system status as shown below. the sr register can be accessed only in privileged mode. bit bit name initial value r/w description 31 ? 0rreserved this bit is always read as 0. the write value should always be 0. 30 md 1 r/w processing mode indicates the cpu processing mode. 0: user mode 1: privileged mode the md bit is set to 1 in reset or exception handling state. 29 rb 1 r/w register bank the general registers r0 to r7 are banked registers. the rb bit selects a bank used in the privileged mode. 0: selects bank 0 registers. in this case, r0_bank0 to r7_bank0 and r8 to r15 are used as general registers. r0_bank1 to r7_bank1 can be accessed by the ldc or str instruction. 1: selects bank 1 registers. in this case, r0_bank1 to r7_bank1 and r8 to r15 are used as general registers. r0_bank0 to r7_bank0 can be accessed by the ldc or str instruction. the rb bit is set to 1 in reset or exception handling state. 28 bl 1 r/w block specifies whether an exception, interrupt, or user break is enabled or not. 0: enables an exception, interrupt, or user break. 1: disables an exception, interrupt, or user break. the bl bit is set to 1 in reset or exception handling state. 27 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 36 of 690 bit bit name initial value r/w description 9 8 m q ? ? r/w r/w m bit q bit these bits are used by the div0s, div0u, and div1 instructions. these bits can be changed even in user mode by using the div0s, div0u, and div1 instructions. these bits are undefined at reset. these bits do not change in an exception handling state. 7 to 4 i3 to i0 all 1 r/w interrupt mask indicates the interrupt mask level. these bits do not change even if an interrupt occurs. at reset, these bits are initialized to b?1111. these bits are not affected in an exception handling state. 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1s ? r/w saturation mode specifies the saturation mode for multiply instructions or multiply and accumulate instructions. this bit can be specified by the sets and clrs instructions in user mode. at reset, this bit is undefined. this bit is not affected in an exception handling state. 0t ? r/w t bit indicates true or false for compare instructions or carry or borrow occurrence for an operation instruction with carry or borrow. this bit can be specified by the sett and clrt instructions in user mode. at reset, this bit is undefined. this bit is not affected in an exception handling state. note: the m, q, s, and t bits can be set/cleared by the user mode specific instructions. other bits can be read or written in privileged mode. save status register (ssr): the save status register (ssr) can be accessed only in privileged mode. before entering the exception, the contents of the sr register is stored in the ssr register. at reset, the ssr initial value is undefined. save program counter (spc): the save program counter (spc) can be accessed only in privileged mode. before entering the exception, the contents of the pc are stored in the spc. at reset, the spc initial value is undefined. global base register (gbr): the global base register (gbr) is referenced as a base register in gbr indirect addressing mode. at reset, the gbr initial value is undefined. rev. 1.0, 11/02, page 37 of 690 vector base register (vbr): the global base register (gbr) can be accessed only in privileged mode. if a transition from reset state to exception handling state occurs, this register is referenced as a base address. for details, refer to section 5, exception handling. at reset, the vbr is initialized as h?00000000. figure 2.6 shows the control register configuration. 31 0 31 spc ssr 0 save status register (ssr) save program counter (spc) 31 0 31 vbr gbr 0 global base register (gbr) vector base register (vbr) 31 0 0 md rb bl 0 status register (sr) t s 0 0 i0 i1 i2 i3 q m 0 figure 2.6 control register configuration 2.4 data formats 2.4.1 register data format register operands are always longwords (32 bits). when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 longword rev. 1.0, 11/02, page 38 of 690 2.4.2 memory data formats memory data formats are classified into byte, word, and longword. memory can be accessed in byte, word, and longword. when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. an address error will occur if word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed. in such cases, the data accessed cannot be guaranteed. when a word or longword operand is accessed, the byte positions on the memory corresponding to the word or longword data on the register is determined to the specified endian mode (big endian or little endian). figure 2.7 shows a byte correspondence in big endian mode. in big endian mode, the msb byte in the register corresponds to the lowest address in the memory, and the lsb the in the register corresponds to the highest address. for example, if the contents of the general register r0 is stored at an address indicated by the general register r1 in longword, the msb byte of the r0 is stored at the address indicated by the r1 and the lsb byte of the r1 register is stored at the address indicated by the (r1 +3). the on-chip device registers assigned to memory are accessed in big endian mode. note that the available access size (byte, word, or long word) differs in each register. note: the cpu instruction codes of this lsi must be stored in word units. in big endian mode, the instruction code must be stored from upper byte to lower byte in this order from the word boundary of the memory. 31 @(r1+0) @(r1+1) @(r1+2) @(r1+3) @(r1+0) @(r1+1) @(r1+2) @(r1+3) @(r1+0) @(r1+1) @(r1+2) @(r1+3) [7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [15:8] [7:0] [7:0] (a) byte access example: mov.b r0, @r1 (r1 = address 4n) (b) word access example: mov.w r0, @r1 (r1 = address 4n) (c) longword access example: mov.l r0, @r1 (r1 = address 4n) byte position in r0 byte position in memory 23 15 7 0 figure 2.7 data format on memory (big endian mode) rev. 1.0, 11/02, page 39 of 690 the little endian mode can also be specified as data format. either big-endian or little-endian mode can be selected according to the md5 pin at reset. when md5 is low at reset, the processor operates in big-endian mode. when md5 is high at reset, the processor operates in little-endian mode. the endian mode cannot be modified dynamically. in little endian mode, the msb byte in the register corresponds to the highest address in the memory, and the lsb the in the register corresponds to the lowest address (figure 2.8). for example, if the contents of the general register r0 is stored at an address indicated by the general register r1 in longword, the msb byte of the r0 is stored at the address indicated by the (r1+3) and the lsb byte of the r1 register is stored at the address indicated by the r1. if the little endian mode is selected, the on-chip device registers assigned to memory are accessed in big endian mode. note that the available access size (byte, word, or long word) differs in each register. note: the cpu instruction codes of this lsi must be stored in word units. in little endian mode, the instruction code must be stored from lower byte to upper byte in this order from the word boundary of the memory. 31 @(r1+3) @(r1+2) @(r1+1) @(r1+0) @(r1+3) @(r1+2) @(r1+1) @(r1+0) @(r1+3) @(r1+2) @(r1+1) @(r1+0) [7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [15:8] [7:0] [7:0] (a) byte access example: mov.b r0, @r1 (r1 = address 4n) (b) word access example: mov.w r0, @r1 (r1 = address 4n) (c) longword access example: mov.l r0, @r1 (r1 = address 4n) byte position in r0 byte position in memory 23 15 7 0 figure 2.8 data format on memory (little endian mode) rev. 1.0, 11/02, page 40 of 690 2.5 features of cpu core instructions 2.5.1 instruction execution method instruction length: all instructions have a fixed length of 16 bits and are executed in the sequential pipeline. in the sequential pipeline, almost all instructions can be executed in one cycle. all data items are handles in longword (32 bits). memory can be accessed in byte, word, or longword. in this case, memory byte or word data is sign-extended and operated on as longword data. immediate data is sign-extended to longword size for arithmetic operations (mov, add, and cmp/eq instructions) or zero-extended to longword size for logical operations (tst, and, or, and xor instructions). load/store architecture: basic operations are executed between registers. in operations involving memory, data is first loaded into a register (load/store architecture). however, bit manipulation instructions such as and are executed directly on memory. delayed branching: unconditional branch instructions are executed as delayed branches. with a delayed branch instruction, the branch is made after execution of the instruction (called the slot instruction) immediately following the delayed branch instruction. this minimizes disruption of the pipeline when a branch is made. this lsi supports two types of conditional branch instructions: delayed branch instruction or normal branch instruction. example: bra target add r1, r0 ; add is executed before branching to the target t bit: the result of a comparison is indicated by the t bit in the status register (sr), and a conditional branch is performed according to whether the result is true or false. processing speed has been improved by keeping the number of instructions that modify the t bit to a minimum. example: add #1, r0 ; the t bit cannot be modified by the add instruction cmp/eq #0, r0 ; the t bit is set to 1 if r0 is 0. bt target ; branch to target if the t bit is set to 1 (r0=0). rev. 1.0, 11/02, page 41 of 690 literal constant: byte literal constant is placed inside the instruction code as immediate data. since the instruction length is fixed to 16 bits, word and longword literal constant is not placed inside the instruction code, but in a table in memory. the table in memory is referenced with a mov instruction using pc-relative addressing mode with displacement. example: mov.w @(disp, pc) absolute addresses: when data is referenced by absolute address, the absolute address value is placed in a table in memory beforehand as well as word or longword literal constant. using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using register indirect addressing mode. 16-bit/32-bit displacement: when data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a table in memory beforehand. using the method whereby word or longword immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using indexed register indirect addressing mode. rev. 1.0, 11/02, page 42 of 690 2.5.2 cpu instruction addressing modes the following table shows addressing modes and effective address calculation methods for instructions executed by the cpu core. table 2.3 addressing modes and effective addresses for cpu instructions addressing mode instruction format effective address calculation method calculation formula register direct rn effective address is register rn. (operand is register rn contents.) ? register indirect @rn effective address is register rn contents. rn rn rn register indirect with post-increment @rn+ effective address is register rn contents. a constant is added to rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn rn 1/2/4 + rn + 1/2/4 rn after instruction execution byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn register indirect with pre-decrement @?rn effective address is register rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn rn - 1/2/4 1/2/4 - rn - 1/2/4 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn (instruction executed with rn after calculation) register indirect with displacement @(disp:4, rn) effective address is register rn contents with 4-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. rn rn + disp 1/2/4 1/2/4 + disp (zero-extended) byte: rn + disp word: rn + disp 2 longword: rn + disp 4 rev. 1.0, 11/02, page 43 of 690 addressing mode instruction format effective address calculation method calculation formula indexed register indirect @(r0, rn) effective address is sum of register rn and r0 contents. + rn r0 rn + r0 rn + r0 gbr indirect with displacement @(disp:8, gbr) effective address is register gbr contents with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. gbr gbr + disp 1/2/4 1/2/4 + disp (zero-extended) byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4 indexed gbr indirect @(r0, gbr) effective address is sum of register gbr and r0 contents. gbr gbr + r0 r0 + gbr + r0 pc-relative with displacement @(disp:8, pc) effective address is pc with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. with a longword operand, the lower 2 bits of pc are masked. pc pc + disp 2 or pc & h'fffffffc + disp 4 h'fffffffc + & 2/4 disp (zero-extended) * *: with longword operand word: pc + disp 2 longword: pc&h'fffffffc + disp 4 rev. 1.0, 11/02, page 44 of 690 addressing mode instruction format effective address calculation method calculation formula pc-relative disp:8 effective address is pc with 8-bit displacement disp added after being sign-extended and multiplied by 2. pc 2 disp (sign-extended) + pc + disp 2 pc + disp 2 disp:12 effective address is pc with 12-bit displacement disp added after being sign-extended and multiplied by 2 pc 2 disp (sign-extended) + pc + disp 2 pc + disp 2 rn effective address is sum of pc and rn. pc pc + rn rn + pc + rn #imm:8 8-bit immediate data imm of tst, and, or, or xor instruction is zero-extended. ? #imm:8 8-bit immediate data imm of mov, add, or cmp/eq instruction is sign-extended. ? immediate #imm:8 8-bit immediate data imm of trapa instruction is zero-extended and multiplied by 4. ? note: for addressing modes with displacement (disp) as shown below, the assembler description in this manual indicates the value before it is scaled (x 1, x2, or x4) according to the operand size to clarify the lsi operation. for details on assembler description, refer to the description rules in each assembler. @ (disp:4, rn) ; register indirect with displacement @ (disp:8, rn) ; gbr indirect with displacement @ (disp:8, pc) ; pc relative with displacement disp:8, disp ; pc relative rev. 1.0, 11/02, page 45 of 690 2.5.3 cpu instruction formats table 2.4 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the cpu core. the meaning of the operands depends on the instruction code. the following symbols are used in the table. xxxx: instruction code mmmm: source register nnnn: destination register iiii: immediate data dddd: displacement table 2.4 cpu instruction formats instruction format source operand destination operand sample instruction 0 type xxxx xxxx xxxx xxxx 15 0 ??nop n type xxxx nnnn xxxx xxxx 15 0 ? nnnn: register direct movt rn control register or system register nnnn: register direct sts mach,rn control register or system register nnnn: pre- decrement register indirect stc.l sr,@-rn m type xxxx mmmm xxxx xxxx 15 0 mmmm: register direct control register or system register ldc rm,sr mmmm: post- increment register indirect control register or system register ldc.l @rm+,sr mmmm: register indirect ?jmp@rm pc-relative using rm ?brafrm rev. 1.0, 11/02, page 46 of 690 instruction format source operand destination operand sample instruction nm type xxxx nnnn mmmm xxxx 15 0 mmmm: register direct nnnn: register direct add rm,rn mmmm: register indirect nnnn: register indirect mov.l rm,@rn mmmm: post- increment register indirect (multiply- and-accumulate operation) nnnn: * post- increment register indirect (multiply- and-accumulate operation) mach, macl mac.w @rm+,@rn+ mmmm: post- increment register indirect nnnn: register direct mov.l @rm+,rn mmmm: register direct nnnn: pre- decrement register indirect mov.l rm,@-rn mmmm: register direct nnnn: indexed register indirect mov.l rm,@(r0,rn) md type xxxx xxxx mmmm dddd 15 0 mmmmdddd: register indirect with displacement r0 (register direct) mov.b @(disp,rm),r0 nd4 type xxxx xxxx nnnn dddd 15 0 r0 (register direct) nnnndddd: register indirect with displacement mov.b r0,@(disp,rn) nmd type xxxx nnnn mmmm dddd 15 0 mmmm: register direct nnnndddd: register indirect with displacement mov.l rm,@(disp,rn) mmmmdddd: register indirect with displacement nnnn: register direct mov.l @(disp,rm),rn rev. 1.0, 11/02, page 47 of 690 instruction format source operand destination operand sample instruction d type xxxx xxxx dddd dddd 15 0 dddddddd: gbr indirect with displacement r0 (register direct) mov.l @(disp,gbr),r0 r0 (register direct) dddddddd: gbr indirect with displacement mov.l r0,@(disp,gbr) dddddddd: pc-relative with displacement r0 (register direct) mova @(disp,pc),r0 dddddddd: pc-relative ? bf label d12 type xxxx dddd dddd dddd 15 0 dddddddddddd: pc-relative ? bra label (label=disp+pc) nd8 type xxxx nnnn dddd dddd 15 0 dddddddd: pc- relative with displacement nnnn: register direct mov.l @(disp,pc),rn i type xxxx xxxx i i i i i i i i 15 0 iiiiiiii: immediate indexed gbr indirect and.b #imm,@(r0,gbr) iiiiiiii: immediate r0 (register direct) and #imm,r0 iiiiiiii: immediate ? trapa #imm ni type xxxx nnnn i i i i i i i i 15 0 iiiiiiii: immediate nnnn: register direct add #imm,rn note: * in multiply-and-accumulate instructions, nnnn is the source register. rev. 1.0, 11/02, page 48 of 690 2.6 instruction set 2.6.1 cpu instruction set based on functions the cpu instruction set consists of 68 basic instruction types divided into six functional groups, as shown in table 2.5. tables 2.6 to 2.11 show the instruction notation, machine code, execution time, and function. table 2.5 cpu instruction types type kinds of instruction op code function number of instructions mov data transfer immediate data transfer peripheral module data transfer structure data transfer 39 mova effective address transfer movt t bit transfer swap upper/lower swap data transfer instructions 5 xtrct extraction of middle of linked registers 21 add binary addition 33 addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division div0s signed division initialization div0u unsigned division initialization dmuls signed double-precision multiplication dmulu unsigned double-precision multiplication dt decrement and test exts sign extension extu zero extension mac multiply-and-accumulate, double- precision multiply-and-accumulate arithmetic operation instructions mul double-precision multiplication (32 32 bits) rev. 1.0, 11/02, page 49 of 690 type kinds of instruction op code function number of instructions 21 muls signed multiplication (16 16 bits) 33 mulu unsigned multiplication (16 16 bits) neg sign inversion negc sign inversion with borrow sub binary subtraction subc binary subtraction with carry arithmetic operation instructions subv binary subtraction with underflow 6 and logical and 14 not bit inversion or logical or tas memory test and bit setting tst logical and and t bit setting logic operation instructions xor exclusive logical or 12 rotl 1-bit left shift 16 rotr 1-bit right shift rotcl 1-bit left shift with t bit rotcr 1-bit right shift with t bit shal arithmetic 1-bit left shift shar arithmetic 1-bit right shift shll logical 1-bit left shift shlln logical n-bit left shift shlr logical 1-bit right shift shlrn logical n-bit right shift shad arithmetic dynamic shift shift instructions shld logical dynamic shift rev. 1.0, 11/02, page 50 of 690 type kinds of instruction op code function number of instructions 9 bf conditional branch, delayed conditional branch (t = 0) 11 bt conditional branch, delayed conditional branch (t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure branch instructions rts return from subroutine procedure 15 clrt t bit clear 75 clrmac mac register clear clrs s bit clear ldc load into control register lds load into system register ldtlb pteh/ptel load into tlb nop no operation pref data prefetch to cache rte return from exception handling sets s bit setting sett t bit setting sleep transition to power-down mode stc store from control register sts store from system register system control instructions trapa trap exception handling total: 68 188 rev. 1.0, 11/02, page 51 of 690 the instruction code, operation, and number of execution states of the cpu instructions are shown in the following tables, classified by instruction type, using the format shown below. instruction instruction code operation privilege execution states t bit indicated by mnemonic. explanation of symbols op.sz src, dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement indicated in msb ? lsb order. explanation of symbols mmmm: source register nnnn: destination register 0000: r0 0001: r1 ......... 1111: r15 iiii: immediate data dddd: displacement * 2 indicates summary of operation. explanation of symbols , : transfer direction (xx): memory operand m/q/t: flag bits in sr &: logical and of each bit |: logical or of each bit ^: exclusive logical or of each bit ~: logical not of each bit < rev. 1.0, 11/02, page 52 of 690 table 2.6 data transfer instructions instruction instruction code operation privileged mode cycles t bit mov #imm,rn 1110nnnniiiiiiii imm sign extension rn ? 1 ? mov.w @(disp,pc),rn 1001nnnndddddddd (disp x 2+pc) sign extension rn ?1? mov.l @(disp,pc),rn 1101nnnndddddddd (disp x 4+pc) rn ? 1 ? mov rm,rn 0110nnnnmmmm0011 rm rn ? 1 ? mov.b rm,@rn 0010nnnnmmmm0000 rm (rn) ? 1 ? mov.w rm,@rn 0010nnnnmmmm0001 rm (rn) ? 1 ? mov.l rm,@rn 0010nnnnmmmm0010 rm (rn) ? 1 ? mov.b @rm,rn 0110nnnnmmmm0000 (rm) sign extension rn ? 1 ? mov.w @rm,rn 0110nnnnmmmm0001 (rm) sign extension rn ? 1 ? mov.l @rm,rn 0110nnnnmmmm0010 (rm) rn ? 1 ? mov.b rm,@?rn 0010nnnnmmmm0100 rn?1 rn, rm (rn) ? 1 ? mov.w rm,@?rn 0010nnnnmmmm0101 rn?2 rn, rm (rn) ? 1 ? mov.l rm,@?rn 0010nnnnmmmm0110 rn?4 rn, rm (rn) ? 1 ? mov.b @rm+,rn 0110nnnnmmmm0100 (rm) sign extension rn, rm+1 rm ?1? mov.w @rm+,rn 0110nnnnmmmm0101 (rm) sign extension rn, rm+2 rm ?1? mov.l @rm+,rn 0110nnnnmmmm0110 (rm) rn, rm+4 rm ? 1 ? mov.b r0,@(disp,rn) 10000000nnnndddd r0 (disp+rn) ? 1 ? mov.w r0,@(disp,rn) 10000001nnnndddd r0 (disp x 2+rn) ? 1 ? mov.l rm,@(disp,rn) 0001nnnnmmmmdddd rm (disp x 4+rn) ? 1 ? mov.b @(disp,rm),r0 10000100mmmmdddd (disp+rm) sign extension r0 ? 1 ? mov.w @(disp,rm),r0 10000101mmmmdddd (disp x 2+rm) sign extension r0 ?1? mov.l @(disp,rm),rn 0101nnnnmmmmdddd (disp x 4+rm) rn ? 1 ? mov.b rm,@(r0,rn) 0000nnnnmmmm0100 rm (r0+rn) ? 1 ? mov.w rm,@(r0,rn) 0000nnnnmmmm0101 rm (r0+rn) ? 1 ? mov.l rm,@(r0,rn) 0000nnnnmmmm0110 rm (r0+rn) ? 1 ? rev. 1.0, 11/02, page 53 of 690 instruction instruction code operation privileged mode cycles t bit mov.b @(r0,rm),rn 0000nnnnmmmm1100 (r0+rm) sign extension rn ? 1 ? mov.w @(r0,rm),rn 0000nnnnmmmm1101 (r0+rm) sign extension rn ? 1 ? mov.l @(r0,rm),rn 0000nnnnmmmm1110 (r0+rm) rn ? 1 ? mov.b r0,@(disp,gbr) 11000000dddddddd r0 (disp+gbr) ? 1 ? mov.w r0,@(disp,gbr) 11000001dddddddd r0 (disp x 2+gbr) ? 1 ? mov.l r0,@(disp,gbr) 11000010dddddddd r0 (disp x 4+gbr) ? 1 ? mov.b @(disp,gbr),r0 11000100dddddddd (disp+gbr) sign extension r0 ?1? mov.w @(disp,gbr),r0 11000101dddddddd (disp x 2+gbr) sign extension r0 ?1? mov.l @(disp,gbr),r0 11000110dddddddd (disp x 4+gbr) r0 ? 1 ? mova @(disp,pc),r0 11000111dddddddd disp x 4+pc r0 ? 1 ? movt rn 0000nnnn00101001 t rn ? 1 ? swap.b rm,rn 0110nnnnmmmm1000 rm swap lowest two bytes rn ?1? swap.w rm,rn 0110nnnnmmmm1001 rm swap two consecutive words rn ?1? xtrct rm,rn 0010nnnnmmmm1101 rm: middle 32 bits of rn rn ? 1 ? rev. 1.0, 11/02, page 54 of 690 table 2.7 arithmetic operation instructions instruction instruction code operation privileged mode cycles t bit add rm,rn 0011nnnnmmmm1100 rn+rm rn ? 1 ? add #imm,rn 0111nnnniiiiiiii rn+imm rn ? 1 ? addc rm,rn 0011nnnnmmmm1110 rn+rm+t rn, carry t ? 1 carry addv rm,rn 0011nnnnmmmm1111 rn+rm rn, overflow t? 1overflow cmp/eq #imm,r0 10001000iiiiiiii if r0 = imm, 1 t?1 comparison result cmp/eq rm,rn 0011nnnnmmmm0000 if rn = rm, 1 t?1 comparison result cmp/hs rm,rn 0011nnnnmmmm0010 if rn rm with unsigned data, 1 t ?1 comparison result cmp/ge rm,rn 0011nnnnmmmm0011 if rn rm with signed data, 1 t ?1 comparison result cmp/hi rm,rn 0011nnnnmmmm0110 if rn > rm with unsigned data, 1 t ?1 comparison result cmp/gt rm,rn 0011nnnnmmmm0111 if rn > rm with signed data, 1 t ?1 comparison result cmp/pl rn 0100nnnn00010101 if rn 0, 1 t?1 comparison result cmp/pz rn 0100nnnn00010001 if rn > 0, 1 t?1 comparison result cmp/str rm,rn 0010nnnnmmmm1100 if rn and rm have an equivalent byte, 1 t ?1 comparison result div1 rm,rn 0011nnnnmmmm0100 single-step division (rn/rm) ? 1 calculation result div0s rm,rn 0010nnnnmmmm0111 msb of rn q, msb of rm m, m ^ q t ?1 calculation result div0u 0000000000011001 0 m/q/t ? 1 0 dmuls.l rm,rn 0011nnnnmmmm1101 signed operation of rn rm mach, macl 32 32 64 bits ?2 (to 5) * ? dmulu.l rm,rn 0011nnnnmmmm0101 unsigned operation of rn rm mach, macl 32 32 64 bits ?2 (to 5) * ? dt rn 0100nnnn00010000 rn ? 1 rn, if rn = 0, 1 t, else 0 t ?1 comparison result rev. 1.0, 11/02, page 55 of 690 instruction instruction code operation privileged mode cycles t bit exts.b rm,rn 0110nnnnmmmm1110 a byte in rm is sign-extended rn ?1? exts.w rm,rn 0110nnnnmmmm1111 a word in rm is sign-extended rn ?1? extu.b rm,rn 0110nnnnmmmm1100 a byte in rm is zero-extended rn ?1? extu.w rm,rn 0110nnnnmmmm1101 a word in rm is zero-extended rn ?1? mac.l @rm+, @rn+ 0000nnnnmmmm1111 signed operation of (rn) (rm) + mac mac,rn + 4 rn, rm + 4 rm, 32 32 + 64 64 bits ? 2 (to 5) * ? mac.w @rm+, @rn+ 0100nnnnmmmm1111 signed operation of (rn) (rm) + mac mac,rn + 2 rn, rm + 2 rm, 16 16 + 64 64 bits ? 2 (to 5) * ? mul.l rm,rn 0000nnnnmmmm0111 rn rm macl, 32 32 32 bits ? 2 (to 5) * ? muls.w rm,rn 0010nnnnmmmm1111 signed operation of rn rm macl, 16 16 32 bits ? 1(to 3) * ? mulu.w rm,rn 0010nnnnmmmm1110 unsigned operation of rn rm macl, 16 16 32 bits ? 1(to 3) * ? neg rm,rn 0110nnnnmmmm1011 0?rm rn ? 1 ? negc rm,rn 0110nnnnmmmm1010 0?rm?t rn, borrow t ? 1 borrow sub rm,rn 0011nnnnmmmm1000 rn?rm rn ? 1 ? subc rm,rn 0011nnnnmmmm1010 rn?rm?t rn, borrow t ? 1 borrow subv rm,rn 0011nnnnmmmm1011 rn?rm rn, underflow t ? 1 underflow note: * the number of execution cycles indicated within the parentheses ( ) are required when the operation result is read from the mach/macl register immediately after the instruction. rev. 1.0, 11/02, page 56 of 690 table 2.8 logic operation instructions instruction instruction code operation privileged mode cycles t bit and rm,rn 0010nnnnmmmm1001 rn & rm rn ? 1 ? and #imm,r0 11001001iiiiiiii r0 & imm r0 ? 1 ? and.b #imm,@(r0, gbr) 11001101iiiiiiii (r0+gbr) & imm (r0+gbr) ? 3 ? not rm,rn 0110nnnnmmmm0111 ~ rm rn ? 1 ? or rm,rn 0010nnnnmmmm1011 rn ? rm rn ? 1 ? or #imm,r0 11001011iiiiiiii r0 ? imm r0 ? 1 ? or.b #imm,@(r0, gbr) 11001111iiiiiiii (r0+gbr) ? imm (r0+gbr) ? 3 ? tas.b @rn 0100nnnn00011011 if (rn) is 0, 1 t; 1 msb of (rn) ?4test result tst rm,rn 0010nnnnmmmm1000 rn & rm; if the result is 0, 1 t? 1 test result tst #imm,r0 11001000iiiiiiii r0 & imm; if the result is 0, 1 t? 1 test result tst.b #imm,@(r0, gbr) 11001100iiiiiiii (r0 + gbr) & imm; if the result is 0, 1 t ?3test result xor rm,rn 0010nnnnmmmm1010 rn ^ rm rn ? 1 ? xor #imm,r0 11001010iiiiiiii r0 ^ imm r0 ? 1 ? xor.b #imm,@(r0, gbr) 11001110iiiiiiii (r0+gbr) ^ imm (r0+gbr) ? 3 ? rev. 1.0, 11/02, page 57 of 690 table 2.9 shift instructions instruction instruction code operation privileged mode cycles t bit rotl rn 0100nnnn00000100 t rn msb ? 1 msb rotr rn 0100nnnn00000101 lsb rn t?1lsb rotcl rn 0100nnnn00100100 t rn t?1msb rotcr rn 0100nnnn00100101 t rn t?1lsb shad rm, rn 0100nnnnmmmm1100 rn 0: rn << rm rn rn < 0: rn >> rm [msb rn] ?1? shal rn 0100nnnn00100000 t rn 0?1msb shar rn 0100nnnn00100001 msb rn t?1lsb shld rm, rn 0100nnnnmmmm1101 rn 0: rn << rm rn rn < 0: rn >> rm [0 rn] ?1? shll rn 0100nnnn00000000 t rn 0?1msb shlr rn 0100nnnn00000001 0 rn t?1lsb shll2 rn 0100nnnn00001000 rn<<2 rn ? 1 ? shlr2 rn 0100nnnn00001001 rn>>2 rn ? 1 ? shll8 rn 0100nnnn00011000 rn<<8 rn ? 1 ? shlr8 rn 0100nnnn00011001 rn>>8 rn ? 1 ? shll16 rn 0100nnnn00101000 rn<<16 rn ? 1 ? shlr16 rn 0100nnnn00101001 rn>>16 rn ? 1 ? rev. 1.0, 11/02, page 58 of 690 table 2.10 branch instructions instruction instruction code operation privileged mode cycles t bit bf disp 10001011dddddddd if t = 0, disp 2 + pc pc; if t = 1, nop ?3/1 * ? bf/s disp 10001111dddddddd delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop ?2/1 * ? bt disp 10001001dddddddd if t = 1, disp 2 + pc pc; if t = 0, nop ?3/1 * ? bt/s disp 10001101dddddddd delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop ?2/1 * ? bra disp 1010dddddddddddd delayed branch, disp 2 + pc pc ?2? braf rm 0000mmmm00100011 delayed branch,rm + pc pc ? 2 ? bsr disp 1011dddddddddddd delayed branch, pc pr, disp 2 + pc pc ?2? bsrf rm 0000mmmm00000011 delayed branch, pc pr, rm + pc pc ?2? jmp @rm 0100mmmm00101011 delayed branch, rm pc ? 2 ? jsr @rm 0100mmmm00001011 delayed branch, pc pr, rm pc ?2? rts 0000000000001011 delayed branch, pr pc ? 2 ? note: * one state when the branch is not executed. rev. 1.0, 11/02, page 59 of 690 table 2.11 system control instructions instruction instruction code operation privileged mode cycles t bit clrm ac 0000000000101000 0 mach,macl ? 1 ? clrs 0000000001001000 0 s?1? clrt 0000000000001000 0 t?10 ldc rm,sr 0100mmmm00001110 rm sr 6lsb ldc rm,gbr 0100mmmm00011110 rm gbr ? 4 ? ldc rm,vbr 0100mmmm00101110 rm vbr 4? ldc rm,ssr 0100mmmm00111110 rm ssr 4? ldc rm,spc 0100mmmm01001110 rm spc 4? ldc rm,r0_bank 0100mmmm10001110 rm r0_bank 4? ldc rm,r1_bank 0100mmmm10011110 rm r1_bank 4? ldc rm,r2_bank 0100mmmm10101110 rm r2_bank 4? ldc rm,r3_bank 0100mmmm10111110 rm r3_bank 4? ldc rm,r4_bank 0100mmmm11001110 rm r4_bank 4? ldc rm,r5_bank 0100mmmm11011110 rm r5_bank 4? ldc rm,r6_bank 0100mmmm11101110 rm r6_bank 4? ldc rm,r7_bank 0100mmmm11111110 rm r7_bank 4? ldc.l @rm+,sr 0100mmmm00000111 (rm) sr, rm+4 rm 8lsb ldc.l @rm+,gbr 0100mmmm00010111 (rm) gbr, rm+4 rm ? 4 ? ldc.l @rm+,vbr 0100mmmm00100111 (rm) vbr, rm+4 rm 4? ldc.l @rm+,ssr 0100mmmm00110111 (rm) ssr, rm+4 rm 4? ldc.l @rm+,spc 0100mmmm01000111 (rm) spc, rm+4 rm 4? ldc.l @rm+, r0_bank 0100mmmm10000111 (rm) r0_bank, rm+4 rm 4? ldc.l @rm+, r1_bank 0100mmmm10010111 (rm) r1_bank, rm+4 rm 4? ldc.l @rm+, r2_bank 0100mmmm10100111 (rm) r2_bank, rm+4 rm 4? ldc.l @rm+, r3_bank 0100mmmm10110111 (rm) r3_bank, rm+4 rm 4? ldc.l @rm+, r4_bank 0100mmmm11000111 (rm) r4_bank, rm+4 rm 4? ldc.l @rm+, r5_bank 0100mmmm11010111 (rm) r5_bank, rm+4 rm 4? rev. 1.0, 11/02, page 60 of 690 instruction instruction code operation privileged mode cycles t bit ldc.l @rm+, r6_bank 0100mmmm11100111 (rm) r6_bank, rm+4 rm 4? ldc.l @rm+, r7_bank 0100mmmm11110111 (rm) r7_bank, rm+4 rm 4? lds rm,mach 0100mmmm00001010 rm mach ? 1 ? lds rm,macl 0100mmmm00011010 rm macl ? 1 ? lds rm,pr 0100mmmm00101010 rm pr ? 1 ? lds.l @rm+,mach 0100mmmm00000110 (rm) mach, rm+4 rm ? 1 ? lds.l @rm+,macl 0100mmmm00010110 (rm) macl, rm+4 rm ? 1 ? lds.l @rm+,pr 0100mmmm00100110 (rm) pr, rm+4 rm ? 1 ? ldtlb 0000000000111000 pteh/ptel tlb 1? nop 0000000000001001 no operation ? 1 ? pref @rm 0000mmmm10000011 (rm) cache ? 1 ? rte 0000000000101011 delayed branch, ssr sr, spc pc 5? sets 0000000001011000 1 s?1? sett 0000000000011000 1 t?11 sleep 0000000000011011 sleep 4 * 1 ? stc sr,rn 0000nnnn00000010 sr rn 1? stc gbr,rn 0000nnnn00010010 gbr rn ? 1 ? stc vbr,rn 0000nnnn00100010 vbr rn 1? stc ssr, rn 0000nnnn00110010 ssr rn 1? stc spc,rn 0000nnnn01000010 spc rn 1? stc r0_bank,rn 0000nnnn10000010 r0_bank rn 1? stc r1_bank,rn 0000nnnn10010010 r1_bank rn 1? stc r2_bank,rn 0000nnnn10100010 r2_bank rn 1? stc r3_bank,rn 0000nnnn10110010 r3_bank rn 1? stc r4_bank,rn 0000nnnn11000010 r4_bank rn 1? stc r5_bank,rn 0000nnnn11010010 r5_bank rn 1? stc r6_bank,rn 0000nnnn11100010 r6_bank rn 1? stc r7_bank,rn 0000nnnn11110010 r7_bank rn 1? stc.l sr,@?rn 0100nnnn00000011 rn?4 rn, sr (rn) 1? stc.l gbr,@?rn 0100nnnn00010011 rn?4 rn, gbr (rn) ? 1 ? stc.l vbr,@?rn 0100nnnn00100011 rn?4 rn, vbr (rn) 1? rev. 1.0, 11/02, page 61 of 690 instruction instruction code operation privileged mode cycles t bit stc.l ssr,@?rn 0100nnnn00110011 rn?4 rn, ssr (rn) 1? stc.l spc,@?rn 0100nnnn01000011 rn?4 rn, spc (rn) 1? stc.l r0_bank,@?rn 0100nnnn10000011 rn?4 rn, r0_bank (rn) 1? stc.l r1_bank,@?rn 0100nnnn10010011 rn?4 rn, r1_bank (rn) 1? stc.l r2_bank,@?rn 0100nnnn10100011 rn?4 rn, r2_bank (rn) 1? stc.l r3_bank,@?rn 0100nnnn10110011 rn?4 rn, r3_bank (rn) 1? stc.l r4_bank,@?rn 0100nnnn11000011 rn?4 rn, r4_bank (rn) 1? stc.l r5_bank,@?rn 0100nnnn11010011 rn?4 rn, r5_bank (rn) 1? stc.l r6_bank,@?rn 0100nnnn11100011 rn?4 rn, r6_bank (rn) 1? stc.l r7_bank,@?rn 0100nnnn11110011 rn?4 rn, r7_bank (rn) 1? sts mach,rn 0000nnnn00001010 mach rn ? 1 ? sts macl,rn 0000nnnn00011010 macl rn ? 1 ? sts pr,rn 0000nnnn00101010 pr rn ? 1 ? sts.l mach,@?rn 0100nnnn00000010 rn?4 rn, mach (rn) ? 1 ? sts.l macl,@?rn 0100nnnn00010010 rn?4 rn, macl (rn) ? 1 ? sts.l pr,@?rn 0100nnnn00100010 rn?4 rn, pr (rn) ? 1 ? trapa #imm 11000011iiiiiiii unconditional trap exception occurs * 3 ?8? notes: * number of states before the chip enters the sleep state. 1. the table shows the minimum number of clocks required for execution. in practice, the number of execution cycles will be increased in the following conditions. a. if there is a conflict between an instruction fetch and a data access b. if the destination register of a load instruction (memory register) is also used by the following instruction. 2. for addressing modes with displacement (disp) as shown below, the assembler description in this manual indicates the value before it is scaled (x 1, x2, or x4) according to the operand size to clarify the lsi operation. for details on assembler description, refer to the description rules in each assembler. @ (disp:4, rn) ; register indirect with displacement @ (disp:8, rn) ; gbr indirect with displacement @ (disp:8, pc) ; pc relative with displacement disp:8, disp ; pc relative 3. for details, refer to section 5, exception handling. rev. 1.0, 11/02, page 62 of 690 2.6.2 operation code map table 2.12 shows the operation code map. table 2.12 operation code map instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0000 rn fx 0000 0000 rn fx 0001 0000 rn 00md 0010 stc sr, rn 0000 rn 01md 0010 stc spc, rn stc gbr, rn stc vbr, rn stc ssr, rn 0000 rn 10md 0010 stc r0_bank, rn stc r1_bank, rn stc r2_bank, rn stc r3_bank, rn 0000 rn 11md 0010 stc r4_bank, rn stc r6_bank, rn stc r7_bank, rn 0000 rm 00md 0011 bsrf rm 0000 rm 10md 0011 pref @rm stc r5_bank, rn braf rm 0000 rn rm 01md mov.b rm, @(r0, rn) mov.w rm, @(r0, rn) mov.l rm,@(r0, rn) mul.l rm, rn 0000 0000 00md 1000 clrt sett 0000 0000 01md 1000 clrs sets 0000 0000 fx 1001 0000 0000 fx 1010 nop div0u clrmac 0000 0000 fx 1011 0000 rn fx 1000 rte 0000 rn fx 1001 rts sleep movt rn 0000 rn fx 1010 0000 rn fx 1011 sts mach, rn sts macl, rn sts pr, rn ldtlb 0000 rn rm 11md mov. b @(r0, rm), rn mov.w @(r0, rm), rn mov.l @(r0, rm), rn mac.l @rm+,@rn+ 0001 rn rm disp mov.l rm, @(disp:4, rn) 0010 rn rm 00md mov.b rm, @rn mov.w rm, @rn mov.l rm, @rn 0010 rn rm 01md mov.b rm, @?rn mov.w rm, @?rn mov.l rm, @?rn div0s rm, rn 0010 rn rm 10md tst rm, rn and rm, rn xor rm, rn or rm, rn 0010 rn rm 11md cmp/str rm, rn mulu.w rm, rn mulsw rm, rn 0011 rn rm 00md cmp/eq rm, rn xtrct rm, rn cmp/hs rm, rn cmp/ge rm, rn rev. 1.0, 11/02, page 63 of 690 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0011 rn rm 01md div1 rm, rn cmp/hi rm, rn cmp/gt rm, rn 0011 rn rm 10md sub rm, rn dmulu.l rm,rn subc rm, rn subv rm, rn 0011 rn rm 11md add rm, rn dmuls.l rm,rn addc rm, rn 0100 rn fx 0000 shll rn dt rn shal rn 0100 rn fx 0001 shlr rn cmp/pz rn shar rn 0100 rn fx 0010 sts.l mach, @?rn sts.l macl, @? rn sts.l pr, @? rn addv rm, rn 0100 rn 00md 0011 stc.l sr, @?rn 0100 rn 01md 0011 stc.l spc, @?rn stc.l gbr, @?rn stc.l vbr, @?rn stc.l ssr, @?rn 0100 rn 10md 0011 stc.l r0_bank, @?rn stc.l r1_bank, @?rn stc.l r2_bank, @?rn stc.l r3_bank, @?rn 0100 rn 11md 0011 stc.l r4_bank, @?rn stc.l r6_bank, @?rn 0100 rn fx 0100 rotl rn stc.l r5_bank, @?rn rotcl rn 0100 rn fx 0101 rotr rn cmp/pl rn rotcr rn 0100 rm fx 0110 lds.l @rm+, mach lds.l @rm+, macl lds.l @rm+, pr stc.l r7_bank, @?rn 0100 rm 00md 0111 ldc.l @rm+, sr 0100 rm 01md 0111 ldc.l @rm+, spc ldc.l @rm+, gbr ldc.l @rm+, vbr ldc.l @rm+, ssr 0100 rm 10md 0111 ldc.l @rm+, r0_bank ldc.l @rm+, r1_bank ldc.l @rm+, r2_bank ldc.l @rm+, r3_bank 0100 rm 11md 0111 ldc.l @rm+, r4_bank ldc.l @rm+, r5_bank ldc.l @rm+, r6_bank 0100 rn fx 1000 shll2 rn shll8 rn shll16 rn 0100 rn fx 1001 shlr2 rn shlr8 rn shlr16 rn 0100 rm fx 1010 lds rm, mach lds rm, macl lds rm, pr 0100 rm/ rn fx 1011 jsr @rm tas.b @rn jmp @rm ldc.l @rm+, r7_bank rev. 1.0, 11/02, page 64 of 690 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0100 rn rm 1100 shad rm, rn 0100 rn rm 1101 shld rm, rn 0100 rm 00md 1110 ldc rm, sr 0100 rm 01md 1110 ldc rm, spc ldc rm, gbr ldc rm, vbr ldc rm, ssr 0100 rm 10md 1110 ldc rm, r0_bank ldc rm, r1_bank ldc rm, r2_bank ldc rm, r3_bank 0100 rm 11md 1110 ldc rm, r4_bank ldc rm, r5_bank ldc rm, r6_bank ldc rm, r7_bank 0100 rn rm 1111 mac.w rm+, rn+ 0101 rn rm disp mov.l (disp:4, rm), rn 0110 rn rm 00md mov.b @rm, rn mov.w @rm, rn mov.l @rm, rn mov rm, rn 0110 rn rm 01md mov.b @rm+, rn mov.w @rm+, rn mov.l @rm+, rn not rm, rn 0110 rn rm 10md swap.b rm, rn swap.w rm, rn negc rm, rn neg rm, rn 0110 rn rm 11md extu.b rm, rn extu.w rm, rn exts.b rm, rn exts.w rm, rn 0111 rn imm add # imm : 8, rn 1000 00md rn disp mov. b r0, @(disp: 4, rn) mov. w r0, @(disp: 4, rn) 1000 01md rm disp mov.b @(disp:4, rm), r0 mov.w @(disp: 4, rm), r0 1000 10md imm/disp bt disp: 8 bf disp: 8 1000 11md imm/disp cmp/eq #imm:8, r0 bt/s disp: 8 bf/s disp: 8 1001 rn disp mov.w (disp : 8, pc), rn 1010 disp bra disp: 12 1011 disp bsr disp: 12 1100 00md imm/disp mov.b r0, @(disp: 8, gbr) mov.w r0, @(disp: 8, gbr) mov.l r0, @(disp: 8, gbr) trapa #imm: 8 1100 01md disp mov.b @(disp: 8, gbr), r0 mov.w @(disp: 8, gbr), r0 mov.l @(disp: 8, gbr), r0 mova @(disp: 8, pc), r0 1100 10md imm tst #imm: 8, r0 and #imm: 8, r0 xor #imm: 8, r0 or #imm: 8, r0 1100 11md imm tst.b #imm: 8, @(r0, gbr) and.b #imm: 8, @(r0, gbr) xor.b #imm: 8, @(r0, gbr) or.b #imm: 8, @(r0, gbr) 1101 rn disp mov.l @(disp: 8, pc), rn 1110 rn imm mov #imm:8, rn 1111 ************ note: for details, refer to the sh-3/sh-3h/sh3-dsp programming manual. rev. 1.0, 11/02, page 65 of 690 section 3 memory management unit (mmu) this lsi has an on-chip memory management unit (mmu) that supports a virtual memory system. the on-chip translation look-aside buffer (tlb) caches information for user-created address translation tables located in external memory. it enables high-speed translation of virtual addresses into physical addresses. address translation uses the paging system and supports two page sizes (1 kbyte or 4 kbytes). the access rights to virtual address space can be set for each of the privileged and user modes to provide memory protection. 3.1 role of mmu the mmu is a feature designed to make efficient use of physical memory. as shown in figure 3.1, if a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory. however, if the process increases in size to the extent that it no longer fits into physical memory, it becomes necessary to partition the process and to map those parts requiring execution onto memory as occasion demands (figure 3.1 (1)). having the process itself consider this mapping onto physical memory would impose a large burden on the process. to lighten this burden, the idea of virtual memory was born as a means of performing en bloc mapping onto physical memory (figure 3.1 (2)). in a virtual memory system, substantially more virtual memory than physical memory is provided, and the process is mapped onto this virtual memory. thus a process only has to consider operation in virtual memory. mapping from virtual memory to physical memory is handled by the mmu. the mmu is normally controlled by the operating system, switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion. switching of physical memory is performed via secondary storage, etc. the virtual memory system that came into being in this way is particularly effective in a time- sharing system (tss) in which a number of processes are running simultaneously (figure 3.1 (3)). if processes running in a tss had to take mapping onto virtual memory into consideration while running, it would not be possible to increase efficiency. virtual memory is thus used to reduce this load on the individual processes and so improve efficiency (figure 3.1 (4)). in the virtual memory system, virtual memory is allocated to each process. the task of the mmu is to perform efficient mapping of these virtual memory areas onto physical memory. it also has a memory protection feature that prevents one process from inadvertently accessing another process?s physical memory. when address translation from virtual memory to physical memory is performed using the mmu, it may occur that the relevant translation information is not recorded in the mmu, with the result that one process may inadvertently access the virtual memory allocated to another process. in this case, the mmu will generate an exception, change the physical memory mapping, and record the new address translation information. although the functions of the mmu could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would mmus300s_000020020300 rev. 1.0, 11/02, page 66 of 690 result in poor efficiency. for this reason, a buffer for address translation (translation look-aside buffer: tlb) is provided in hardware to hold frequently used address translation information. the tlb can be described as a cache for storing address translation information. unlike cache memory, however, if address translation fails, that is, if an exception is generated, switching of address translation information is normally performed by software. this makes it possible for memory management to be performed flexibly by software. the mmu has two methods of mapping from virtual memory to physical memory: a paging method using fixed-length address translation, and a segment method using variable-length address translation. with the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 kbytes) called a page. in the following text, the address space in virtual memory is referred to as virtual address space, and address space in physical memory as physical memory space. process 1 physical memory physical memory process 1 mmu physical memory process 1 process 3 process 2 process 1 process 1 process 2 process 3 virtual memory mmu (1) (2) (3) (4) physical memory physical memory virtual memory figure 3.1 mmu functions rev. 1.0, 11/02, page 67 of 690 3.1.1 mmu of this lsi virtual address space: this lsi supports a 32-bit virtual address space that enables access to a 4-gbyte address space. as shown in figures 3.2 and 3.3, the virtual address space is divided into several areas. in privileged mode, a 4-gbyte space comprising areas p0 to p4 is accessible. in user mode, a 2-gbyte space of u0 area is accessible. access to any area excluding the u0 area in user mode will result in an address error. if the mmu is enabled by setting the at bit of the mmucr register to 1, p0, p3, and u0 areas can be used as any physical address area in 1- or 4-kbyte page units. by using an 8-bit address space identifier, p0, p2, and u0 areas can be increased to up to 256 areas. mapping from virtual address to 29-bit physical address can be achieved by the tlb. 1. p0, p3, and u0 areas the p0, p3, and u0 areas can be address translated by the tlb and can be accessed through the cache. if the mmu is enabled, these areas can be mapped to any physical address space in 1- or 4-kbyte page units via the tlb. if the ce bit in the cache control register (ccr1) is set to 1 and if the corresponding cache enable bit (c bit) of the tlb entry is set to 1, access via the cache is enabled. if the mmu is disabled, replacing the upper three bits of an address in these areas with 0s creates the address in the corresponding physical address space. if the ce bit of the ccr1 register is set to 1, access via the cache is enabled. when the cache is used, either the copy-back or write-through mode is selected for write access via the wt bit in ccr1. if these areas are mapped to the on-chip module control register area in area 1 in the physical address space via the tlb, the c bit of the corresponding page must be cleared to 0. 2. p1 area the p1 area can be accessed via the cache and cannot be address-translated by the tlb. whether the mmu is enabled or not, replacing the upper three bits of an address in these areas with 0s creates the address in the corresponding physical address space. use of the cache is determined by the ce bit in the cache control register (ccr1). when the cache is used, either the copy-back or write-through mode is selected for write access by the cb bit in the ccr1 register. 3. p2 area the p2 area cannot be accessed via the cache and cannot be address-translated by the tlb. whether the mmu is enabled or not, replacing the upper three bits of an address in this area with 0s creates the address in the corresponding physical address space. 4. p4 area the p4 area is mapped to the on-chip module control register of this lsi. this area cannot be accessed via the cache and cannot be address-translated by the tlb. figure 3.4 shows the configuration of the p4 area. rev. 1.0, 11/02, page 68 of 690 h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff area p0 cacheable address translation possible area u0 cacheable address translation possible area p1 cacheable address translation not possible area p2 non-cacheable address translation not possible area p3 cacheable address translation possible area p4 non-cacheable address translation not possible address error h'0000 0000 h'8000 0000 h'ffff ffff h'0000 0000 privileged mode user mode area 0 area 1 area 2 area 3 area 4 area 5 area 7 area 6 external address space 256 256 figure 3.2 virtual address space (mmucr.at = 1) rev. 1.0, 11/02, page 69 of 690 h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff area p0 cacheable area u0 cacheable area p1 cacheable area p2 non-cacheable area p3 cacheable area p4 non-cacheable address error h'0000 0000 h'8000 0000 h'ffff ffff h'0000 0000 privileged mode user mode area 0 area 1 area 2 area 3 area 4 area 5 area 7 area 6 external address space figure 3.3 virtual address space (mmucr.at = 0) h'f000 0000 h'f100 0000 h'f200 0000 h'f300 0000 h'f400 0000 h'ffff ffff h'fc00 0000 reserved area reserved area cache address array cache data array tlb address array tlb data array h'e000 0000 control register area figure 3.4 p4 area rev. 1.0, 11/02, page 70 of 690 the area from h'f000 0000 to h'f0ff ffff is for direct access to the cache address array. for more information, see section 4.4, memory-mapped cache. the area from h'f100 0000 to h'f1ff ffff is for direct access to the cache data array. for more information, see section 4.4, memory-mapped cache. the area from h'f200 0000 to h'f2ff ffff is for direct access to the tlb address array. for more information, see section 3.6, memory-mapped tlb. the area from h'f300 0000 to h'f3ff ffff is for direct access to the tlb data array. for more information, see section 3.6, memory-mapped tlb. the area from h'fc00 0000 to h'ffff ffff is reserved for the on-chip module control registers. for more information, see section 24, list of registers. physical address space: this lsi supports a 29-bit physical address space. as shown in figure 3.5, the physical address space is divided into eight areas. area 1 is mapped to the on-chip module control register area. area 7 is reserved. for details on physical address space, refer to section 7, bus state controller (bsc). h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1c00 0000 h'1fff ffff h'1800 0000 area 0 area 1 (on-chip module control register) area 2 area 3 area 4 area 5 area 6 area 7 (reserved area) h'0000 0000 figure 3.5 external memory space rev. 1.0, 11/02, page 71 of 690 address transition: when the mmu is enabled, the virtual address space is divided into units called pages. physical addresses are translated in page units. address translation tables in external memory hold information such as the physical address that corresponds to the virtual address and memory protection codes. when an access to area p1 or p2 occurs, there is no tlb access and the physical address is defined uniquely by hardware. if it belongs to area p0, p3 or u0, the tlb is searched by virtual address and, if that virtual address is registered in the tlb, the access hits the tlb. the corresponding physical address and the page control information are read from the tlb and the physical address is determined. if the virtual address is not registered in the tlb, a tlb miss exception occurs and processing will shift to the tlb miss handler. in the tlb miss handler, the tlb address translation table in external memory is searched and the corresponding physical address and the page control information are registered in the tlb. after returning from the handler, the instruction that caused the tlb miss is re-executed. when the mmu is enabled, address translation information that results in a physical address space of h'20000000 to h'ffffffff should not be registered in the tlb. when the mmu is disabled, masking the upper three bits of the virtual address to 0s creates the address in the corresponding physical address space. since this lsi supports 29-bit address space as physical address space, the upper three bits of the virtual address are ignored as shadow areas. for details, refer to section 7, bus state controller (bsc). for example, address h?00001000 in the p0 area, address h?80001000 in the p1 area, address h?a0001000 in the p2 area, and address h?c0001000 in the p3 area are all mapped to the same physical memory. if these addresses are accessed while the cache is enabled, the upper three bits are always cleared to 0 to guarantee the continuity of addresses stored in the address array of the cache. single virtual memory mode and multiple virtual memory mode: there are two virtual memory modes: single virtual memory mode and multiple virtual memory mode. in single virtual memory mode, multiple processes run in parallel using the virtual address space exclusively and the physical address corresponding to a given virtual address is specified uniquely. in multiple virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a given virtual address may be translated into different physical addresses depending on the process. by the value set to the mmu control register (mmucr), either single or multiple virtual mode is selected. in terms of operation, the only difference between single virtual memory mode and multiple virtual memory mode is in the tlb address comparison method (see section 3.3.3, tlb address comparison). address space identifier (asid): in multiple virtual memory mode, the address space identifier (asid) is used to differentiate between processes running in parallel and sharing virtual address space. the asid is eight bits in length and can be set by software setting of the asid of the currently running process in page table entry register high (pteh) within the mmu. when the process is switched using the asid, the tlb does not have to be purged. rev. 1.0, 11/02, page 72 of 690 in single virtual memory mode, the asid is used to provide memory protection for processes running simultaneously and using the virtual address space exclusively (see section 3.3.3, tlb address comparison). 3.2 register descriptions there are four registers for mmu processing. these are all on-chip module control registers, so they are located in address space area p4 and can only be accessed from privileged mode by specifying the address. the mmu has the following registers. refer to section 24, list of registers, for the addresses and access size for these registers. ? page table entry register high (pteh) ? page table entry register low (ptel) ? translation table base register (ttb) ? mmu control register (mmucr) 3.2.1 page table entry register high (pteh) the page table entry register high (pteh) register residing at address h'fffffff0, which consists of a virtual page number (vpn) and asid. the vpn set is the vpn of the virtual address at which the exception is generated in case of an mmu exception or address error exception. when the page size is 4 kbytes, the vpn is the upper 20 bits of the virtual address, but in this case the upper 22 bits of the virtual address are set. the vpn can also be modified by software. as the asid, software sets the number of the currently executing process. the vpn and asid are recorded in the tlb by the ldtlb instruction. a program that modifies the asid in pteh should be allocated in the p1 or p2 areas. bit bit name initial value r/w description 31 to 10 vpn ? r/w number of virtual page 9, 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 asid ? r/w address space identifier rev. 1.0, 11/02, page 73 of 690 3.2.2 page table entry register low (ptel) the page table entry register low (ptel) register residing at address h'fffffff4, and used to store the physical page number and page management information to be recorded in the tlb by the ldtlb instruction. the contents of this register are only modified in response to a software command. bit bit name initial value r/w description 31 to 29 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 28 to 10 ppn ? r number of physical page 9 8 7 6, 5 4 3 2 1 0 ? v ? pr sz c d sh ? 0 ? 0 ? ? ? ? ? 0 r/w page management information for more details, see section 3.3, tlb functions 3.2.3 translation table base register (ttb) the translation table base register (ttb) residing at address h'fffffff8, which points to the base address of the current page table. the hardware does not set any value in ttb automatically. ttb is available to software for general purposes. the initial value is undefined. 3.2.4 mmu control register (mmucr) the mmu control register (mmucr) residing at address h'ffffffe0, which makes the mmu settings described in figure 3.3. any program that modifies mmucr should reside in the p1 or p2 area. rev. 1.0, 11/02, page 74 of 690 bit bit name initial value r/w description 31 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8sv ? r/w single virtual memory mode 0: multiple virtual memory mode 1: single virtual memory mode 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5, 4 rc all 0 r/w random counter a 2-bit random counter that is automatically updated by hardware according to the following rules in the event of an mmu exception. when a tlb miss exception occurs, all of tlb entry ways corresponding to the virtual address at which the exception occurred are checked. if all ways are valid, 1 is added to rc; if there is one or more invalid way, they are set by priority from way 0, in the order way 0, way 1, way 2, and way 3. in the event of an mmu exception other than a tlb miss exception, the way which caused the exception is set in rc. 3 ? 0rreserved these bits are always read as 0. the write value should always be 0. 2tf0r/wtlb flush write 1 to flush the tlb (clear all valid bits of the tlb to 0). when they are read, 0 is always returned. 1 ix 0 r/w index mode 0: vpn bits 16 to 12 are used as the tlb index number. 1: the value obtained by ex-oring asid bits 4 to 0 in pteh and vpn bits 16 to 12 is used as the tlb index number. 0 at 0 r/w address translation enables/disables the mmu. 0: mmu disabled 1: mmu enabled rev. 1.0, 11/02, page 75 of 690 3.3 tlb functions 3.3.1 configuration of the tlb the tlb caches address translation table information located in the external memory. the address translation table stores the logical page number and the corresponding physical number, the address space identifier, and the control information for the page, which is the unit of address translation. figure 3.6 shows the overall tlb configuration. the tlb is 4-way set associative with 128 entries. there are 32 entries for each way. figure 3.7 shows the configuration of virtual addresses and tlb entries. entry 1 address array data array entry 0 entry 1 entry 31 way 0 to 3 way 0 to 3 vpn(11-10) vpn(31-17) asid(7-0) v entry 0 entry 31 ppn(28-10) pr(1-0) sz c d sh figure 3.6 overall configuration of the tlb rev. 1.0, 11/02, page 76 of 690 31 9 vpn virtual address (1-kbyte page) virtual address (4-kbyte page) tlb entry offset vpn vpn (31-17) vpn (11-0) asid v pr sz sh ppn c d offset 0 10 31 11 0 (15) (2) (2) (8) (1) (19) (1) (1) (1) (1) 12 legend: vpn: virtual page number upper 22 bits of virtual address for a 1-kbyte page, or upper 20 bits of virtual address for a 4-kbyte page. since vpn bits 16 to 12 are used as the index number, they are not stored in the tlb entry. attention must be paid to the synonym problem (see section 3.4.4, avoiding synonym problems). asid: address space identifier indicates the process that can access a virtual page. in single virtual memory mode and user mode, or in multiple virtual memory mode, if the sh bit is 0, the address is compared with the asid in pteh when address comparison is performed. sh: share status bit 0: page not shared between processes 1: page shared between processes sz: page-size bit 0: 1-kbyte page 1: 4-kbyte page v: valid bit indicates whether entry is valid. 0: invalid 1: valid cleared to 0 by a power-on reset. not affected by a manual reset. ppn: physical page number upper 22 bits of physical address. ppn bits 11 to10 are not used in case of a 4-kbyte page. pr: protection key field 2-bit field encoded to define the access rights to the page. 00: reading only is possible in privileged mode. 01: reading/writing is possible in privileged mode. 10: reading only is possible in privileged/user mode. 11: reading/writing is possible in privileged/user mode. c: cacheable bit indicates whether the page is cacheable. 0: non-cacheable 1: cacheable d: dirty bit indicates whether the page has been written to. 0: not written to 1: written to figure 3.7 virtual address and tlb structure rev. 1.0, 11/02, page 77 of 690 3.3.2 tlb indexing the tlb uses a 4-way set associative scheme, so entries must be selected by index. vpn bits 16 to 12 are used as the index number regardless of the page size. the index number can be generated in two different ways depending on the setting of the ix bit in mmucr. 1. when ix = 0, vpn bits 16 to 12 alone are used as the index number 2. when ix = 1, vpn bits 16 to 12 are ex-ored with asid bits 4 to 0 to generate a 5-bit index number the first method is used to prevent lowered tlb efficiency that results when multiple processes run simultaneously in the same virtual address space (multiple virtual memory) and a specific entry is selected by indexing of each process. in single virtual memory mode (mmucr.sv = 1), ix bit should be set to 0. figures 3.8 and 3.9 show the indexing schemes. 31 16 11 12 17 0 31 0 pteh register virtual address vpn 0 asid 7 10 index asid(4-0) exclusive-or way 0 to 3 vpn(31-17) vpn(11-10) asid(7-0) v 0 31 address array data array ppn(28-10) pr(1-0) sz c d sh figure 3.8 tlb indexing (ix = 1) rev. 1.0, 11/02, page 78 of 690 31 16 11 12 17 0 virtual address index way 0 to 3 vpn(31-17) vpn(11-10) asid(7-0) v 0 31 address array data array ppn(28-10) pr(1-0) sz c d sh figure 3.9 tlb indexing (ix = 0) 3.3.3 tlb address comparison the results of address comparison determine whether a specific virtual page number is registered in the tlb. the virtual page number of the virtual address that accesses external memory is compared to the virtual page number of the indexed tlb entry. the asid within the pteh is compared to the asid of the indexed tlb entry. all four ways are searched simultaneously. if the compared values match, and the indexed tlb entry is valid (v bit = 1), the hit is registered. it is necessary to have software ensure that tlb hits do not occur simultaneously in more than one way, as hardware operation is not guaranteed if this occurs. an example of setting which causes tlb hits to occur simultaneously in more than one way is described below. it is necessary to ensure that this kind of setting is not made by software. 1. if there are two identical tlb entries with the same vpn and a setting is made such that a tlb hit is made only by a process with asid = h?ff when one is in the shared state (sh = 1) and the other in the non-shared state (sh = 0), then if the asid in pteh is set to h?ff, there is a possibility of simultaneous tlb hits in both these ways. 2. if several entries which have different asid with the same vpn are registered in single virtual memory mode, there is the possibility of simultaneous tlb hits in more than one way when accessing the corresponding page in privileged mode. several entries with the same vpn must not be registered in single virtual memory mode. 3. there is the possibility of simultaneous tlb hits in more than one way. these hits may occur depending on the contents of asid in pteh when a page to which sh is set 1 is registered in the tlb in index mode (mmucr.ix = 1). therefore a page to which sh is set 1 must not be registered in index mode. when memory is shared by several processings, different pages must be registered in each asid. rev. 1.0, 11/02, page 79 of 690 the object compared varies depending on the page management information (sz, sh) in the tlb entry. it also varies depending on whether the system supports multiple virtual memory or single virtual memory. the page-size information determines whether vpn (11 to 10) is compared. vpn (11 to 10) is compared for 1-kbyte pages (sz = 0) but not for 4-kbyte pages (sz = 1). the sharing information (sh) determines whether the pteh.asid and the asid in the tlb entry are compared. asids are compared when there is no sharing between processes (sh = 0) but not when there is sharing (sh = 1). when single virtual memory is supported (mmucr.sv = 1) and privileged mode is engaged (sr.md = 1), all process resources can be accessed. this means that asids are not compared when single virtual memory is supported and privileged mode is engaged. the objects of address comparison are shown in figure 3.10. sh = 1 or (sr.md = 1 and mmucr.sv = 1)? sz = 0? sz = 0? no no (4-kbyte) yes yes (1-kbyte) no (4-kbyte) yes (1-kbyte) bits compared: vpn 31 to 17 vpn 11 to 10 bits compared: vpn 31 to 17 bits compared: vpn 31 to 17 vpn 11 to 10 asid 7 to 0 bits compared: vpn 31 to 17 asid 7 to 0 figure 3.10 objects of address comparison rev. 1.0, 11/02, page 80 of 690 3.3.4 page management information in addition to the sh and sz bits, the page management information of tlb entries also includes d, c, and pr bits. the d bit of a tlb entry indicates whether the page is dirty (i.e., has been written to). if the d bit is 0, an attempt to write to the page results in an initial page write exception. for physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. to record that there has been a write to a given page in the address translation table in memory, an initial page write exception is used. the c bit in the entry indicates whether the referenced page resides in a cacheable or non- cacheable area of memory. when the on-chip module control registers in area 1 are mapped, set the c bit to 0. the pr field specifies the access rights for the page in privileged and user modes and is used to protect memory. attempts at non-permitted accesses result in tlb protection violation exceptions. access states designated by the d, c, and pr bits are shown in table 3.1. table 3.1 access states designated by d, c, and pr bits privileged mode user mode reading writing reading writing d bit 0 permitted initial page write exception permitted initial page write exception 1 permitted permitted permitted permitted c bit 0 permitted (no caching) permitted (no caching) permitted (no caching) permitted (no caching) 1 permitted (with caching) permitted (with caching) permitted (with caching) permitted (with caching) pr bit 00 permitted tlb protection violation exception tlb protection violation exception tlb protection violation exception 01 permitted permitted tlb protection violation exception tlb protection violation exception 10 permitted tlb protection violation exception permitted tlb protection violation exception 11 permitted permitted permitted permitted rev. 1.0, 11/02, page 81 of 690 3.4 mmu functions 3.4.1 mmu hardware management there are two kinds of mmu hardware management as follows. 1. the mmu decodes the virtual address accessed by a process and performs address translation by controlling the tlb in accordance with the mmucr settings. 2. in address translation, the mmu receives page management information from the tlb, and determines the mmu exception and whether the cache is to be accessed (using the c bit). for details of the determination method and the hardware processing, see section 3.5, mmu exceptions. 3.4.2 mmu software management there are three kinds of mmu software management, as follows. 1. mmu register setting mmucr setting, in particular, should be performed in areas p1 and p2 for which address translation is not performed. also, since sv and ix bit changes constitute address translation system changes, in this case, tlb flushing should be performed by simultaneously writing 1 to the tf bit also. since mmu exceptions are not generated in the mmu disabled state with the at bit cleared to 0, use in the disabled state must be avoided with software that does not use the mmu. 2. tlb entry recording, deletion, and reading tlb entry recording can be done in two ways by using the ldtlb instruction, or by writing directly to the memory-mapped tlb. for tlb entry deletion and reading, the memory allocation tlb can be accessed. see section 3.4.3, mmu instruction (ldtlb), for details of the ldtlb instruction, and section 3.6, memory-mapped tlb, for details of the memory- mapped tlb. 3. mmu exception processing when an mmu exception is generated, it is handled on the basis of information set from the hardware side. see section 3.5, mmu exceptions, for details. when single virtual memory mode is used, it is possible to create a state in which physical memory access is enabled in the privileged mode only by clearing the share status bit (sh) to 0 to specify recording of all tlb entries. this strengthens inter-process memory protection, and enables special access levels to be created in the privileged mode only. recording a 1- or 4- kbyte page tlb entry may result in a synonym problem. see section 3.4.4, avoiding synonym problems. rev. 1.0, 11/02, page 82 of 690 3.4.3 mmu instruction (ldtlb) the load tlb instruction (ldtlb) is used to record tlb entries. when the ix bit in mmucr is 0, the ldtlb instruction changes the tlb entry in the way specified by the rc bit in mmucr to the value specified by pteh and ptel, using vpn bits 16 to 12 specified in pteh as the index number. when the ix bit in mmucr is 1, the ex-or of vpn bits 16 to 12 specified in pteh and asid bits 4 to 0 in pteh are used as the index number. figure 3.11 shows the case where the ix bit in mmucr is 0. when an mmu exception occurs, the virtual page number of the virtual address that caused the exception is set in pteh by hardware. the way is set in the rc bit of mmucr for each exception according to the rules (see section 3.2.4, mmu control registers). consequently, if the ldtlb instruction is issued after setting only ptel in the mmu exception processing routine, tlb entry recording is possible. any tlb entry can be updated by software rewriting of pteh and the rc bits in mmucr. as the ldtlb instruction changes address translation information, there is a risk of destroying address translation information if this instruction is issued in the p0, u0, or p3 area. make sure, therefore, that this instruction is issued in the p1 or p2 area. also, an instruction associated with an access to the p0, u0, or p3 area (such as the rte instruction) should be issued at least two instructions after the ldtlb instruction. vpn(31-17) vpn(11-10) asid(7-0) v vpn 0 asid vpn 0 sv 0 0 rc 0 tf ix at ppn 0 0 v 0 pr sz c d sh 0 write ppn(28-10) pr(1-0) sz c d sh write data array address array way selection way 0 to 3 31 9 0 mmucr index 31 17 12 10 8 0 pteh register 31 29 28 10 0 ptel register 0 31 0 0 figure 3.11 operation of ldtlb instruction rev. 1.0, 11/02, page 83 of 690 3.4.4 avoiding synonym problems when a 1- or 4-kbyte page is recorded in a tlb entry, a synonym problem may arise. if a number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. the reason that this problem occurs is explained below with reference to figure 3.12. the relationship between bit n of the virtual address and cache size is shown in the following table. note that no synonym problems occur in 4-kbyte page when the cache size is 16 kbytes. cache size bit n in virtual address 16 kbytes 11 32 kbytes 12 to achieve high-speed operation of this lsi?s cache, an index number is created using virtual address bits 12 to 4. when a 1-kbyte page is used, virtual address bits 12 to 10 is subject to address translation and when a 4-kbyte page is used, a virtual address bit 12 is subject to address translation. therefore, the physical address bits 12 to 10 may not be the same as the virtual address bits 12 to 10. for example, assume that, with 1-kbyte page tlb entries, tlb entries for which the following translation has been performed are recorded in two tlbs: virtual address 1 h'00000000 physical address h'00000c00 virtual address 2 h'00000c00 physical address h'00000c00 virtual address 1 is recorded in cache entry h'000, and virtual address 2 in cache entry h'0c0. since two virtual addresses are recorded in different cache entries despite the fact that the physical addresses are the same, memory inconsistency will occur as soon as a write is performed to either virtual address. consequently, the following restrictions apply to the recording of address translation information in tlb entries. 1. when address translation information whereby a number of 1-kbyte page tlb entries are translated into the same physical address is recorded in the tlb, ensure that the vpn bits 12 to 10 are the same. 2. when address translation information whereby a number of 4-kbyte page tlb entries are translated into the same physical address is recorded in the tlb, ensure that the vpn bit 12 is the same. 3. do not use the same physical addresses for address translation information of different page sizes. rev. 1.0, 11/02, page 84 of 690 the above restrictions apply only when performing accesses using the cache. note: when multiple items of address translation information use the same physical memory to provide for future superh risc engine family expansion, ensure that the vpn bits 20 to 10 are the same. ? when using a 4-kbyte page virtual address 31 vpn 0 12 13 11 10 offset physical address 28 ppn 0 offset virtual address 12 to 4 physical address 28 to 10 cache when using a 1-kbyte page virtual address 31 vpn 0 10 11 12 13 offset physical address 28 ppn 0 10 11 12 13 offset virtual address 12 to 4 physical address 28 to 10 cache 12 13 11 10 figure 3.12 synonym problem (32-kbyte cache) rev. 1.0, 11/02, page 85 of 690 3.5 mmu exceptions when the address translation unit of the mmu is enabled, occurrence of the mmu exception is checked following the cpu address error check. there are four mmu exceptions: tlb miss, tlb protection violation, tlb invalid, and initial page write, and these mmu exceptions are checked in this order. 3.5.1 tlb miss exception a tlb miss results when the virtual address and the address array of the selected tlb entry are compared and no match is found. tlb miss exception processing includes both hardware and software operations. hardware operations: in a tlb miss, this hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. either exception code h'040 for a load access, or h'060 for a store access, is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written to the save program counter (spc). if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written to the spc. 5. the contents of the status register (sr) at the time of the exception are written to the save status register (ssr). 6. the mode (md) bit in sr is set to 1 to place the privileged mode. 7. the block (bl) bit in sr is set to 1 to mask any further exception requests. 8. the register bank (rb) bit in sr is set to 1. 9. the rc field in the mmu control register (mmucr) is incremented by 1 when all entries indexed are valid. when some entries indexed are invalid, the smallest way number of them is set in rc. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000400 to invoke the user-written tlb miss exception handler. software (tlb miss handler) operations: the software searches the page tables in external memory and allocates the required page table entry. upon retrieving the required page table entry, software must execute the following operations: 1. write the value of the physical page number (ppn) field and the protection key (pr), page size (sz), cacheable (c), dirty (d), share status (sh), and valid (v) bits of the page table entry recorded in the address translation table in the external memory into the ptel register. rev. 1.0, 11/02, page 86 of 690 2. if using software for way selection for entry replacement, write the desired value to the rc field in mmucr. 3. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 4. issue the return from exception handler (rte) instruction to terminate the handler routine and return to the instruction stream. 3.5.2 tlb protection violation exception a tlb protection violation exception results when the virtual address and the address array of the selected tlb entry are compared and a valid entry is found to match, but the type of access is not permitted by the access rights specified in the pr field. tlb protection violation exception processing includes both hardware and software operations. hardware operations: in a tlb protection violation exception, this hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. either exception code h'0a0 for a load access, or h'0c0 for a store access, is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written into spc (if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written into spc). 5. the contents of sr at the time of the exception are written to ssr. 6. the md bit in sr is set to 1 to place the privileged mode. 7. the bl bit in sr is set to 1 to mask any further exception requests. 8. the rb bit in sr is set to 1. 9. the way that generated the exception is set in the rc field in mmucr. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100 to invoke the tlb protection violation exception handler. software (tlb protection violation handler) operations: software resolves the tlb protection violation and issues the rte (return from exception handler) instruction to terminate the handler and return to the instruction stream. issue the rte instruction after issuing two instructions from the ldtlb instruction. rev. 1.0, 11/02, page 87 of 690 3.5.3 tlb invalid exception a tlb invalid exception results when the virtual address is compared to a selected tlb entry address array and a match is found but the entry is not valid (the v bit is 0). tlb invalid exception processing includes both hardware and software operations. hardware operations: in a tlb invalid exception, this hardware executes a set of prescribed operations, as follows: 1. the vpn number of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. either exception code h'040 for a load access, or h'060 for a store access, is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written to the spc. if the exception occurred in a delay slot, the pc value indicating the address of the delayed branch instruction is written to the spc. 5. the contents of sr at the time of the exception are written into ssr. 6. the mode (md) bit in sr is set to 1 to place the privileged mode. 7. the block (bl) bit in sr is set to 1 to mask any further exception requests. 8. the rb bit in sr is set to 1. 9. the way number causing the exception is written to rc in mmucr. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100, and the tlb protection violation exception handler starts. software (tlb invalid exception handler) operations: the software searches the page tables in external memory and assigns the required page table entry. upon retrieving the required page table entry, software must execute the following operations: 1. write the values of the physical page number (ppn) field and the values of the protection key (pr), page size (sz), cacheable (c), dirty (d), share status (sh), and valid (v) bits of the page table entry recorded in the external memory to the ptel register. 2. if using software for way selection for entry replacement, write the desired value to the rc field in mmucr. 3. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 4. issue the rte instruction to terminate the handler and return to the instruction stream. the rte instruction should be issued after two ldtlb instructions. rev. 1.0, 11/02, page 88 of 690 3.5.4 initial page write exception an initial page write exception results in a write access when the virtual address and the address array of the selected tlb entry are compared and a valid entry with the appropriate access rights is found to match, but the d (dirty) bit of the entry is 0 (the page has not been written to). initial page write exception processing includes both hardware and software operations. hardware operations: in an initial page write exception, this hardware executes a set of prescribed operations, as follows: 1. the vpn field of the virtual address causing the exception is written to the pteh register. 2. the virtual address causing the exception is written to the tea register. 3. exception code h'080 is written to the expevt register. 4. the pc value indicating the address of the instruction in which the exception occurred is written to the spc. if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written to the spc. 5. the contents of sr at the time of the exception are written to ssr. 6. the md bit in sr is set to 1 to place the privileged mode. 7. the bl bit in sr is set to 1 to mask any further exception requests. 8. the rb bit in sr is set to 1. 9. the way that caused the exception is set in the rc field in mmucr. 10. execution branches to the address obtained by adding the value of the vbr contents and h'00000100 to invoke the user-written initial page write exception handler. software (initial page write handler) operations: the software must execute the following operations: 1. retrieve the required page table entry from external memory. 2. set the d bit of the page table entry in the external memory to 1. 3. write the value of the ppn field and the pr, sz, c, d, sh, and v bits of the page table entry in the external memory to the ptel register. 4. if using software for way selection for entry replacement, write the desired value to the rc field in mmucr. 5. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. 6. issue the rte instruction to terminate the handler and return to the instruction stream. the rte instruction must be issued after two ldtlb instructions. rev. 1.0, 11/02, page 89 of 690 start sh = 0 and (mmucr.sv = 0 or sr.md = 0)? vpns and asids match? v=1? user or privileged? d=1? c=1? memory access cache access initial page write exception tlb protection violation exception pr? tlb protection violation exception r/w? r/w? r/w? r/w? pr? tlb invalid exception tlb miss exception cpu address error vpns match? no no no no (non-cacheable) yes (cacheable) yes yes yes yes yes no address error? yes no no user mode privileged mode 01/11 00/10 00/01 10 11 wwww r rrr figure 3.13 mmu exception generation flowchart rev. 1.0, 11/02, page 90 of 690 3.6 memory-mapped tlb in order for tlb operations to be managed by software, tlb contents can be read or written to in the privileged mode using the mov instruction. the tlb is assigned to the p4 area in the virtual address space. the tlb address array (vpn, v bit, and asid) is assigned to h'f2000000 to h'f2ffffff, and the data array (ppn, pr, sz, c, d, and sh bits) to h'f3000000 to h'f3ffffff. the v bit in the address array can also be accessed from the data array. only longword access is possible for both the address array and the data array. however, the instruction data cannot be fetched from both arrays. 3.6.1 address array the address array is assigned to h'f2000000 to h'f2ffffff. to access an address array, the 32- bit address field (for read/write operations) and 32-bit data field (for write operations) must be specified. the address field specifies information for selecting the entry to be accessed; the data field specifies the vpn, v bit and asid to be written to the address array (figure 3.14 (1)). in the address field, specify the entry address for selecting the entry (bits 16 to 12), w for selecting the way (bits 9 to 8) and h'f2 to indicate address array access (bits 31 to 24). the ix bit in mmucr indicates whether an ex-or is taken of the entry address and asid. the following two operations can be used on the address array: 1. address array read vpn, v, and asid are read from the tlb entry corresponding to the entry address and way set in the address field. 2. tlb address array write the data specified in the data field are written to the tlb entry corresponding to the entry address and way set in the address field. 3.6.2 data array the data array is assigned to h'f3000000 to h'f3ffffff. to access a data array, the 32-bit address field (for read/write operations), and 32-bit data field (for write operations) must be specified. the address section specifies information for selecting the entry to be accessed; the data section specifies the longword data to be written to the data array (figure 3.14 (2)). in the address section, specify the entry address for selecting the entry (bits 16 to 12), w for selecting the way (bits 9 to 8), and h'f3 to indicate data array access (bits 31 to 24). the ix bit in mmucr indicates whether an ex-or is taken of the entry address and asid. both reading and writing use the longword of the data array specified by the entry address and way number. the access size of the data array is fixed at longword. rev. 1.0, 11/02, page 91 of 690 1 1 1 1 0 0 1 0 9 vpn: virtual page number v: valid bit w: way (00: way 0, 01: way 1, 10: way 2, 11: way 3) asid: address space identifier * : don ? t care bit address field data field address field data field address field data field 31 24 23 17 16 12 1110 9 8 7 0 31 17 16 12 1110 9 8 7 0 31 24 23 17 16 12 11 11 10 9 8 7 0 31 17 16 12 10 9 8 7 0 31 24 23 29 28 17 16 12 1110 9 8 7 0 1 2 31 10 8 7 0 6 654321 0 0 0 vpn 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1 (1) tlb address array access read access write access (2) tlb data array access read/write access 6 * . . . . . . . . . . . . * vpn w 0 ** * . . . . . . . . . * vpn 0 . . . . . . . 0 vpn 0 v asid * . . . . . . . . . . . . * vpn * . . . . . . . * w0 * . . . . . . . . . * * * vpn v * asid * . . . . . . . . . . . . * vpn w * . . . . . . . . . . . * * * ppn xvx pr sz cd sh x ppn: physical page number pr: protection key field c: cacheable bit sh: share status bit vpn: virtual page number x: 0 for read, don ? t care bit for write w: way (00: way 0, 01: way 1, 10: way 2, 11: way 3) v: valid bit sz: page-size bit d: dirty bit * : don ? t care bit 00 1 2 00 1 2 00 figure 3.14 specifying address and data for memory-mapped tlb access rev. 1.0, 11/02, page 92 of 690 3.6.3 usage examples invalidating specific entries: specific tlb entries can be invalidated by writing 0 to the entry?s v bit. r0 specifies the write data and r1 specifies the address. ; r0=h'1547 381c r1=h'f201 3000 ; mmucr.ix=0 ; the v bit of way 0 of the entry selected by the vpn(16?12)=b'1 0011 ; index is cleared to0,achieving invalidation. mov.l r0,@r1 reading the data of a specific entry: this example reads the data section of a specific tlb entry. the bit order indicated in the data field in figure 3.14 (2) is read. r0 specifies the address and the data section of a selected entry is read to r1. ; r0 = h'f300 4300 vpn(16-12)=b'00100 way 3 ; mov.l @r0,r1 3.7 usage note the following operations should be performed in the p1 or p2 areas. in addition, when the p0, p3, or u0 areas are accessed consecutively (this access includes instruction fetching), the instruction code should be placed at least two instructions after the instruction that executes the following operations. 1. modification of sr.md or sr.bl 2. execution of the ldtlb instruction 3. write to the memory-mapped tlb 4. modification of mmucr 5. modification of pteh.asid rev. 1.0, 11/02, page 93 of 690 section 4 cache 4.1 features ? capacity: 16 or 32 kbytes ? structure: instructions/data mixed, 4-way set associative ? locking: way 2 and way 3 are lockable ? line size: 16 bytes ? number of entries: 256 entries/way in 16-kbyte mode or 512 entries/way in 32-kbyte mode ? write system: write-back/write-through is selectable for spaces p0, p1, p3, and u0 group 1 (p0, p3, and u0 areas) group 2 (p1 area) ? replacement method: least-recently used (lru) algorithm note: after power-on reset or manual reset, initialized as 16-kbyte mode (256 entries/way). 4.1.1 cache structure the cache mixes instructions and data and uses a 4-way set associative system. it is composed of four ways (banks), and each of which is divided into an address section and a data section. note that the following sections will be described for the 32-kbyte mode as an example. for other cache size modes, change the number of entries and size/way according to table 4.1. each of the address and data sections is divided into 512 entries. the entry data is called a line. each line consists of 16 bytes (4 bytes 4). the data capacity per way is 8 kbytes (16 bytes 512 entries) in the cache as a whole (4 ways). the cache capacity is 32 kbytes as a whole. figure 4.1 shows the cache structure. table 4.1 number of entries and size/way in each cache size cache size number of entries size/way 16 kbytes 256 4 kbytes 32 kbytes 512 8 kbytes cach000s_000020020300 rev. 1.0, 11/02, page 94 of 690 24 (1 + 1 + 22) bits 128 (32 4) bits 6 bits lw0 to lw3: longword data 0?3 entry 0 entry 1 entry 511 0 1 511 0 1 511 v u tag address lw0 lw1 lw2 lw3 address array (ways 0?3) data array (ways 0?3) lru . . . . . . . . . . . . . . . . . . figure 4.1 cache structure (32-kbyte mode) address array: the v bit indicates whether the entry data is valid. when the v bit is 1, data is valid; when 0, data is not valid. the u bit indicates whether the entry has been written to in write- back mode. when the u bit is 1, the entry has been written to; when 0, it has not. the tag address holds the physical address used in the external memory access. it is composed of 22 bits (address bits 31 to 10) used for comparison during cache searches. in this lsi, the top three of 32 physical address bits are used as shadow bits (see section 7, bus state controller (bsc)), and therefore the top three bits of the tag address are cleared to 0. the v and u bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. the tag address is not initialized by either a power-on or manual reset. data array: holds a 16-byte instruction or data. entries are registered in the cache in line units (16 bytes). the data array is not initialized by a power-on or manual reset. lru: with the 4-way set associative system, up to four instructions or data with the same entry address can be registered in the cache. when an entry is registered, lru shows which of the four ways it is recorded in. there are six lru bits, controlled by hardware. a least-recently-used (lru) algorithm is used to select the way. six lru bits indicate the way to be replaced, when a cache miss occurs. table 4.2 shows the relationship between the lru bits and the way to be replaced when the cache locking mechanism is disabled. (for the relationship when the cache locking mechanism is enabled, refer to section 4.2.2, cache control register 2.) if a bit pattern other than those listed in table 4.2 is set in the lru bits by software, the cache will not function correctly. when modifying the lru bits by software, set one of the patterns listed in table 4.2. the lru bits are initialized to 000000 by a power-on reset, but are not initialized by a manual reset. rev. 1.0, 11/02, page 95 of 690 table 4.2 lru and way replacement (when cache locking mechanism is disabled) lru (bits 5 to 0) way to be replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0 4.2 register descriptions the cache has the following registers. for details on register addresses and register states during each process, refer to section 24, list of registers. ? cache control register 1 (ccr1) ? cache control register 2 (ccr2) ? cache control register 3 (ccr3) rev. 1.0, 11/02, page 96 of 690 4.2.1 cache control register 1 (ccr1) the cache is enabled or disabled using the ce bit in ccr1. ccr1 also has a cf bit (which invalidates all cache entries), and wt and cb bits (which select either write-through mode or write-back mode). programs that change the contents of the ccr1 register should be placed in address space that is not cached. bit bit name initial value r/w description 31 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 cf 0 r/w cache flush writing 1 flushes all cache entries (clears the v, u, and lru bits of all cache entries to 0). this bit is always read as 0. write-back to external memory is not performed when the cache is flushed. 2 cb 0 r/w write-back indicates the cache?s operating mode for space p1. 0: write-through mode 1: write-back mode 1 wt 0 r/w write-through indicates the cache?s operating mode for spaces p0, u0, and p3. 0: write-back mode 1: write-through mode 0 ce 0 r/w cache enable indicates whether the cache function is used. 0: the cache function is not used. 1: the cache function is used. rev. 1.0, 11/02, page 97 of 690 4.2.2 cache control register 2 (ccr2) the ccr2 register controls the cache locking mechanism in cache lock mode only. the cpu enters the cache lock mode when the lock enable bit (bit 16) in the cache control register 2 (ccr2) is set to 1. the cache locking mechanism is disabled in non-cache lock mode (dsp bit = 0). when a prefetch instruction (pref@rn) is issued in cache lock mode and a cache miss occurs, the line of data pointed to by rn will be loaded into the cache, according to the setting of bits 9 and 8 (w3load, w3lock) and bits 1 and 0 (w2load, w2lock in ccr2). table 4.3 shows the relationship between the settings of bits and the way that is to be replaced when the cache is missed by a prefetch instruction. on the other hand, when the cache is hit by a prefetch instruction, new data is not loaded into the cache and the valid entry is held. for example, a prefetch instruction is issued while bits w3load and w3lock are set to 1 and the line of data to which rn points is already in way 0, the cache is hit and new data is not loaded into way 3. in cache lock mode, bits w3lock and w2lock restrict the way that is to be replaced, when instructions other than the prefetch instruction are issued. table 4.4 shows the relationship between the settings of bits in ccr2 and the way that is to be replaced when the cache is missed by instructions other than the prefetch instruction. programs that change the contents of the ccr2 register should be placed in address space that is not cached. rev. 1.0, 11/02, page 98 of 690 bit bit name initial value r/w description 31 to 17 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 16 le 0 r/w lock enable (le) controls cache lock mode. 0: does not enter cache lock mode. 1: enters cache lock mode. 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 w3load w3lock 0 0 r/w r/w way 3 load (w3load) way 3 lock (w3lock) when the cache is missed by a prefetch instruction while in cache lock mode and when bits w3load and w3lock in ccr2 are set to 1, the data is always loaded into way 3. under any other condition, the prefetched data is loaded into the way to which lru points. 7 to 2? all 0r reserved these bits are always read as 0. the write value should always be 0. 1 0 w2load w2lock 0 0 r/w r/w way 2 load (w2load) way 2 lock (w2lock) when the cache is missed by a prefetch instruction while in cache lock mode and when bits w2load and w2lock in ccr2 are set to 1, the data is always loaded into way 2. under any other condition, the prefetched data is loaded into the way to which lru points. note: w2load and w3load should not be set to 1 at the same time. rev. 1.0, 11/02, page 99 of 690 table 4.3 way replacement when a pref instruction misses the cache dsp bit w3load w3lock w2load w2lock way to be replaced 0 **** determined by lru (table 4.2) 1 * 0 * 0 determined by lru (table 4.2) 1 * 0 0 1 determined by lru (table 4.5) 10 1 * 0 determined by lru (table 4.6) 1 0 1 0 1 determined by lru (table 4.7) 10 * 11way 2 1110 * way 3 note: * don?t care w3load and w2load should not be set to 1 at the same time. table 4.4 way replacement when instructions other than the pref instruction miss the cache dsp bit w3load w3lock w2load w2lock way to be replaced 0 **** determined by lru (table 4.2) 1 * 0 * 0 determined by lru (table 4.2) 1 * 0 * 1 determined by lru (table 4.5) 1 * 1 * 0 determined by lru (table 4.6) 1 * 1 * 1 determined by lru (table 4.7) note: * don?t care w3load and w2load should not be set to 1 at the same time. table 4.5 lru and way replacement (when w2lock = 1 and w3lock = 0) lru (bits 5 to 0) way to be replaced 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 3 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 1 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 0 table 4.6 lru and way replacement (when w2lock = 0 and w3lock = 1) lru (bits 5 to 0) way to be replaced 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 2 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 1 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 rev. 1.0, 11/02, page 100 of 690 table 4.7 lru and way replacement (when w2lock = 1 and w3lock = 1) lru (bits 5 to 0) way to be replaced 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 1 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 4.2.3 cache control register 3 (ccr3) the ccr3 register controls the cache size to be used. the cache size must be specified according to the lsi to be selected. if the specified cache size exceeds the size of cache incorporated in the lsi, correct operation cannot be guaranteed. note that programs that change the contents of the ccr3 register should be placed in un-cached address space. in addition, note that all cache entries must be invalidated by setting the cf bit of the ccr1 to 1 before accessing the cache after the ccr3 is modified. bit bit name initial value r/w description 31 to 24 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 23 to 16 csize7 to csize0 h?01 r/w cache size specify the cache size as shown below. 0000 0001: 16-kbyte cache 0000 0010: 32-kbyte cache settings other than above are prohibited. 15 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 101 of 690 4.3 operation 4.3.1 searching the cache if the cache is enabled (the ce bit in ccr1 = 1), whenever instructions or data in spaces p0, p1, p3, and u0 are accessed the cache will be searched to see if the desired instruction or data is in the cache. figure 4.2 illustrates the method by which the cache is searched. the cache is a physical cache and holds physical addresses in its address section. the following will be described for the 32-kbyte mode as an example. entries are selected using bits 12 to 4 of the address (virtual) of the access to memory and the tag address of that entry is read. the virtual address (bits 31 to 10) of the access to memory and the physical address (tag address) read from the address array are compared. the address comparison uses all four ways. when the comparison shows a match and the selected entry is valid (v = 1), a cache hit occurs. when the comparison does not show a match or the selected entry is not valid (v = 0), a cache miss occurs. figure 4.2 shows a hit on way 1. 0 1 511 v u tag address lw0 lw1 lw2 lw3 ways 0 to 3 ways 0 to 3 31 13 12 4 3 2 1 0 virtual address cmp0 cmp1 cmp2 cmp3 physical address cmp0: comparison circuit 0 cmp1: comparison circuit 1 cmp2: comparison circuit 2 cmp3: comparison circuit 3 hit signal 1 entry selection longword (lw) selection mmu figure 4.2 cache search scheme rev. 1.0, 11/02, page 102 of 690 4.3.2 read access read hit: in a read access, instructions and data are transferred from the cache to the cpu. the lru i s updated to indicate that the hit way is the most recently hit way. read miss: an external bus cycle starts and the entry is updated. the way to be replaced is shown in table 4.3. entries are updated in 16-byte units. when the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the cpu in parallel with being loaded to the cache. when it is loaded to the cache, the u bit is cleared to 0 and the v bit is set to 1 to indicate that the hit way is the most recently hit way. when the u bit for the entry which is to be replaced by entry updating in write-back mode is 1, the cache- update cycle starts after the entry is transferred to the write-back buffer. after the cache completes its update cycle, the write-back buffer writes the entry back to the memory. transfer is in 16-byte units. 4.3.3 prefetch operation prefetch hit: the lru is updated to indicate that the hit way is the most recently hit way. the other contents of the cache are not changed. instructions and data are not transferred from the cache to the cpu. prefetch miss: instructions and data are not transferred from the cache to the cpu. the way that is to be replaced is shown in table 4.2. the other operations are the same as those for a read miss. 4.3.4 write access write hit: in a write access in write-back mode, the data is written to the cache and no external memory write cycle is issued. the u bit of the entry that has been written to is set to 1, and the lru is updated to indicate that the hit way is the most recently hit way. in write-through mode, the data is written to the cache and an external memory write cycle is issued. the u bit of the entry that has been written to is not updated, and the lru is updated to indicate that the hit way is the most recently hit way. write miss: in write-back mode, an external write cycle starts when a write miss occurs, and the entry is updated. the way to be replaced is shown in table 4.3. when the u bit of the entry which is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been transferred to the write-back buffer. data is written to the cache and the u bit and the v bit are set to 1. the lru is updated to indicate that the replaced way is the most recently updated way. after the cache has completed its update cycle, the write-back buffer writes the entry back to the memory. transfer is in 16-byte units. in write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. rev. 1.0, 11/02, page 103 of 690 4.3.5 write-back buffer when the u bit of the entry to be replaced in write-back mode is 1, the entry must be written back to the external memory. to increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. after the fetching of new entries to the cache completes, the write-back buffer writes the entry back to the external memory. during the write-back cycles, the cache can be accessed. the write-back buffer can hold one line of cache data (16 bytes) and its physical address. figure 4.3 shows the configuration of the write-back buffer. longword 0 longword 1 longword 2 longword 3 pa (31 to 4) pa (31 to 4): longword 0 to 3: physical address written to external memory one line of cache data to be written to external memory figure 4.3 write-back buffer configuration 4.3.6 coherency of cache and external memory use software to ensure coherency between the cache and the external memory. when memory shared by this lsi and another device is placed in an address space to which caching applies, use the memory-mapped cache to make the data invalid and written back, as required. memory that is shared by this lsi?s cpu and dmac should also be handled in this way. rev. 1.0, 11/02, page 104 of 690 4.4 memory-mapped cache to allow software management of the cache, cache contents can be read and written by means of mov instructions in privileged mode. the cache is mapped onto the p4 area in virtual address space. the address array is mapped onto addresses h'f0000000 to h'f0ffffff, and the data array onto addresses h'f1000000 to h'f1ffffff. only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 4.4.1 address array the address array is mapped onto h'f0000000 to h'f0ffffff. to access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. the address field specifies information for selecting the entry to be accessed; the data field specifies the tag address, v bit, u bit, and lru bits to be written to the address array. in the address field, specify the entry address for selecting the entry, w for selecting the way, a for enabling or disabling the associative operation, and h'f0 for indicating address array access. as for w, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3). in the data field, specify the tag address, lru bits, u bit, and v bit. figure 4.4 shows the address and data formats in 32-kbyte mode. the following three operations are available in the address array. address-array read: read the tag address, lru bits, u bit, and v bit for the entry that corresponds to the entry address and way specified by the address field of the read instruction. in reading, the associative operation is not performed, regardless of whether the associative bit (a bit) specified in the address is 1 or 0. address-array write (non-associative operation): write the tag address, lru bits, u bit, and v bit, specified by the data field of the write instruction, to the entry that corresponds to the entry address and way as specified by the address field of the write instruction. ensure that the associative bit (a bit) in the address field is set to 0. when writing to a cache line for which the u bit = 1 and the v bit =1, write the contents of the cache line back to memory, then write the tag address, lru bits, u bit, and v bit specified by the data field of the write instruction. always clear the uppermost 3 bits (bits 31 to 29) of the tag address to 0. when 0 is written to the v bit, 0 must also be written to the u bit for that entry. address-array write (associative operation): when writing with the associative bit (a bit) of the address = 1, the addresses in the four ways for the entry specified by the address field of the write instruction are compared with the tag address that is specified by the data field of the write instruction. if the mmu is enabled in this case, a logical address specified by data is translated into a physical address via the tlb before comparison. write the u bit and the v bit specified by the data field of the write instruction to the entry of the way that has a hit. however, the tag rev. 1.0, 11/02, page 105 of 690 address and lru bits remain unchanged. when there is no way that receives a hit, nothing is written and there is no operation. this function is used to invalidate a specific entry in the cache. when the u bit of the entry that has received a hit is 1 at this point, writing back should be performed. however, when 0 is written to the v bit, 0 must also be written to the u bit of that entry. 4.4.2 data array the data array is mapped onto h'f1000000 to h'f1ffffff. to access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. the address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. in the address field, specify the entry address for selecting the entry, l for indicating the longword position within the (16-byte) line, w for selecting the way, and h'f1 for indicating data array access. as for l, 00 indicates longword 0, 01 indicates longword 1, 10 indicates longword 2, and 11 indicates longword 3. as for w, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3). since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be set to 00. figure 4.4 shows the address and data formats in 32-kbyte mode. for other cache size modes, change the entry address and w as shown in table 4.8. the following two operations on the data array are available. the information in the address array is not affected by these operations. data-array read: read the data specified by l of the address filed, from the entry that corresponds to the entry address and the way that is specified by the address filed. data-array write: write the longword data specified by the data filed, to the position specified by l of the address field, in the entry that corresponds to the entry address and the way specified by the address field. rev. 1.0, 11/02, page 106 of 690 (1) address array access (a) address specification read access write access (b) data specification (both read and write accesses) (2) data array access (both read and write accesses) (a) address specification 31 24 23 15 14 13 12 4 3 0 1111 0000 * -------- * w entry address 31 24 23 15 14 13 12 4 3 0 1111 0000 * -------- * w entry address 2 a 31 10 4 3 0 lru 2 xx 9 tag address (31 to 10) uv 1 31 24 23 15 14 13 12 4 3 0 1111 0001 * -------- * w entry address 1 2 l (b) data specification 31 0 longword * : don ? t care bit x: 0 for read, don ? t care for write 0 * 0 0 * 0 0 2 00 figure 4.4 specifying address and data for memory-mapped cache access (32-kbyte mode) table 4.8 address format based on size of cache to be assigned to memory cache size entry address bits w bit 16 kbytes 11 to 4 13 to 12 32 kbytes 12 to 4 14 to 13 rev. 1.0, 11/02, page 107 of 690 4.4.3 usage examples invalidating specific entries: specific cache entries can be invalidated by writing 0 to the entry?s v bit in the memory-mapped cache access. when the a bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and a match is found, the entry is written back if the entry?s u bit is 1 and the v bit and u bit specified by the write data are written. if no match is found, there is no operation. in the example shown below, r0 specifies the write data and r1 specifies the address. ; r0 = h'01100010; vpn = b'0000 0001 0001 0000 0000 00, u = 0, v = 0 ; r1 = h'f0000088; address array access, entry = b'00001000, a = 1 ; mov.l r0,@r1 reading the data of a specific entry: to read the data field of a specific entry is enabled by the memory-mapped cache access. the longword indicated in the data field of the data array in figure 4.4 is read into the register. in the example shown below, r0 specifies the address and r1 shows what is read. ; r0 = h'f100 004c; data array access, entry = b'00000100 ; way = 0, longword address = 3 ; mov.l @r0,r1 ; longword 3 is read. rev. 1.0, 11/02, page 108 of 690 4.5 usage note do note execute the pref instruction for the area that cannot be accessed using the cache (p2 and p4 areas). rev. 1.0, 11/02, page 109 of 690 section 5 exception handling exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. for example, if an attempt is made to execute an undefined instruction code or an instruction protected by the cpu processing mode, a control function may be required to return to the source program by executing the appropriate operation or to report an abnormality and carry out end processing. in addition, a function to control processing requested by lsi on-chip modules or an lsi external module to the cpu may also be required. transferring control to a user-defined exception processing routine and executing the process to support the above functions are called exception handling. this lsi has two types of exceptions: general exceptions and interrupts. the user can execute the required processing by assigning exception handling routines corresponding to the required exception processing and then return to the source program. a reset input can terminate the normal program execution and pass control to the reset vector after register initialization. this reset operation can also be regarded as an exception handling. this section describes an overview of the exception handling operation. here, general exceptions and interrupts are referred to as exception handling. for interrupts, this section describes only the process executed for interrupt requests. for details on how to generate an interrupt request, refer to section 6, interrupt controller (intc). 5.1 register descriptions there are five registers for exception handling. a register with an undefined initial value should be initialized by the software. refer to section 24, list of registers, for the addresses and access sizes of these registers. ? trapa exception register (tra) ? exception event register (expevt) ? interrupt event register (intevt) ? interrupt event register 2 (intevt2) ? exception address register (tea) rev. 1.0, 11/02, page 110 of 690 figure 5.1 shows the bit configuration of each register. 31 tra expevt intevt intevt2 tra expevt intevt intevt2 tea tea 10 9 2 1 0 31 12 11 0 0 0 0 0 0 31 12 11 0 31 12 11 0 31 0 figure 5.1 register bit configuration 5.1.1 trapa exception register (tra) tra is assigned to address h?ffffffd0 and consists of the 8-bit immediate data (imm) of the trapa instruction. tra is automatically specified by the hardware when the trapa instruction is executed. only bits 9 to 2 of the tra can be re-written using the software. bit bit name initial value r/w description 31 to 10 ?? r reserved these bits are always read as 0. the write value should always be 0. 9 to 2 tra ? r/w 8-bit immediate data 1, 0 ?? r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 111 of 690 5.1.2 exception event register (expevt) expevt is assigned to address h?ffffffd4 and consists of a 12-bit exception code. exception codes to be specified in expevt are those for resets and general exceptions. these exception codes are automatically specified the hardware when an exception occurs. only bits 11 to 0 of expevt can be re-written using the software. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 expevt * r/w 12-bit exception code note: initialized to h?000 at power-on reset and h?020 at manual reset. 5.1.3 interrupt event register (intevt) intevt is assigned to address h?ffffffd8 and consists of a 12-bit exception code. exception codes to be specified in intevt are those for interrupt requests. these exception codes are automatically specified by the hardware when an exception occurs. only bits 11 to 0 of intevt can be re-written using the software. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 intevt ? r/w 12-bit exception code rev. 1.0, 11/02, page 112 of 690 5.1.4 interrupt event register 2 (intevt2) intevt2 is assigned to address h?a4000000 and consists of a 12-bit exception code. exception codes to be specified in intevt2 are those for interrupt requests. these exception codes are automatically specified by the hardware when an exception occurs. intevt2 cannot be modified using the software. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 intevt ? r/w 12-bit exception code note: initialized to h?000 at power-on reset and h?020 at manual reset. 5.1.5 exception address register (tea) tea is assigned to address h?fffffffc and stores the logical address for an exception occurrence when an exception related to memory accesses occurs. tea can be modified using the software. bit bit name initial value r/w description 31 to 0 tea ? r/w logical address for exception occurrence note: initialized to h?000 at power-on reset and h?020 at manual reset. rev. 1.0, 11/02, page 113 of 690 5.2 exception handling function 5.2.1 exception handling flow in exception handling, the contents of the program counter (pc) and status register (sr) are saved in the saved program counter (spc) and saved status register (ssr), respectively, and execution of the exception handler is invoked from a vector address. the return from exception handler (rte) instruction is issued by the exception handler routine on completion of the routine, restoring the contents of pc and sr to return to the processor state at the point of interruption and the address where the exception occurred. a basic exception handling sequence consists of the following operations. if an exception occurs and the cpu accepts it, operations 1 to 8 are executed. 1. the contents of pc is saved in spc. 2. the contents of sr is saved in ssr. 3. the block (bl) bit in sr is set to 1, masking any subsequent exceptions. 4. the mode (md) bit in sr is set to 1 to place the privileged mode. 5. the register bank (rb) bit in sr is set to 1. 6. an exception code identifying the exception event is written to bits 11 to 0 of the exception event (expevt) or interrupt event (intevt or intevt2) register. 7. instruction execution jumps to the designated exception vector address to invoke the handler routine. *1 8. if a trapa instruction is executed, an 8-bit immediate data specified by the trapa instruction is set to tra. for an exception related to memory accesses, the logic address where the exception occurred is written to tea. the above operations from 1 to 8 are executed in sequence. during these operations, no other exceptions may be accepted unless multiple exception acceptance is enabled. in an exception handling routine for a general exception, the appropriate exception handling must be executed based on an exception source determined by the expevp. in an interrupt exception handling routine, the appropriate exception handling must be executed based on an exception source determined by the intevt or intevt2. after the exception handling routine has been completed, program execution can be resumed by executing an rte instruction. the rte instruction causes the following operations to be executed. 1. the contents of the ssr are restored into the sr to return to the processing state in effect before the exception handling took place. 2. a delay slot instruction of the rte instruction is executed.*2 3. control is passed to the address stored in the spc. rev. 1.0, 11/02, page 114 of 690 the above operations from 1 to 3 are executed in sequence. during these operations, no other exceptions may be accepted. by changing the spt and ssr before executing the rte instruction, a status different from that in effect before the exception handling can also be specified. notes: 1. the mmu registers are also modified if an mmu exception occurs. 2. for details on the cpu processing mode in which rte delay slot instructions are executed, please refer to section 5.4, usage notes. 5.2.2 exception vector addresses a vector address for general exceptions is determined by adding a vector offset to a vector base address. the vector offset for general exceptions other than the tlb error exception is h?00000100. the vector offset for interrupts is h?00000600. the vector base address is loaded into the vector base register (vbr) using the software. the vector base address should reside in the p1 or p2 fixed physical address space. 5.2.3 exception codes the exception codes are written to bits 11 to 0 of the expevt register (for reset or general exceptions) or the intevt2 register (for interrupt requests) to identify each specific exception event. see section 6, interrupt controller (intc), for details of the exception codes for interrupt requests. table 5.1 lists exception codes for resets and general exceptions. 5.2.4 exception request and bl bit (multiple exception prevention) the bl bit in sr is set to 1 when a reset or exception is accepted. while the bl bit is set to 1, acceptance of general exceptions is restricted as described below, making it possible to effectively prevent multiple exceptions from being accepted. if the bl bit is set to 1, an interrupt request is not accepted and is retained. the interrupt request is accepted when the bl bit is cleared to 0. if the cpu is in low power consumption mode, an interrupt is accepted even if the bl bit is set to 1 and the cpu returns from the low power consumption mode. a dma error is not accepted and is retained if the bl bit is set to 1 and accepted when the bl bit is cleared to 0. user break requests generated while the bl bit is set are ignored and are not retained. accordingly, user breaks are not accepted even if the bl bit is cleared to 0. if a general exception other than a dma address error or user break occurs while the bl bit is set to 1, the cpu enters a state similar to that in effect immediately after a reset, and passes control to the reset vector (h?a0000000) (multiple exception). in this case, unlike a normal reset, modules other than the cpu are not initialized, the contents of expevt, spc, and ssr are undefined, and this status is not detected by an external device. rev. 1.0, 11/02, page 115 of 690 to enable acceptance of multiple exceptions, the contents of spc and ssr must be saved while the bl bit is set to 1 after an exception has been accepted, and then the bl bit must be cleared to 0. before restoring the spc and ssr, the bl bit must be set to 1. 5.2.5 exception source acceptance timing and priority exception request of instruction synchronous type and instruction asynchronous type: resets and interrupts are requested asynchronously regardless of the program flow. in general exceptions, a dma address error and a user break under the specific condition are also requested asynchronously. the user cannot expect on which instruction an exception is requested. for general exceptions other than a dma address error and a user break under a specific condition, each general exception corresponds to a specific instruction. re-execution type and processing-completion type exceptions: all exceptions are classified into two types: a re-execution type and a processing-completion type. if a re-execution type exception is accepted, the current instruction executed when the exception is accepted is terminated and the instruction address is saved to the spc. after returning from the exception processing, program execution resumes from the instruction where the exception was accepted. in a processing-completion type exception, the current instruction executed when the exception is accepted is completed, the next instruction address is saved to the spc, and then the exception processing is executed. during a delayed branch instruction and delay slot, the following operations are executed. a re- execution type exception detected in a delay slot is accepted before executing the delayed branch instruction. a processing-completion type exception detected in a delayed branch instruction or a delay slot is accepted when the delayed branch instruction has been executed. in this case, the acceptance of delayed branch instruction or a delay slot precedes the execution of the branch destination instruction. in the above description, a delay slot indicates an instruction following an unconditional delayed branch instruction or an instruction following a conditional delayed branch instruction whose branch condition is satisfied. if a branch does not occur in a conditional delayed branch, the normal processing is executed. acceptance priority and test priority: acceptance priorities are determined for all exception requests. the priority of resets, general exceptions, and interrupts are determined in this order: a reset is always accepted regardless of the cpu status. interrupts are accepted only when resets or general exceptions are not requested. if multiple general exceptions occur simultaneously in the same instruction, the priority is determined as follows. 1. a processing-completion type exception generated at the previous instruction* 2. a user break before instruction execution (re-execution type) 3. an exception related to an instruction fetch (cpu address error and mmu related exceptions: re-execution type) rev. 1.0, 11/02, page 116 of 690 4. an exception caused by an instruction decode (general illegal instruction exceptions and slot illegal instruction exceptions: re-execution type, unconditional trap: processing-completion type) 5. an exception related to data access (cpu address error and mmu related exceptions: re- execution type) 6. unconditional trap (processing-completion type) 7. a user break other than one before instruction execution (processing-completion type) 8. dma address error (processing-completion type) note:* if a processing-completion type exception is accepted at an instruction, exception processing starts before the next instruction is executed. this exception processing executed before an exception generated at the next instruction is detected. only one exception is accepted at a time. accepting multiple exceptions sequentially results in all exception requests being processed. table 5.1 exception event vectors exception type current instruction exception event priority * 1 exception order process at bl=1 vector code vector offset power-on reset 1 1 reset h'a00 ? reset aborted manual reset 1 2 reset h'020 ? user break(before instruction execution) 2 0 ignored h'1e0 h'00000100 cpu address error (instruction access) 2 1 reset h'0e0 h'00000100 tlb miss * 4 (instruction access) 2 1-1 reset h'040 h'00000400 tlb invalid * 4 (instruction access) 2 1-2 reset h'040 h'00000100 tlb protection violation * 4 (instruction access) 2 1-4 reset h'0a0 h'00000100 illegal general instruction exception 2 2 reset h'180 h'00000100 illegal slot instruction exception 2 2 reset h'1a0 h'00000100 cpu address error (data access) 23 reseth'0e0/ h?100 h'00000100 general exception events re-executed tlb miss * 4 (data access) 2 3-1 reset h'040/ h?060 h'00000400 rev. 1.0, 11/02, page 117 of 690 exception type current instruction exception event priority * 1 exception order process at bl=1 vector code vector offset tlb invalid * 4 (data access) 2 3-2 reset h'040/ h?060 h'00000100 tlb protection violation * 4 (data access) 23-3reseth'0a0/ h?0c0 h'00000100 re-executed initial page write * 4 (data access) 2 3-4 reset h'080 h'00000100 unconditional trap (trapa instruction) 2 4 reset h'160 h'00000100 general exception events completed user breakpoint (after instruction execution, address) 2 5 ignored h'1e0 h'00000100 user breakpoint (data break, i-bus break) 2 5 ignored h'1e0 h'00000100 general interrupt requests completed dma address error 2 6 retained h'5c0 h'00000100 interrupt requests completed interrupt requests 3 ? * 2 retained ? * 3 h'00000600 notes: * 1 priorities are indicated from high to low, 1 being the highest and 3 the lowest. a reset has the highest priority. an interrupt is accepted only when general exceptions are not requested. * 2 for details on priorities in multiple interrupt sources, refer to section 6, interrupt controller (intc). * 3 if an interrupt is accepted, the interrupt source register (expevt) is not changed. the interrupt source code is specified in interrupt source register 2 (expevt2). for details, refer to section 6, interrupt controller (intc). *4 these exception codes are valid when the mmu is used. rev. 1.0, 11/02, page 118 of 690 5.3 individual exception operations this section describes the conditions for specific exception handling and the processor operations for resets and general exceptions. for interrupts, refer to section 6, interrupt controller (intc). 5.3.1 resets power-on reset: ? conditions power-on reset is request ? operations set expevt to h'000, initialize the cpu and on-chip peripheral modules, and branch to the reset vector h?a0000000. for details, refer to the register descriptions in the relevant sections. manual reset: ? conditions manual reset is request ? operations set expevt to h'020, initialize the cpu and on-chip peripheral modules, and branch to the reset vector h?a0000000. for details, refer to the register descriptions in the relevant sections. 5.3.2 general exceptions cpu address error: ? conditions ? instruction is fetched from odd address (4n + 1, 4n + 3) ? word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3) ? longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) ? the area ranging from h'80000000 to h'ffffffff in logical space is accessed in user mode ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) rev. 1.0, 11/02, page 119 of 690 ? exception code an exception occurred during read: h?0e0 an exception occurred during write: h?1e0 ? remarks the logical address (32 bits) that caused the exception is set in tea. illegal general instruction exception: ? conditions ? when undefined code not in a delay slot is decoded delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s note: for details on undefined code, refer to section 2.6.2, operation code map. when an undefined code other than h f000 to h ffff is decoded, operation cannot be guaranteed. ? when a privileged instruction not in a delay slot is decoded in user mode privileged instructions: ldc, stc, rte, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions. ? types instruction synchronous, re-execution type ? save address an instruction address where an exception occurs ? exception code h?180 ? remarks none illegal slot instruction: ? conditions ? when undefined code in a delay slot is decoded delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s ? when a privileged instruction in a delay slot is decoded in user mode privileged instructions: ldc, stc, rte, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions. ? when an instruction that rewrites pc in a delay slot is decoded instructions that rewrite pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa, ldc rm, sr, ldc.l @rm+, sr ? types instruction synchronous, re-execution type rev. 1.0, 11/02, page 120 of 690 ? save address a delayed branch instruction address ? exception code h?1a0 ? remarks none unconditional trap: ? conditions trapa instruction executed ? types instruction synchronous, processing-completion type ? save address an address of an instruction following trapa ? exception code h?160 ? remarks the exception is a processing-completion type, so pc of the instruction after the trapa instruction is saved to spc. the 8-bit immediate value in the trapa instruction is quadrupled and set in tra[9:2]. user break point trap: ? conditions when a break condition set in the user break controller is satisfied ? types break (l bus) before instruction execution: instruction synchronous, re-execution type operand break (l bus): instruction synchronous, processing-completion type data break (l bus): instruction asynchronous, processing-completion type i bus break: instruction asynchronous, processing-completion type ? save address re-execution type: an address of the instruction where a break occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) processing-completion type: an address of the instruction following the instruction where a break occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code h?1e0 rev. 1.0, 11/02, page 121 of 690 ? remarks for details on user break controller, refer to section 22, user break controller (ubc). dma address error: ? conditions ? word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) ? longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) ? types instruction asynchronous, processing-completion type ? save address an address of the instruction following the instruction where a break occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) ? exception code h?5c0 ? remarks an exception occurs when a dma transfer is executed while an illegal instruction address described above is specified in the dmac. since the dma transfer is performed asynchronously with the cpu instruction operation, an exception is also requested asynchronously with the instruction execution. for details on dmac, refer to section 8, direct memory access controller (dmac). 5.3.3 general exceptions (mmu exceptions) when the address translation unit of the memory management unit (mmu) is valid, mmu exceptions are checked after a cpu address error has been checked. four types of mmu exceptions are defined: tlp error exception, tlp invalid exception, tlb protection exception, and initial page write exception. these exceptions are checked in this order. a vector offset for a tlb error exception is defined as h?00000400 to simplify exception source determination. for details on mmu exception operations, refer to section 3, memory management unit (mmu). tlb miss exception: ? conditions comparison of tlb addresses shows no address match. ? types instruction synchronous, re-execution type rev. 1.0, 11/02, page 122 of 690 ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code an exception occurred during read: h?040 an exception occurred during write: h?060 ? remarks the logical address (32 bits) that caused the exception is set in tea and the mmu registers are updated. the vector address of the tlb miss exception is vbr + h'0400. to speed up tlb miss processing, the offset differs from other exceptions. tlb invalid exception: ? conditions comparison of tlb addresses shows address match but v = 0. ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code an exception occurred during read: h?040 an exception occurred during write: h?060 ? remarks the logical address (32 bits) that caused the exception is set in tea and the mmu registers are updated. tlb protection exception: ? conditions when a hit access violates the tlb protection information (pr bits) ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) rev. 1.0, 11/02, page 123 of 690 ? exception code an exception occurred during read: h?0a0 an exception occurred during write: h?0c0 ? remarks the logical address (32 bits) that caused the exception is set in tea and the mmu registers are updated. initial page write exception: ? conditions a hit occurred to the tlb for a store access, but d = 0. ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code h?080 ? remarks the logical address (32 bits) that caused the exception is set in tea and the mmu registers are updated. rev. 1.0, 11/02, page 124 of 690 5.4 usage notes 1. an instruction assigned at a delay slot of the rte instruction is executed after the contents of the ssr is restored into the sr. an acceptance of an exception related to instruction access is determined according to the sr before restore. an acceptance of other exceptions is determined by the sr after restore, processing mode, and bl bit value. a processing- completion type exception is accepted before an instruction at the rte branch destination address is executed. however, note that the correct operation cannot be guaranteed if a re- execution type exception occurs. 2. in an instruction assigned at a delay slot of the rte instruction, a user break cannot be accepted. 3. if the md and bl bits of the sr register are changed by the ldc instruction, an exception is accepted according to the changed sr value from the next instruction.* a processing- completion type exception is accepted before the next instruction is executed. an interrupt and dma address error in re-execution type exceptions are accepted before the next instruction is executed. note:* if an ldc instruction is executed for the sr, the following instructions are re-fetched and an instruction fetch exception is accepted according to the modified sr value. rev. 1.0, 11/02, page 125 of 690 section 6 interrupt controller (intc) the interrupt controller (intc) ascertains the priority of interrupt sources and controls interrupt requests to the cpu. the intc registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 6.1 features ? 16 levels of interrupt priority can be set by setting the interrupt priority registers, the priorities of on-chip peripheral modules, and irq interrupts can be selected from 16 levels for individual request sources. ? nmi noise canceller function an nmi input-level bit indicates the nmi pin state. by reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as a noise canceller. ? irq interrupts can be set detection of low level, high level, rising edge, or falling edge rev. 1.0, 11/02, page 126 of 690 figure 6.1 shows a block diagram of the intc. dmac scif adc usb cmt tmu tpu wdt h-udi ref rtc 6 dmac : direct memory access controller scif : serial communication interface (with fifo) adc : a/d converter usb : usb interface cmt : compare match timer tmu : timer pulse unit tpu : 16-bit timer pulse unit wdt : watchdog timer h-udi : hitachi user debugging interface rtc : realtime clock ref : refresh request in bus state controller icr : interrupt control register ipr : interrupt priority level setting register irr : interrupt request register pinter: pint interrupt enable register sr : status register input/output control priority identifier com- parator interrupt request sr cpu bus interface internal bus intc i3 i2 i1 i0 (interrupt request) icr irr legend: pinter irq5 irq0 16 pint15 pint0 nmi ipr figure 6.1 block diagram of intc rev. 1.0, 11/02, page 127 of 690 6.2 input/output pins table 6.1 shows the intc pin configuration. table 6.1 pin configuration name abbreviation i/o description nonmaskable interrupt input pin nmi input input of interrupt request signal, not maskable by the interrupt mask bits in sr interrupt input pins irq5 to irq0, irl3 to irl0 input input of interrupt request signals port interrupt input pins pint15 to pint0 input input of port interrupt signals note: irl3 to irl0 are multiplexed with irq3 to irq0; they cannot be used together with irq3 to irq0 at the same time. 6.3 register descriptions the intc has the following registers. for details on register addresses and register states during each processing, refer to section 24, list of registers. ? interrupt control register 0 (icr0) ? interrupt control register 1 (icr1) ? interrupt control register 2 (icr2) ? pint interrupt enable register (pinter) ? interrupt priority level setting register a (ipra) ? interrupt priority level setting register b (iprb) ? interrupt priority level setting register c (iprc) ? interrupt priority level setting register d (iprd) ? interrupt priority level setting register e (ipre) ? interrupt priority level setting register f (iprf) ? interrupt priority level setting register g (iprg) ? interrupt priority level setting register h (iprh) ? interrupt request register 0 (irr0) ? interrupt request register 1 (irr1) ? interrupt request register 2 (irr2) rev. 1.0, 11/02, page 128 of 690 6.3.1 interrupt priority level setting registers a to h (ipra to iprh) ipra to iprh are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module, and irq and pint interrupts. bit bit name initial value r/w description 15 to 0 ipr15 to ipr0 all 0 r/w these bits set the priority level for each interrupt source in 4-bit units. for details, see table 6.2, interrupt sources and ipra to iprh. table 6.2 interrupt sources and ipra to iprh register bits 15 to 12 bits 11 to 8 bits 7 to 4 bits 3 to 0 ipra tmu0 tmu1 tmu2 rtc iprb wdt ref reserved * reserved * iprc irq3 irq2 irq1 irq0 iprd pint0 to pint7 pint8 to pint15 irq5 irq4 ipre dmac scif0 scif2 adc iprf reserved * reserved * usb reserved * iprg tpu0 tpu1 reserved * reserved * iprh tpu2 tpu3 reserved * reserved * note: * always read as 0. the write value should always be 0. as shown in table 6.2, on-chip peripheral module, or irq or pint interrupts are assigned to four 4-bit groups in each register. these 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from h'0 (0000) to h'f (1111). setting h'0 means priority level 0 (masking is requested); h'f means priority level 15 (the highest level). rev. 1.0, 11/02, page 129 of 690 6.3.2 interrupt control register 0 (icr0) icr0 is a register that sets the input signal detection mode of external interrupt input pin nmi, and indicates the input signal level at the nmi pin. bit bit name initial value r/w description 15 nmil 0/1 * r nmi input level sets the level of the signal input at the nmi pin. this bit can be read from to determine the nmi pin level. this bit cannot be modified. 0: nmi input level is low 1: nmi input level is high 14 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 nmie 0 r/w nmi edge select selects whether the falling or rising edge of the interrupt request signal at the nmi pin is detected. 0: interrupt request is detected on falling edge of nmi input 1: interrupt request is detected on rising edge of nmi input 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. note: * when nmi input is high, 0 when nmi input is low. rev. 1.0, 11/02, page 130 of 690 6.3.3 interrupt control register 1 (icr1) icr1 is a 16-bit register that specifies the detection mode for external interrupt input pins irq0 to irq5 individually: rising edge, falling edge, high level, or low level. bit bit name initial value r/w description 15 mai 0 r/w mask all interrupts when set to 1, masks all interrupt requests when a low level is being input to the nmi pin. masks nmi interrupts in standby mode. 0: all interrupt requests are not masked when a low level is being input to the nmi pin 1: all interrupt requests are masked when a low level is being input to the nmi pin 14 irqlvl 1 r/w interrupt request level detect selects whether the irq3 to irq0 pins are enabled or disabled to be used as four independent interrupt pins. this bit does not affect the irq4 and irq5 pins. 0: used as four independent interrupt request pins irq3 to irq0 1: used as encoded 15-level interrupt pins as irl3 to irl0 13 blmsk 0 r/w bl bit mask specifies whether nmi interrupts are masked when the bl bit of the sr register is 1. 0: nmi interrupts are masked when the bl bit is 1 1: nmi interrupts are accepted regardless of the bl bit setting 12 ? 0rreserved this bit is always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 131 of 690 bit bit name initial value r/w description irqn sense select select whether the interrupt signals to the irq5 to irq0 pins are detected at the falling edge, at the rising edge, at low level, or at high level. bit 2n+1 bit 2n irqn1s irqn0s 0 0 an interrupt request is detected at irqn input falling edge 0 1 an interrupt request is detected at irqn input rising edge 1 0 an interrupt request is detected at irqn input low level 1 1 an interrupt request is detected at irqn input high level 11 to 0 irq51s to irq00s all 0 r/w [legend] n = 0 to 5 rev. 1.0, 11/02, page 132 of 690 6.3.4 interrupt control register 2 (icr2) icr2 is a 16-bit register that specifies the detection mode for external interrupt input pins pint15 to pint0. bit bit name initial value r/w description 15 to 0 pint15s to pint0s all 0 r/w pint15 to pint0 sense select select whether interrupt request signals to pint15 to pint0 are detected at low levels or high levels. pintns 0: interrupt requests are detected at low level input to the pint pins 1: interrupt requests are detected at high level input to the pint pins [legend] n = 0 to 15 6.3.5 pint interrupt enable register (pinter) pinter is a 16-bit register that enables interrupt requests input to external interrupt input pins pint0 to pint15. when all or some of these pins, pint0 to pint15 are not used as an interrupt input, a bit corresponding to a pin unused as an interrupt request should be cleared to 0. bit bit name initial value r/w description 15 to 0 pint15e to pint0e all 0 r/w pint15 to pint0 interrupt enable select whether the interrupt requests input to the pint15 to pint0 pins is enabled. pintne 0: disables pint input interrupt requests 1: enables pint input interrupt requests [legend] n = 0 to 15 rev. 1.0, 11/02, page 133 of 690 6.3.6 interrupt request register 0 (irr0) irr0 is an 8-bit register that indicates interrupt requests from external input pins irq0 to irq5 and pint0 to pint15. bit bit name initial value r/w description 7 pint0r 0 r pint0 to pint7 interrupt request indicates whether interrupt requests are input to pint0 to pint7 pins. 0: interrupt requests are not input to pint0 to pint7 pins 1: interrupt requests are input to pint0 to pint7 pins 6 pint1r 0 r pint8 to pint15 interrupt request indicates whether interrupt requests are input to pint8 to pint15 pins. 0: interrupt requests are not input to pint8 to pint15 pins 1: interrupt requests are input to pint8 to pint15 pins 5 to 0 irq5r to irq0r all 0 r/w irqn interrupt request indicates whether there is interrupt request input to the irqn pin. when edge-detection mode is set for irqn, an interrupt request is cleared by writing 0 to the irqnr bit after reading irqnr = 1. when level-detection mode is set for irqn, these bits indicate whether an interrupt request is input. the interrupt request is set/cleared by only 1/0 input to the irqn pin. irqnr 0: no interrupt request input to irqn pin 1: interrupt request input to irqn pin [legend] n = 0 to 5 rev. 1.0, 11/02, page 134 of 690 6.3.7 interrupt request register 1 (irr1) irr1 is an 8-bit register that indicates whether dmac or scif0 interrupt requests are generated. bit bit name initial value r/w description 7 txi0r 0 r txi0 interrupt request indicates whether a txi0 (scif0) interrupt request is generated. 0: a txi0 interrupt request is not generated 1: a txi0 interrupt request is generated 6 ? 0rreserved this bit is always read as 0. 5 rxi0r 0 r rxi0 interrupt request indicates whether an rxi0 (scif0) interrupt request is generated. 0: an rxi0 interrupt request is not generated 1: an rxi0 interrupt request is generated 4 eri0r 0 r eri0 interrupt request indicates whether an eri0 (scif0) interrupt request is generated. 0: an eri0 interrupt request is not generated 1: an eri0 interrupt request is generated 3 dei3r 0 r dei3 interrupt request indicates whether a dei3 (dmac) interrupt request is generated. 0: a dei3 interrupt request is not generated 1: a dei3 interrupt request is generated 2 dei2r 0 r dei2 interrupt request indicates whether a dei2 (dmac) interrupt request is generated. 0: a dei2 interrupt request is not generated 1: a dei2 interrupt request is generated 1 dei1r 0 r dei1 interrupt request indicates whether a dei1 (dmac) interrupt request is generated. 0: a dei1 interrupt request is not generated 1: a dei1 interrupt request is generated rev. 1.0, 11/02, page 135 of 690 bit bit name initial value r/w description 0 dei0r 0 r dei0 interrupt request indicates whether a dei0 (dmac) interrupt request is generated. 0: a dei0 interrupt request is not generated 1: a dei0 interrupt request is generated 6.3.8 interrupt request register 2 (irr2) irr2 is an 8-bit register that indicates whether scif2 or adc interrupt requests are generated. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. 4 adir 0 r adi interrupt request indicates whether an adi (adc) interrupt request is generated. 0: an adi interrupt request is not generated 1: an adi interrupt request is generated 3 txi2r 0 r txi2 interrupt request indicates whether a txi2 (scif2) interrupt request is generated. 0: a txi2 interrupt request is not generated 1: a txi2 interrupt request is generated 2 ? 0rreserved this bit is always read as 0. 1 rxi2r 0 r rxi2 interrupt request indicates whether an rxi2 (scif2) interrupt request is generated. 0: an rxi2 interrupt request is not generated 1: an rxi2 interrupt request is generated 0 eri2r 0 r eri2 interrupt request indicates whether an eri2 (scif2) interrupt request is generated. 0: an eri2 interrupt request is not generated 1: an eri2 interrupt request is generated rev. 1.0, 11/02, page 136 of 690 6.4 interrupt sources there are five types of interrupt sources: nmi, irq, irl, pint, and on-chip peripheral modules. each interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. priority level 0 masks an interrupt, so the interrupt request is ignored. 6.4.1 nmi interrupt the nmi interrupt has the highest priority level of 16. when the blmsk bit in the interrupt control register 1 (icr1) is 1 or the bl bit in the status register (sr) is 0, nmi interrupt is accepted. nmi interrupt is edge-detected. in sleep or standby mode, the interrupt is accepted regardless of the bl setting. the nmi edge select bit (nmie) in the interrupt control register 0 (icr0) is used to select either rising or falling edge detection. when using edge-input detection for nmi interrupt, a pulse width of at least two p cycles (peripheral clock) is necessary. nmi interrupt exception handling does not affect the interrupt mask level bits (i3 to i0) in the status register (sr). when the mai bit in icr1 is 1, nmi interrupt is not accepted. it is possible to wake the chip up from sleep mode or standby mode with an nmi interrupt. 6.4.2 irq interrupts irq interrupts are input by level or edge from pins irq0 to irq5. the priority level can be set by interrupt priority registers c and d (iprc and iprd) in a range from 0 to 15. when using edge-sensing for irq interrupts, clear the interrupt source by having software read 1 from the corresponding bit in irr0, then write 0 to the bit. when icr1 is rewritten, irq interrupts may be mistakenly detected, depending on the irq pin states. to prevent this, rewrite the register while interrupts are masked, then release the mask after clearing the illegal interrupt by writing 0 to interrupt request register 0 (irr0). edge input interrupt detection requires input of a pulse width of more than two cycles on a p clock basis. when using level-sensing for irq interrupts, the pin levels must be retained until the cpu samples the pins. therefore, the interrupt source must be cleared by the interrupt handler. the interrupt mask bits (i3 to i0) in the status register (sr) are not affected by irq interrupt handling. irq interrupts can wake the chip up from the standby state when the relevant interrupt level is higher than i3 to i0 in sr (but only when the rtc is used, the clock for the rtc is used to wake the chip up from the standby state). rev. 1.0, 11/02, page 137 of 690 6.4.3 irl interrupts irl interrupts are input by level at pins irl3 to irl0 . the priority level is the higher of those indicated by pins irl3 to irl0 . an irl3 to irl0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). a value of 15 (1111) indicates no interrupt request (interrupt priority level 0). figure 6.2 shows an examples of an irl interrupt connection. table 6.3 shows irl pin and interrupt levels. a noise-cancellation feature is built in, and the irl interrupt is not detected unless the levels sampled at every peripheral clock remain unchanged for two consecutive cycles, so that no transient level on the irl pin change is detected. in standby mode, as the peripheral clock is stopped, noise cancellation is performed using the clock for the rtc instead. therefore when the rtc is not used, recovery from standby mode by means of irl interrupts cannot be performed in standby mode. the priority level of the irl interrupt must not be lowered unless the interrupt is accepted and the interrupt processing starts. however, the priority level can be changed to a higher one. the interrupt mask bits (i3 to i0) in the status register (sr) are not affected by irl interrupt processing. interrupt request priority encoder to 4 this lsi to figure 6.2 example of irl interrupt connection rev. 1.0, 11/02, page 138 of 690 table 6.3 irl3 irl3 irl3 irl3 to irl0 irl0 irl0 irl0 pins and interrupt levels irl3 irl3 irl3 irl3 irl2 irl2 irl2 irl2 irl1 irl1 irl1 irl1 irl0 irl0 irl0 irl0 interrupt priority level interrupt request 0 0 0 0 15 level 15 interrupt request 0 0 0 1 14 level 14 interrupt request 0 0 1 0 13 level 13 interrupt request 0 0 1 1 12 level 12 interrupt request 0 1 0 0 11 level 11 interrupt request 0 1 0 1 10 level 10 interrupt request 0 1 1 0 9 level 9 interrupt request 0 1 1 1 8 level 8 interrupt request 1 0 0 0 7 level 7 interrupt request 1 0 0 1 6 level 6 interrupt request 1 0 1 0 5 level 5 interrupt request 1 0 1 1 4 level 4 interrupt request 1 1 0 0 3 level 3 interrupt request 1 1 0 1 2 level 2 interrupt request 1 1 1 0 1 level 1 interrupt request 1 1 1 1 0 no interrupt request 6.4.4 pint interrupt pint interrupts are input from pins pint0 to pint15 with a level. the priority level can be set by the interrupt priority level setting register d (iprd) in a range from levels 0 to 15, in the unit of pint0 to pint7 or pint8 to pint15. the pint interrupt level should be held until the interrupt is accepted and interrupt handling is started. the interrupt mask bits (i3 to i0) in the status register (sr) are not affected by pint interrupt processing. pint interrupts can wake the chip up from the standby state when the relevant interrupt level is higher than i3 to i0 in sr (but only when the rtc is used, the clock for the rtc is used to wake the chip up from the standby state). 6.4.5 on-chip peripheral module interrupts on-chip peripheral module interrupts are generated by the following 10 modules: ? direct memory access controller (dmac) ? serial communication interfaces (scif0 and scif2) ? a/d converter (adc) ? usb interface (usb) rev. 1.0, 11/02, page 139 of 690 ? timer unit (tmu) ? 16-bit timer pulse unit (tpu) ? watchdog timer (wdt) ? bus state controller (bsc) ? hitachi user-debugging interface (h-udi) ? realtime clock (rtc) not every interrupt source is assigned a different interrupt vector. sources are reflected in the interrupt event registers (intevt and intevt2). it is easy to identify sources by using the value of intevt or intevt2 as a branch offset. a priority level (from 0 to 15) can be set for each module except h-udi by writing to the interrupt priority level setting registers a to h (ipra to iprh). the priority level of the h-udi interrupt is 15 (fixed). the interrupt mask bits (i3 to i0) in the status register are not affected by on-chip peripheral module interrupt handling. 6.4.6 interrupt exception handling and priority there are five types of interrupt sources: nmi, irq, irl, pint, and on-chip peripheral modules. the priority of each interrupt source is set within priority levels 0 to 16; level 16 is the highest and level 1 is the lowest. when the priority is set to level 0, that interrupt is masked and the interrupt request is ignored. tables 6.4 and 6.5 list the codes for the interrupt source and the interrupt event registers (intevt and intevt2) and the order of interrupt priority. each interrupt source is assigned a unique code by intevt and intevt2. the start address of the interrupt service routine is common for each interrupt source. this is why, for instance, the value of intevt2 is used as an offset at the start of the interrupt service routine and branched to in order to identify the interrupt source. irq and pint interrupts, and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each module by setting the interrupt priority level setting registers. a reset assigns priority level 0 to irq, pint, and on-chip peripheral module interrupts. if the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in tables 6.4 and 6.5. rev. 1.0, 11/02, page 140 of 690 table 6.4 interrupt exception handling sources and priority (irq mode) interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 * 2 16 ?? high h-udi h'5e0 * 2 15 ?? irq0 h'600 * 3 0 to 15 (0) iprc (3 to 0) ? irq1 h'620 * 3 0 to 15 (0) iprc (7 to 4) ? irq2 h'640 * 3 0 to 15 (0) iprc (11 to 8) ? irq3 h'660 * 3 0 to 15 (0) iprc (15 to 12) ? irq4 h'680 * 3 0 to 15 (0) iprd (3 to 0) ? irq irq5 h'6a0 * 3 0 to 15 (0) iprd (7 to 4) ? pint0 to pint7 h'700 * 3 0 to 15 (0) iprd (15 to 12) ? pint pint8 to pint15 h'720 * 3 0 to 15 (0) iprd (11 to 8) ? dei0 h'800 * 3 high dei1 h'820 * 3 dei2 h'840 * 3 dmac dei3 h'860 * 3 0 to 15 (0) ipre (15 to 12) low eri0 h'880 * 3 0 to 15 (0) ipre (11 to 8) high rxi0 h'8a0 * 3 scif0 txi0 h'8e0 * 3 low eri2 h'900 * 3 high rxi2 h'920 * 3 scif2 txi2 h'960 * 3 0 to 15 (0) ipre (7 to 4) low adc adi h'980 * 3 0 to 15 (0) ipre (3 to 0) ? usi0 h'a20 * 3 high usb usi1 h'a40 * 3 0 to 15 (0) iprf (7 to 4) low tpu0 tpi0 h'c00 * 3 0 to 15 (0) iprg (15 to 12) ? tpu1 tpi1 h'c20 * 3 0 to 15 (0) iprg (11 to 8) ? tpu2 tpi2 h'c80 * 3 0 to 15 (0) iprh (15 to 12) ? tpu3 tpi3 h'ca0 * 3 0 to 15 (0) iprh (11 to 8) ? low rev. 1.0, 11/02, page 141 of 690 interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority tmu0 tuni0 h'400 * 2 0 to 15 (0) ipra (15 to 12) ? high tmu1 tuni1 h'420 * 2 0 to 15 (0) ipra (11 to 8) ? tuni2 h'440 * 2 high tmu2 ticpi2 h'460 * 2 0 to 15 (0) ipra (8 to 4) low ati h'480 * 2 high pri h'4a0 * 2 rtc cui h'4c0 * 2 0 to 15 (0) ipra (3 to 0) low wdt iti h'560 * 2 0 to 15 (0) iprb (15 to 12) ? ref rcmi h'580 * 2 0 to 15 (0) iprb (11 to 8) ? low notes: 1. the intevt2 code. 2. the same code as intevt2 is set in intevt. 3. the code indicating an interrupt level (h'200 to h'3c0 shown in table 6.6) is set in intevt. rev. 1.0, 11/02, page 142 of 690 table 6.5 interrupt exception handling sources and priority (irl mode) interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 * 2 16 ? ? high h-udi h'5e0 * 2 15 ? ? irl irl (3:0) = 0000 h'200 * 3 15 ? ? irl (3:0) = 0001 h'220 * 3 14 ? ? irl (3:0) = 0010 h'240 * 3 13 ? ? irl (3:0) = 0011 h'260 * 3 12 ? ? irl (3:0) = 0100 h'280 * 3 11 ? ? irl (3:0) = 0101 h'2a0 * 3 10 ? ? irl (3:0) = 0110 h'2c0 * 3 9?? irl (3:0) = 0111 h'2e0 * 3 8?? irl (3:0) = 1000 h'300 * 3 7?? irl (3:0) = 1001 h'320 * 3 6?? irl (3:0) = 1010 h'340 * 3 5?? irl (3:0) = 1011 h'360 * 3 4?? irl (3:0) = 1100 h'380 * 3 3?? irl (3:0) = 1101 h'3a0 * 3 2?? irl (3:0) = 1110 h'3c0 * 3 1?? irq irq4 h'680 * 3 0 to 15 (0) iprd (3 to 0) ? irq5 h'6a0 * 3 0 to 15 (0) iprd (7 to 4) ? pint pint0 to pint 7 h'700 * 3 0 to 15 (0) iprd (15 to 12) ? pint8 to pint 15 h'720 * 3 0 to 15 (0) iprd (11 to 8) ? dmac dei0 h'800 * 3 0 to 15 (0) ipre (15 to 12) high dei1 h'820 * 3 dei2 h'840 * 3 dei3 h'860 * 3 low scif0 eri0 h'880 * 3 0 to 15 (0) ipre (11 to 8) high rxi0 h'8a0 * 3 txi0 h'8e0 * 3 low low rev. 1.0, 11/02, page 143 of 690 interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority scif2 eri2 h'900 * 3 0 to 15 (0) ipre (7 to 4) high high rxi2 h'920 * 3 txi2 h'960 * 3 low adc adi h'980 * 3 0 to 15 (0) ipre (3 to 0) ? usb usi0 h'a20 * 3 0 to 15 (0) iprf (7 to 4) high usi1 h'a40 * 3 low tpu0 tpi0 h'c00 * 3 0 to 15 (0) iprg (15 to 12) ? tpu1 tpi1 h'c20 * 3 0 to 15 (0) iprg (11 to 8) ? tpu2 tpi2 h'c80 * 3 0 to 15 (0) iprh (15 to 12) ? tpu3 tpi3 h'ca0 * 3 0 to 15 (0) iprh (11 to 8) ? tmu0 tuni0 h'400 * 2 0 to 15 (0) ipra (15 to 12) ? tmu1 tuni1 h'420 * 2 0 to 15 (0) ipra (11 to 8) ? tmu2 tuni2 h'440 * 2 0 to 15 (0) ipra (7 to 4) high ticpi2 h'460 * 2 low rtc ati h'480 * 2 0 to 15 (0) ipra (3 to 0) high pri h'4a0 * 2 cui h'4c0 * 2 low wdt iti h'560 * 2 0 to 15 (0) iprb (15 to 12) ? ref rcmi h'580 * 2 0 to 15 (0) iprb (11 to 8) ? low notes: 1. the intevt2 code. 2. the same code as intevt2 is set in intevt. 3. the code indicating an interrupt level (h'200 to h'3c0 shown in table 6.6) is set in intevt. rev. 1.0, 11/02, page 144 of 690 table 6.6 interrupt level and intevt code interrupt level intevt code 15 h'200 14 h'220 13 h'240 12 h'260 11 h'280 10 h'2a0 9h'2c0 8h'2e0 7 h'300 6 h'320 5 h'340 4 h'360 3 h'380 2h'3a0 1h'3c0 6.5 operation 6.5.1 interrupt sequence the sequence of interrupt operations is described below. figure 6.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in the interrupt priority level setting registers a to h (ipra to iprh). lower priority interrupts are held pending. if two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest priority is selected, according to tables 6.4 and 6.5, interrupt exception handling sources and priority. 3. the priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (i3 to i0) in the status register (sr) of the cpu. if the request priority level is higher than the level in bits i3 to i0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. rev. 1.0, 11/02, page 145 of 690 4. detection timing: the intc operates, and notifies the cpu of interrupt requests, in synchronization with the peripheral clock (p ). the cpu receives an interrupt at a break in instructions. 5. the interrupt source code is set in the interrupt event registers (intevt and intevt2). 6. the status register (sr) and program counter (pc) are saved to ssr and spc, respectively. 7. the block bit (bl), mode bit (md), and register bank bit (rb) in sr are set to 1. 8. the cpu jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (vbr) and h'00000600). this jump is not a delayed branch. the interrupt handler may branch with intevt or intevt2 value as its offset in order to identify the interrupt source. this enables it to branch to the handling routine for the individual interrupt source. notes: 1. the interrupt mask bits (i3 to i0) in the status register (sr) are not changed by acceptance of an interrupt in this lsi. 2. the interrupt source flag should be cleared in the interrupt handler. to ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an rte instruction. rev. 1.0, 11/02, page 146 of 690 yes yes yes yes yes yes yes yes yes yes yes yes yes no no no no no no no no no no no no no program execution state interrupt generated? icr1.mai = 1? icr1.blmsk = 1? nmi? nmi = low? sr.bl=0 or sleep mode or software standby mode? nmi? level 15 interrupt? i3-i0 level 14 or lower? level 14 interrupt? i3-i0 level 13 or lower? level 1 interrupt? i3-i0 level 0? set interrupt source in intevt and intevt2 save sr to ssr; save pc to spc set bl/md/rb bits in sr to 1 branch to exception handler i3-i0: interrupt mask bits in status register (sr) figure 6.3 interrupt operation flowchart rev. 1.0, 11/02, page 147 of 690 6.5.2 multiple interrupts when handling multiple interrupts, an interrupt handler should include the following procedures: 1. branch to a specific interrupt handler corresponding to a code set in intevt or intevt2. the code in intevt or intevt2 can be used as an offset for branching to the specific handler. 2. clear the interrupt source in each specific handler. 3. save ssr and spc to memory. 4. clear the bl bit in sr, and set the accepted interrupt level in the interrupt mask bits in sr. 5. handle the interrupt. 6. execute the rte instruction. when these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing bl in step 4. figure 6.3 shows a sample interrupt operation flowchart. 6.6 usage note the interrupt accept timing in this lsi is not acknowledged externally. thus, keep the following note in mind when designing the system. ? level interrupt the level interrupt request should be held until the cpu accepts it. the level interrupt request needs to be cleared (released) within the specific interrupt handler. if the level interrupt request is not held, the operation may branch to the interrupt handling routine when the value in intevt/2 becomes h 000. when the standby state is cancelled, if the level interrupt request is not held, the operation will go back to the standby state again in the middle of wdt counting. when canceling the standby state again in such a condition by asserting the level interrupt request, the settling time for the pll or crystal oscillator is not secured enough and the operation may not recover from the standby state correctly. ? interrupt flag update when an interrupt is acceptable and the generation of an interrupt request is enabled, updating or clearing the interrupt flag may branch the operation to the interrupt handling routine when the value in intevt2 becomes h 000. rev. 1.0, 11/02, page 148 of 690 bscs311a_000020020100 rev. 1.0, 11/02, page 149 of 690 section 7 bus state controller (bsc) 7.1 overview the bus state controller (bsc) outputs control signals for various types of memory that is connected to the external address space and external devices. bsc functions enable this lsi to connect directly with sram, sdram, and other memory storage devices, and external devices. 7.1.1 features the bsc has the following features: ? physical address space is divided into eight areas ? a maximum 32 or 64 mbytes for each of the eight areas, cs0, cs2 to cs4, cs5a, cs5b, cs6a and cs6b, totally 384 mbytes. ? can specify the normal space interface, byte-selection sram interface, burst rom, address/data multiplex i/o (mpx), or sdram for each address space. ? can select the data bus width (8, 16, or 32 bits) for each address space. ? controls the insertion of the wait state for each address space. ? controls the insertion of the wait state for each read access and write access. ? can set the independent idling cycle in the continuous access for five cases: read-write (in same space/different space), read-read (in same space/different space), the first cycle is a write access. ? normal space interface ? supports the interface that can directly connect to the sram. ? burst rom interface ? high-speed access to the rom, such as flash memory, that has the page mode function. ? address/data multiplex i/o (mpx) interface ? can directly connect to a peripheral lsi that needs an address/data multiplexing. ? sdram interface ? can set the sdram up to 2 areas. ? multiplex output for row address/column address. ? efficient access by single read/single write. ? high-speed access by the bank-active mode. ? supports an auto-refresh and self-refresh. rev. 1.0, 11/02, page 150 of 690 ? bus arbitration ? shares all of the resources with other cpu and outputs the bus enable after receiving the bus request from external devices. 7.1.2 block diagram bsc functional block diagram is shown in figure 7.1. output signal drive controller wait between access cycles controller wait controller memory controller refresh controller address/data controller area controller cmncr csnbcr * csnwcr * sdcr rtcsr rtcnt rtcor comparator , , , , , , , , , rd/ , to , , , , , , cke, dqmuu, dqmul, dqmlu, dqmll a25 to 0 d31 to 0 internal address bus internal data bus note * csnbcr, csnwcr : n = 0, 2, 3, 4, 5a, 5b, 6a, 6b legend: csnbcr : area n bus control register csnwcr : area n wait control register sdcr : sdram control register rtcsr : refresh timer control/status register rtcnt : refresh timer counter rtcor : refresh timer constant register bsc figure 7.1 bsc functional block diagram rev. 1.0, 11/02, page 151 of 690 7.2 pin configuration table 7.1 pin configuration name i/o function a25 to a0 o address bus d31 to d0 i/o data bus bs o bus cycle start asserted when a normal space, byte-selection sram, burst rom, or address/data multiplex i/o is accessed. asserted by the same timing as cas in sdram access. cs0 , cs2 to cs4 , cs5a , cs5b , cs6a , cs6b o chip select rd/ wr o read/write connects to we pins when sdram or byte-selection sram is connected. rd o read we3 , dqmuu o indicates that d31 to d24 are being written to when a normal space is set. selects d31 to d24 when a byte-selection sram space is set. selects d31 to d24 when an sdram space is set. we2 , dqmul o indicates that d23 to d16 are being written to when a normal space is set. selects d23 to d16 when a byte-selection sram space is set. selects d23 to d16 when an sdram space is set. we1 , dqmlu o indicates that d15 to d8 are being written to when a normal space and address/data multiplex i/o space are set. selects d15 to d8 when a byte-selection sram space is set. selects d15 to d8 when an sdram space is set. we0 , dqmll o indicates that d7 to d0 are being written to when a normal space and address/data multiplex i/o space are set. selects d7 to d0 when a byte-selection sram space is set. selects d7 to d0 when an sdram space is set. rasu rasl o connects to ras pin when sdram is connected. casu casl o connects to cas pin when sdram is connected. rev. 1.0, 11/02, page 152 of 690 name i/o function cke o connects to cke pin when sdram is connected. ah o holds the address in address/data multiplex i/o mode. wait i external wait input breq i bus request input back o bus acknowledge output md3, md4 i area 0 bus width (8/16/32 bits) md5 i specifies endian 0: big endian 1: little endian 7.3 area overview in the architecture of this lsi, both logical spaces and physical spaces have 32-bit address spaces. the cache access method is shown by the upper 3 bits. for details see section 4, cache. the remaining 29 bits are used for division of the space into eight areas. the bsc performs control for this 29-bit space. as listed in table 7.2, this lsi can be connected directly to eight areas of memory, and it outputs chip select signals ( cs0 , cs2 to cs4 , cs5a , cs5b , cs6a , and cs6b ) for each of them. cs0 is asserted during area 0 access; cs5b is asserted during area 5b access. when an sdram is connected to area 2 or area 3, rasu , rasl , casu , casl , dqmuu, dqmul, dqmlu, and dqmll are asserted. 7.3.1 address map the external address space has a capacity of 384 mbytes and is used by dividing 8 partial spaces. the kind of memory to be connected and the data bus width are specified in each partial space. the address map for the external address space is listed below. table 7.2 physical address space map area memory to be connected physical address capacity access size h 00000000 to h 03ffffff 64 mbytes 8, 16, 32 * 2 area 0 normal memory * 1 , burst rom h 00000000 to h 03ffffff + h 20000000 n + h 20000000 n shadow (n: 1 to 6) rev. 1.0, 11/02, page 153 of 690 area memory to be connected physical address capacity access size h 04000000 to h 07ffffff area 1 internal i/o register * 7 h 04000000 to h 07ffffff + h 20000000 n + h 20000000 n (n:1 to 6) h 08000000 to h 0bffffff 64 mbytes 8, 16, 32 * 3, * 5 area 2 normal memory * 1 , synchronous dram h 08000000 to h 0bffffff + h 20000000 n + h 20000000 n shadow (n:1 to 6) h 0c000000 to h 0fffffff 64 mbytes 8, 16, 32 * 3, * 5 area 3 normal memory * 1 , synchronous dram h 0c000000 to h 0fffffff + h 20000000 n + h 20000000 n shadow (n: 1 to 6) h 10000000 to h 13ffffff 64 mbytes 8, 16, 32 * 3 area 4 normal memory * 1 , burst rom, byte-selection sram h 10000000 to h 13ffffff + h 20000000 n + h 20000000 n shadow (n: 1 to 6) h 14000000 to h 15ffffff 32 mbytes 8, 16, 32 * 3 area 5a normal memory * 1 h 14000000 to h 15ffffff + h 20000000 n + h 20000000 n shadow (n: 1 to 6) h 16000000 to h 17ffffff 32 mbytes 8, 16 * 3, * 4 area 5b normal memory * 1 , address/data multiplex i/o (mpx), byte- selection sram h 16000000 to h 17ffffff + h 20000000 n + h 20000000 n shadow (n: 1 to 6) h 18000000 to h 19ffffff 32 mbytes 8, 16 * 3 area 6a normal memory * 1 h 18000000 to h 19ffffff + h 20000000 n + h 20000000 n shadow (n: 1 to 6) h 1a000000 to h 1bffffff 32 mbytes 8, 16 * 3 area 6b normal memory * 1 h 1a000000 to h 1bffffff + h 20000000 n + h 20000000 n shadow (n: 1 to 6) area 7 * 6 reserved area h 1c000000 to h 1fffffff + h 20000000 n + h 20000000 n (n: 0 to 7) notes: * 1 memory that has an interface such as sram or rom. * 2 memory bus width is specified by an external pin. * 3 memory bus width is specified by a register. * 4 with the address/data multiplex i/o (mpx) interface, the bus width must be 16 bits. * 5 with the sdram, the bus width must be 16 bits or 32 bits. * 6 do not access the reserved area. if the reserved area is accessed, the operation cannot be guaranteed. * 7 when the addresses of the on-chip module control registers (internal i/o registers) in area 1 are not translated by the mmu, set the top three bits of the logical addresses to 101 to allocate in the p2 space. rev. 1.0, 11/02, page 154 of 690 area 0 ( ) h'00000000 h'20000000 h'40000000 h'60000000 h'80000000 h'a0000000 h'c0000000 h'e0000000 internal i/o area 2 ( ) area 3 ( ) area 4 ( ) area 5a ( ) area 6a ( ) h'00000000 h'04000000 h'08000000 h'0c000000 h'10000000 h'14000000 h'18000000 reserved area physical address space logical address space note: for logical address spaces p0 and p3, when the memory management unit (mmu) is on, it can optionally generate a physical address for the logical address. this figure can be applied when mmu is off and when the mmu is on and each physical address for the logical address is equal except for higher three bits. when translating a logical address to a physical address, refer to table 7.2, address space map. p0 p1 p2 p3 p4 area 5b ( ) area 6b ( ) h'16000000 h'1a000000 h'1bffffff figure 7.2 address space 7.3.2 memory bus width the memory bus width in this lsi can be set for each area. in area 0, external pins can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. the correspondence between the external pins (md3, md4) and memory size is listed in the table below. table 7.3 correspondence between external pins (md3 and md4) and memory size md4 md3 memory size 0 setting prohibited. 0 18 bits 0 16 bits 1 1 32 bits for areas other than area 0, byte, word, and longword may be chosen for the bus width using csnbcr that can be set in each area. the bus width that can be set differs according to a connected interface. for more details, see the csn bus control register. rev. 1.0, 11/02, page 155 of 690 when port a or b is used, set the bus width of all areas to 8-bit or 16-bit. for details see section 7.4.2, csn space bus control register (csnbcr). 7.3.3 shadow space areas 0, 2 to 4, 5a, 5b, 6a, and 6b are decoded by physical addresses a28 to a26, which correspond to areas 000 to 110. address bits 31 to 29 are ignored. this means that the range of area 0 addresses, for example, is h'00000000 to h'03ffffff, and its corresponding shadow space is the address space obtained by adding to it h'20000000 n (n = 1 to 6) in areas p1 to p3. the address range for area 7 is h'1c000000 to h'1fffffff. the address space h'1c000000 + h'20000000 n to h'1fffffff + h'20000000 n (n = 0 to 7) corresponding to the area 7 shadow space is reserved, so do not use it. area p4 (h'e0000000 to h'efffffff) is the i/o area where on-chip registers are allocated. this area has no shadow space. 7.4 register descriptions the bsc has the following registers. refer to section 24, list of registers for the details of the addresses of these registers and the state of registers in each operating mode. do not access spaces other than cs0 until the termination of the setting the memory interface. ? common control register (cmncr) ? bus control register for cs0 space (cs0bcr) ? bus control register for cs2 space (cs2bcr) ? bus control register for cs3 space (cs3bcr) ? bus control register for cs4 space (cs4bcr) ? bus control register for cs5a space (cs5abcr) ? bus control register for cs5b space (cs5bbcr) ? bus control register for cs6a space (cs6abcr) ? bus control register for cs6b space (cs6bbcr) ? wait control register for cs0 space (cs0wcr) ? wait control register for cs2 space (cs2wcr) ? wait control register for cs3 space (cs3wcr) ? wait control register for cs4 space (cs4wcr) ? wait control register for cs5a space (cs5awcr) ? wait control register for cs5b space (cs5bwcr) ? wait control register for cs6a space (cs6awcr) rev. 1.0, 11/02, page 156 of 690 ? wait control register for cs6b space (cs6bwcr) ? sdram control register (sdcr) ? refresh timer control/status register (rtcsr)* 1 ? refresh timer counter (rtcnt)* 1 ? refresh time constant register (rtcor)* 1 ? sdram mode register for cs2 space (sdmr2)* 2 ? sdram mode register for cs3 space (sdmr3)* 2 notes: *1 this register only accepts 32-bit writing to prevent incorrect writing. in this case, the upper 16 bits of the data must be h?a55a, otherwise writing cannot be performed. when reading, the upper 16 bits are read as h?0000. *2 the contents of this register are stored in sdram. when this register space is accessed, the corresponding register in sdram is written to. for details, refer to section 7.8.10, power-on sequence. 7.4.1 common control register (cmncr) cmncr is a 32-bit register that controls the common items for each area. do not access external memory other than area 0 until the cmncr register initialization is complete. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 dmaiw1 dmaiw0 0 0 r/w r/w wait states between access cycles when dma single address transfer is performed. specify the number of idle cycles to be inserted after an access to an external device with dack when dma single address transfer is performed. the method of inserting idle cycles depends on the contents of dmaiwa. 00: no idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycled inserted rev. 1.0, 11/02, page 157 of 690 bit bit name initial value r/w description 5 dmaiwa 0 r/w method of inserting wait states between access cycles when dma single address transfer is performed. specifies the method of inserting the idle cycles specified by the dmaiw1 and dmaiw0 bits. clearing this bit will make this lsi insert the idle cycles when another device, which includes this lsi, drives the data bus after an external device with dack drove it. setting this bit will make this lsi insert the idle cycles even when the continuous accesses to an external device with dack are performed. 4 ? 1rreserved this bit is always read as 1. the write value should always be 1. 3 endian 0/1 * r endian flag samples the external pin for specifying endian on power-on reset (md5). all address spaces are defined by this bit. this is a read-only bit. 0: the external pin for specifying endian (md5) was low level on power-on reset. this lsi is being operated as big endian. 1: the external pin for specifying endian (md5) was high level on power-on reset. this lsi is being operated as little endian. 2 ? 0rreserved this bit is always read as 0. the write value should always be 0. 1 hizmem 0 r/w high-z memory control specifies the pin state in software standby mode for a25 to a0, bs , cs , rd/ wr , we , and rd . 0: high impedance in software standby mode. 1: driven in software standby mode 0 hizcnt 0 r/w high-z control specifies the state in software standby mode and bus released for rasu , rasl , casu , and casl . 0: high impedance in software standby mode and bus released for rasu , rasl , casu , and casl . 1: driven in standby mode and bus released for rasu , rasl , casu , and casl . note: * the external pin for specifying endian (md5) is sampled on power-on reset. when big endian is specified, this bit is read as 0 and when little endian is specified, this bit is read as 1. rev. 1.0, 11/02, page 158 of 690 7.4.2 csn space bus control register (csnbcr) (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) csnbcr is a 32-bit readable/writable register that specifies the function of each area, the number of idle cycles between bus cycles, and the bus-width. do not access external memory other than area 0 until csnbcr register initialization is completed. bit bit name initial value r/w description 31, 30 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 29 28 iww1 iww0 1 1 r/w r/w idle cycles between write-read cycles and write-write cycles these bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target access cycles are the write-read cycle and write- write cycle. 00: no idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 27 ? 0rreserved this bit is always read as 0. the write value should always be 0. 26 25 iwrwd1 iwrwd2 1 1 r/w r/w idle cycles for another space read-write specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target access cycle is a read-write one in which continuous accesses switch between different spaces. 00: setting prohibited 01: 2 idle cycles inserted 10: 3 idle cycles inserted 11: 5 idle cycles inserted rev. 1.0, 11/02, page 159 of 690 bit bit name initial value r/w description 24 ? 0rreserved this bit is always read as 0. the write value should always be 0. 23 22 iwrws1 iwrws0 1 1 r/w r/w idle cycles for read-write in the same space specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target cycle is a read-write cycle of which continuous accesses are for the same space. 00: setting prohibited. 01: 2 idle cycles inserted 10: 3 idle cycles inserted 11: 5 idle cycles inserted 21 ? 0rreserved this bit is always read as 0. the write value should always be 0. 20 19 iwrrd1 iwrrd0 1 1 r/w r/w idle cycles for read-read in another space specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target cycle is a read-read cycle of which continuous accesses switch between different space. 00: 1 idle cycle inserted 01: 2 idle cycles inserted 10: 3 idle cycles inserted 11: 5 idle cycles inserted 18 ? 0rreserved this bit is always read as 0. the write value should always be 0. 17 16 iwrrs1 iwrrs0 1 1 r/w r/w idle cycles for read-read in the same space specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target cycle is a read-read cycle of which continuous accesses are for the same space. 00: no idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted rev. 1.0, 11/02, page 160 of 690 bit bit name initial value r/w description 15 ? 0rreserved this bit is always read as 0. the write value should always be 0. 14 13 12 type2 type1 type0 0 0 0 r/w r/w r/w memory type specify the type of memory connected to a space. 000: normal space 001: burst rom 010: address/data multiplex i/o (mpx) 011: byte-selection sram 100: sdram 101: setting prohibited. 110: setting prohibited. 111: setting prohibited. note: sdram can be specified only in area 2 and area 3. burst rom can be specified only in area 0 and area 4. address/data multiplex i/o (mpx) can be specified only in area 5b. byte-selection sram can be specified only in area 4 and area 5b. 11 ? 0rreserved this bit is always read as 0. the write value should always be 0. 10 9 bsz1 bsz0 1 1 r/w r/w data bus size specify the data bus sizes of spaces. the data bus sizes of areas 2, 3, 4 and 5a are shown below. 00: setting prohibited. 01: 8-bit size 10: 16-bit size 11: 32-bit size the data bus sizes of areas 5b, 6a, and 6b are shown below. 00: setting prohibited. 01: 8-bit size 10: 16-bit size 11: setting prohibited rev. 1.0, 11/02, page 161 of 690 bit bit name initial value r/w description 8 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. notes: 1. when the cs5b space is specified as address/data multiplex i/o (mpx), specify the bus size to 16 bits. 2. the data bus size of the cs0 space is specified by an external input pin. the value of bsz[1:0] bits in cs0bcr are invalid. 3. when both the cs2 and cs3 spaces are specified as the sdram space, specify the same bus size for the cs2 and cs3 spaces. 4. when the cs2 or cs3 space is specified as the sdram space, specify the bus width to 16 bits or 32 bits. 5. the initial values of the bus size assignment for areas 5b, 6a, and 6b after power-on reset is specified to prohibited setting. therefore, specify the 8- or 16-bit size before accessing these areas. 6. when port a or b is used, specify the bus size of all areas to 8 bits or 16 bits. when the memory type is specified to an area other than the areas that can be specified, the operation of this lsi is not guaranteed. 7.4.3 csn space wait control register (csnwcr) (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) csnwcr is a 32-bit readable/writable register that specifies various wait cycles for memory accesses. the bit configuration of this register varies as shown below according to the memory type (type 2, type 1, or type 0) specified by the csn space bus control register (csnbcr). specify the csnwcr register before accessing the target area. specify csnbcr register first, then specify the csnwcr register. rev. 1.0, 11/02, page 162 of 690 1. normal space, byte-selection sram, address/data multiplex i/o (mpx) cs0wcr, cs6awcr, cs6bwcr bit bit name initial value r/w description 31 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen assertion specify the number of delay cycles from address and csn assertion to rd and wen assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: setting prohibited. 1110: setting prohibited. 1111: setting prohibited. rev. 1.0, 11/02, page 163 of 690 bit bit name initial value r/w description 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w delay cycles from rd, wen negation to address, csn negation specify the number of delay cycles from rd and wen negation to address and csn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles rev. 1.0, 11/02, page 164 of 690 cs2wcr, cs3wcr bit bit name initial value r/w description 31 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: setting prohibited. 1110: setting prohibited. 1111: setting prohibited. 6 wm 0 r/w external wait mask specification specify whether or not the external wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 165 of 690 cs4wcr, cs5awcr bit bit name initial value r/w description 31 to 19 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 18 17 16 ww2 ww1 ww0 0 0 0 r/w r/w r/w number of write access wait cycles specify the number of cycles that are necessary for write access. 000: the same cycles as wr3 to wr0 setting (read access wait) 001: 0 cycle 010: 1 cycles 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen assertion specify the number of delay cycles from address and csn assertion to rd and wen assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles rev. 1.0, 11/02, page 166 of 690 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specif y the number of c y cles that are necessar y for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: setting prohibited. 1110: setting prohibited. 1111: setting prohibited. 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w delay cycles from rd, wen negation to address, csn negation specify the number of delay cycles from rd and wen negation to address and csn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles rev. 1.0, 11/02, page 167 of 690 cs5bwcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 mpxw 0 r/w mpx interface address wait specifies the wait to be inserted between address cycles for address/data multiplex i/o. this specification is valid only when area 5b is specified to address/data multiplex i/o. 0: no wait 1: 1 cycle wait inserted 19 ? 0rreserved this bit is always read as 0. the write value should always be 0. 18 17 16 ww2 ww1 ww0 0 0 0 r/w r/w r/w number of write access wait cycles specify the number of cycles that are necessary for write access. 000: the same cycles as wr3 to wr0 setting (read access wait) 001: 0 cycle 010: 1 cycles 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen assertion specify the number of delay cycles from address and csn assertion to rd and wen assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles rev. 1.0, 11/02, page 168 of 690 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specif y the number of c y cles that are necessar y for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: setting prohibited. 1110: setting prohibited. 1111: setting prohibited. 6 wm 0 r/w external wait mask specification specify whether or not the external wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w delay cycles from rd, wen negation to address, csn negation specify the number of delay cycles from rd and wen negation to address and csn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles rev. 1.0, 11/02, page 169 of 690 2. burst rom cs0wcr bit bit name initial value r/w description 31 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 16 bw1 bw0 0 0 r/w r/w number of burst wait cycles specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 7 w3 w2 w1 w0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted in the first read/write access cycle. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: setting prohibited. 1110: setting prohibited. 1111: setting prohibited. rev. 1.0, 11/02, page 170 of 690 bit bit name initial value r/w description 6 wm 0 r/w external wait mask specification specify whether or not the external wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. cs4wcr bit bit name initial value r/w description 31 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 16 bw1 bw0 0 0 r/w r/w number of burst wait cycles specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen assertion specify the number of delay cycles from address and csn assertion to rd and wen assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles rev. 1.0, 11/02, page 171 of 690 bit bit name initial value r/w description 10 9 8 7 w3 w2 w1 w0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted in the first read/write access cycle. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: setting prohibited. 1110: setting prohibited. 1111: setting prohibited. 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w delay cycles from rd , wen negation to address, csn negation specify the number of delay cycles from rd and wen negation to address and csn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles rev. 1.0, 11/02, page 172 of 690 3. sdram* cs2wcr bit bit name initial value r/w description 31 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 ? 1rreserved this bit is always read as 1. the write value should always be 1. 9 ? 0rreserved this bit is always read as 0. the write value should always be 0. 8 7 a2cl1 a2cl0 1 0 r/w r/w cas latency for area 2 specify the cas latency for area 2. 00: setting prohibited. 01: 2 cycles 10: 3 cycles 11: setting prohibited. 6 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 173 of 690 cs3wcr bit bit name initial value r/w description 31 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 14 13 trp1 trp0 0 0 r/w r/w number of cycles from auto-precharge/pre command to actv command specify the number of minimum cycles from the start of auto- precharge or issuing of pre command to the issuing of actv command for the same bank. the setting for areas 2 and 3 is common. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 12 ? 0rreserved this bit is always read as 0. the write value should always be 0. 11 10 trcd1 trcd0 0 1 r/w r/w number of cycles from actv command to read(a)/writ(a) command specify the number of minimum cycles from issuing actv command to issuing read(a)/writ(a) command. the setting for areas 2 and 3 is common. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 9 ? 0rreserved this bit is always read as 0. the write value should always be 0. 8 7 a3cl1 a3cl0 1 0 r/w r/w cas latency for area 3 specify the cas latency for area 3. 00: setting prohibited. 01: 2 cycles 10: 3 cycles 11: setting prohibited. rev. 1.0, 11/02, page 174 of 690 bit bit name initial value r/w description 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 trwl1 trwl0 0 0 r/w r/w number of cycles from writa/writ command to auto- precharge/pre command specifies the number of cycles from issuing writa/writ command to the start of auto-precharge or to issuing pre command. the setting for areas 2 and 3 is common. 00: 0 cycle 01: 1 cycle 10: 2 cycles 11: setting prohibited 2 ? 0rreserved this bit is always read as 0. the write value should always be 0. 1 0 trc1 trc0 0 0 r/w r/w number of cycles from ref command/self-refresh release to actv command specify the number of cycles from issuing the ref command or releasing self-refresh to issuing the actv command. the setting for areas 2 and 3 is common. 00: 3 cycles 01: 4 cycles 10: 6 cycles 11: 9 cycles note: * specify area 3 as sdram when only one area is connected with sdram. in this case, specify area 2 as normal space. 7.4.4 sdram control register (sdcr) sdcr specifies the method to refresh and access sdram, and the types of sdrams to be connected. the bits other than rfsh and rmode should be written in the initialization after a power-on reset and should not be modified after the initialization. when modifying these bits rfsh and rmode, do not change the values of other bits and write the previous values. do not access area 2 or 3 until the sdcr register setting is complete when using synchronous dram. rev. 1.0, 11/02, page 175 of 690 bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 19 a2row1 a2row0 0 0 r/w r/w number of bits of row address for area 2 specifies the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits 11: setting prohibited 18 ? 0rreserved this bit is always read as 0. the write value should always be 0. 17 16 a2col1 a2col0 0 0 r/w r/w number of bits of column address for area 2 specifies the number of bits of column address for area 2. 00: 8 bits 01: 9 bits 10: 10 bits 11: setting prohibited 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 slow 0 r/w low-frequency mode specifies the output timing of command, address, and write data for sdram and the latch timing of read data from sdram. setting this bit makes the hold time for command, address, write and read data extended. this mode is suitable for sdram with low-frequency clock. 0: command, address, and write data for sdram is output at the rising edge of ckio. read data from sdram is latched at the rising edge of ckio. 1: command, address, and write data for sdram is output at the falling edge of ckio. read data from sdram is latched at the falling edge of ckio. rev. 1.0, 11/02, page 176 of 690 bit bit name initial value r/w description 11 rfsh 0 r/w refresh control specifies whether or not the refresh operation of the sdram is performed. 0: no refresh 1: refresh 10 rmode 0 r/w refresh control specifies whether to perform auto-refresh or self-refresh when the rfsh bit is 1. when the rfsh bit is 1 and this bit is 1, self-refresh starts immediately. when the rfsh bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in registers rtcsr, rtcnt, and rtcor. 0: auto-refresh is performed 1: self-refresh is performed 9 ? 0rreserved this bit is always read as 0. the write value should always be 0. 8 bactv 0 r/w bank active mode specifies to access whether in auto-precharge mode (using reada and writa commands) or in bank active mode (using read and writ commands). 0: auto-precharge mode (using reada and writa commands) 1: bank active mode (using read and writ commands) note: bank active mode can be used only when either the upper or lower bits of the cs3 space are used. when both the cs2 and cs3 spaces are set to sdram, specify the auto-precharge mode. 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 a3row1 a3row0 0 0 r/w r/w number of bits of row address for area 3 specifies the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: setting prohibited rev. 1.0, 11/02, page 177 of 690 bit bit name initial value r/w description 2 ? 0rreserved this bit is always read as 0. the write value should always be 0. 1 0 a3col1 a3col0 0 0 r/w r/w number of bits of column address for area 3 specifies the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: setting prohibited 7.4.5 refresh timer control/status register (rtcsr) rtcsr specifies various items about refresh for sdram. this register only accepts 32-bit writing to prevent incorrect writing. in this case, the upper 16 bits of the data must be h?a55a, otherwise writing cannot be performed. when reading, the upper 16 bits are read as h?0000. rtcsr bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 cmf 0 r/w compare match flag 0: clearing condition when 0 is written in cmf after reading out rtcsr during cmf = 1. 1: setting condition when the condition rtcnt = rtcor is satisfied. 6 cmie 0 r/w cmf interrupt enable 0: cmf interrupt request is disabled. 1: cmf interrupt request is enabled. rev. 1.0, 11/02, page 178 of 690 bit bit name initial value r/w description 5 4 3 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select select the clock input to count-up the refresh timer counter (rtcnt). 000: stop the counting-up 001: b /4 010: b /16 011: b /64 100: b /256 101: b /1024 110: b /2048 111: b /4096 2 1 0 rrc2 rrc1 rrc0 0 0 0 r/w r/w r/w refresh count specify the number of continuous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (rtcnt) and the refresh time constant register (rtcor). these bits can make the period of occurrence of refresh long. 000: once 001: twice 010: 4 times 011: 6 times 100: 8 times 101: setting prohibited. 110: setting prohibited. 111: setting prohibited. rev. 1.0, 11/02, page 179 of 690 7.4.6 refresh timer counter (rtcnt) rtcnt is an 8-bit counter that counts up using the clock selected by bits cks2 to cks0 in rtcsr. this register only accepts 32-bit writing to prevent incorrect writing. in this case, the upper 16 bits of the data must be h?a55a, otherwise writing cannot be performed. when reading, the upper 16 bits are read as h?0000. when rtcnt matches rtcor, rtcnt is cleared to 0. the value in rtcnt returns to 0 after counting up to 255. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 ? all 0 r/w 8-bit counter 7.4.7 refresh time constant register (rtcor) rtcor is an 8-bit register. when rtcor matches rtcnt, the cmf bit in rtcsr is set to 1 and rtcnt is cleared to 0. this register only accepts 32-bit writing to prevent incorrect writing. in this case, the upper 16 bits of the data must be h?a55a, otherwise writing cannot be performed. when reading, the upper 16 bits are read as h?0000. when the rfsh bit in sdcr is 1, a memory refresh request is issued by this matching signal. this request is maintained until the refresh operation is performed. if the request is not processed when the next matching occurs, the previous request is ignored. when the cmie bit in rtcsr is 1, an interrupt request is issued by this matching signal. this request signal is output until the cmf bit in rtcsr is cleared. clearing the cmf bit only affects the interrupt and does not affect the refresh request. accordingly, the refresh requests and interval timer interrupts can be used together. for example, the number of refresh requests can be counted by using interrupts while the refresh is performed. this register only accepts 32-bit writing to prevent incorrect writing. in this case, the upper 16 bits of the data must be h?a55a, otherwise writing cannot be performed. when reading, the upper 16 bits are read as h?0000. rev. 1.0, 11/02, page 180 of 690 bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 ? all 0 r/w maximum counter value (eight bits) 7.4.8 reset wait counter (rwtcnt) rwtcnt is a 16-bit register. the lower seven bits of this register (bits 6 to 0) are valid as a counter and the upper nine bits (bits 15 to 7) are reserved. this counter starts to count-up by synchronizing the ckio after a power-on reset is released. this counter stops when the value reaches to h 007f. the access to an external bus has to wait when the counter is operating. this counter is provided to minimize the time from releasing a reset for flash memory to the first access. this counter cannot be read or written into. 7.5 endian/access size and data alignment this lsi supports big endian, in which the 0 address is the most significant byte (msbyte) in the byte data and little endian, in which the 0 address is the least significant byte (lsbyte) in the byte data. endian is specified on power-on reset by the external pin (md5). when md5 pin is low level on power-on reset, the endian will become big endian and when md5 pin is high level on power-on reset, the endian will become little endian. three data bus widths are available for normal memory (byte, word, and longword). word and longword are available for sdram. data bus width for address/data multiplex i/o (mpx) should be 16 bits. data alignment is performed in accordance with the data bus width of the device and endian. this also means that when longword data is read from a byte-width device, the read operation must be done four times. in this lsi, data alignment and conversion of data length is performed automatically between the respective interfaces. tables 7.4 to 7.9 show the relationship between endian, device data width, and access unit. rev. 1.0, 11/02, page 181 of 690 table 7.4 32-bit external device/big endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 data 7 to data 0 ??? assert ??? byte access at 1 ? data 7 to data 0 ??? assert ?? byte access at 2 ?? data 7 to data 0 ?? ? assert ? byte access at 3 ??? data 7 to data 0 ??? assert word access at 0 data 15 to data 8 data 7 to data 0 ?? assert assert ?? word access at 2 ?? data 15 to data 8 data 7 to data 0 ?? assert assert longword access at 0 data 31 to data 24 data 23 to data 16 data 15 to data 8 data 7 to data 0 assert assert assert assert rev. 1.0, 11/02, page 182 of 690 table 7.5 16-bit external device/big endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 ?? data 7 to data 0 ?? ? assert ? byte access at 1 ??? data 7 to data 0 ??? assert byte access at 2 ?? data 7 to data 0 ?? ? assert ? byte access at 3 ??? data 7 to data 0 ??? assert word access at 0 ?? data 15 to data 8 data 7 to data 0 ?? assert assert word access at 2 ?? data 15 to data 8 data 7 to data 0 ?? assert assert 1st time at 0 ?? data 31 to data 24 data 23 to data 16 ?? assert assert longword access at 0 2nd time at 2 ?? data 15 to data 8 data 7 to data 0 ?? assert assert rev. 1.0, 11/02, page 183 of 690 table 7.6 8-bit external device/big endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 ?? ? data 7 to data 0 ??? assert byte access at 1 ?? ? data 7 to data 0 ??? assert byte access at 2 ?? ? data 7 to data 0 ??? assert byte access at 3 ?? ? data 7 to data 0 ??? assert word access at 0 1st time at 0 ?? ? data 15 to data 8 ??? assert 2nd time at 1 ?? ? data 7 to data 0 ??? assert word access at 2 1st time at 2 ?? ? data 15 to data 8 ??? assert 2nd time at 3 ?? ? data 7 to data 0 ??? assert longword access at 0 1st time at 0 ?? ? data 31 to data 24 ??? assert 2nd time at 1 ?? ? data 23 to data 16 ??? assert 3rd time at 2 ?? ? data 15 to data 8 ??? assert 4th time at 3 ?? ? data 7 to data 0 ??? assert rev. 1.0, 11/02, page 184 of 690 table 7.7 32-bit external device/little endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 ??? data 7 to data 0 ??? assert byte access at 1 ?? data 7 to data 0 ?? ? assert ? byte access at 2 ? data 7 to data 0 ??? assert ?? byte access at 3 data 7 to data 0 ??? assert ??? word access at 0 ?? data 15 to data 8 data 7 to data 0 ?? assert assert word access at 2 data 15 to data 8 data 7 to data 0 ?? assert assert ?? longword access at 0 data 31 to data 24 data 23 to data 16 data 15 to data 8 data 7 to data 0 assert assert assert assert rev. 1.0, 11/02, page 185 of 690 table 7.8 16-bit external device/little endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 ??? data 7 to data 0 ??? assert byte access at 1 ?? data 7 to data 0 ?? ? assert ? byte access at 2 ??? data 7 to data 0 ??? assert byte access at 3 ?? data7 to data 0 ?? ? assert ? word access at 0 ?? data 15 to data 8 data 7 to data 0 ?? assert assert word access at 2 ?? data 15 to data 8 data 7 to data 0 ?? assert assert 1st time at 0 ?? data 15 to data 8 data 7 to data 0 ?? assert assert longword access at 0 2nd time at 1 ?? data 31 to data 24 data 23 to data 16 ?? assert assert rev. 1.0, 11/02, page 186 of 690 table 7.9 8-bit external device/little endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3 we3 we3 we3 , dqmuu we2 we2 we2 we2 , dqmul we1 we1 we1 we1 , dqmlu we0 we0 we0 we0 , dqmll byte access at 0 ?? ? data 7 to data 0 ??? assert byte access at 1 ?? ? data 7 to data 0 ??? assert byte access at 2 ?? ? data 7 to data 0 ??? assert byte access at 3 ?? ? data 7 to data 0 ??? assert word access at 0 1st time at 0 ?? ? data 7 to data 0 ??? assert 2nd time at 1 ?? ? data 15 to data 8 ??? assert word access at 2 1st time at 2 ?? ? data 7 to data 0 ??? assert 2nd time at 3 ?? ? data 15 to data 8 ??? assert longword access at 0 1st time at 0 ?? ? data 7 to data 0 ??? assert 2nd time at 1 ?? ? data 15 to data 8 ??? assert 3rd time at 2 ?? ? data 23 to data 16 ??? assert 4th time at 3 ?? ? data 31 to data 24 ??? assert rev. 1.0, 11/02, page 187 of 690 7.6 normal space interface 7.6.1 basic timing for access to a normal space, this lsi uses strobe signal output in consideration of the fact that mainly static ram will be directly connected. when using sram with a byte-selection pin, see section 7.10, byte-selection sram interface. figures 7.3 and 7.4 show the basic timings of normal space accesses. a no-wait normal access is completed in two cycles. the bs signal is asserted for one cycle to indicate the start of a bus cycle. there is no access size specification when reading. the correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in case of a 32-bit device, and 16 bits in case of a 16-bit device. when writing, only the wen signal for the byte to be written is asserted. read/write for cache fill or writeback follows the selected bus width and transfers a total of 16 bytes continuously. the bus is not released during this transfer. for cache misses that occur during byte or word operand accesses or branching to odd word boundaries, the fill is always performed by longword accesses on the chip-external interface. write-through-area write access and non- cacheable read/write access are based on the actual address size. it is necessary to output the read out data by using rd when a buffer is established in the data bus. the rd/ wr signal is in a read state (high output) when an access is not performed. therefore, care must be taken about the collision of output in controlling the external data buffer. when the wm bit in csnwcr is cleared to 0, a tnop cycle is inserted to evaluate an external wait. when the wm bit in csnwcr is set to 1, an external wait is ignored and no tnop cycle is inserted. rev. 1.0, 11/02, page 188 of 690 ckio a25 to a0 rd/ data dack t1 t2 t1 t2 data read write figure 7.3 continuous access for normal space (no wait, wm bit in csnwcr = 1, 16-bit bus width, longword access, no wait state between cycles) rev. 1.0, 11/02, page 189 of 690 ckio a25 to a0 data data dackn t1 t2 taw t1 t2 read write figure 7.4 continuous access for normal space (no wait, one wait state between cycles) rev. 1.0, 11/02, page 190 of 690 figures 7.5 to 7.7 show examples of connection to 32-bit, 16-bit, and 8-bit data-width sram, respectively. ? a16 a0 cs oe i/o7 i/o0 we a18 a2 csn rd d31 d24 we3 d23 d16 we2 d15 d8 we1 d7 d0 we0 this lsi 128k 8-bit sram a16 a0 cs oe i/o7 i/o0 we a16 a0 cs oe i/o7 i/o0 we a16 a0 cs oe i/o7 i/o0 we figure 7.5 example of 32-bit data-width sram connection rev. 1.0, 11/02, page 191 of 690 a16 a0 cs oe i/o7 i/o0 we a17 a1 csn rd d15 d8 we1 d7 d0 we0 this lsi 128k 8-bit sram a16 a0 cs oe i/o7 i/o0 we figure 7.6 example of 16-bit data-width sram connection a16 a0 i/o7 i/o0 a16 a0 d7 d0 . . . . . . . . . . . . this lsi 128 k 8 bits sram figure 7.7 example of 8-bit data-width sram connection rev. 1.0, 11/02, page 192 of 690 7.6.2 access wait control wait cycle insertion on a normal space access can be controlled by the settings of bits wr3 to wr0 in csnwcr. it is possible for areas 4, 5a, and 5b to insert wait cycles independently in read access and in write access. the areas other than 4, 5a, and 5b have common access wait for read cycle and write cycle. the specified number of tw cycles is inserted as wait cycles in a normal space access shown in figure 7.8. t1 ckio a25 to a0 rd/ data data tw read write t2 dackn * note: * the waveform for dackn is when active low is specified. figure 7.8 wait timing for normal space access (software wait only) rev. 1.0, 11/02, page 193 of 690 when the wm bit in csnwcr is cleared to 0, the external wait input wait signal is also sampled. wait pin sampling is shown in figure 7.9. a 2-cycle wait is specified as a software wait. the wait signal is sampled on the falling edge of ckio at the transition from the t1 or tw cycle to the t2 cycle. t1 ckio a25 to a0 rd/ data data tw tw twx t2 read write wait states inserted by signal dackn * note: * the waveform for dackn is when active low is specified. figure 7.9 wait state timing for normal space access (wait state insertion by wait wait wait wait signal) rev. 1.0, 11/02, page 194 of 690 7.6.3 csn csn csn csn assert period expansion the number of cycles from csn assertion to rd , wen assertion can be specified by setting bits sw1 and sw0 in csnwcr. the number of cycles from rd , wen negation to csn negation can be specified by setting bits hw1 and hw0. therefore, a flexible interface to an external device can be obtained. figure 7.10 shows an example. a th cycle and a tf cycle are added before and after an ordinary cycle, respectively. in these cycles, rd and wen are not asserted, while other signals are asserted. the data output is prolonged to the tf cycle, and this prolongation is useful for devices with slow writing operations. t1 ckio a25 to a0 rd/ data data th read write t2 dackn * tf note: * the waveform for dackn is when active low is specified. figure 7.10 csn csn csn csn assert period expansion rev. 1.0, 11/02, page 195 of 690 7.7 address/data multiplex i/o interface the address/data multiplex (mpx) i/o interface can be selected by setting bits type2 to type0 to 010 in cs5bbcr. do not set this value to the bits in csnbcr other than those in area 5b, otherwise the operation of the lsi is not guaranteed. access timing for the mpx space is shown below. in the mpx space, cs5b , ah , rd , and wen signals control the accessing. the basic access for the mpx space consists of 2 cycles of address output followed by an access to a normal space. the address output is performed from cycle ta2 to cycle ta3. because cycle ta1 has a high- impedance state, collisions of addresses and data can be avoided without inserting idle cycles, even in continuous accesses. address output is increased to 3 cycles by setting the mpxw bit to 1 in cs5bwcr. the rd/ wr signal is output at the same time as the csn signal; it is high in the read cycle and low in the write cycle. the data cycle is the same as that in a normal space access. timing charts are shown in figures 7.11, 7.12, and 7.13. t1 ckio a25 to a16 rd/ d15 to d0 d15 to d0 read write t2 dackn * ta1 ta2 ta3 address address data data note: * the waveform for dackn is when active low is specified. figure 7.11 access timing for mpx space (address cycle no wait, data cycle no wait) rev. 1.0, 11/02, page 196 of 690 t1 ckio a25 to a16 rd/ d15 to d0 d15 to d0 read write t2 dackn * ta1 ta2 ta3 address address data data tadw note: * the waveform for dackn is when active low is specified. figure 7.12 access timing for mpx space (address cycle wait 1, data cycle no wait) rev. 1.0, 11/02, page 197 of 690 t1 ckio a25 to a16 rd/ d15 to d0 d15 to d0 read write t2 dackn * ta1 ta2 ta3 address address data data tadw tw twx note: * the waveform for dackn is when active low is specified. figure 7.13 access timing for mpx space (address cycle access wait 1, data cycle wait 1, external wait 1) rev. 1.0, 11/02, page 198 of 690 7.8 sdram interface 7.8.1 sdram direct connection since synchronous dram can be selected by the cs signal, physical space areas 2 and 3 can be connected using ras and other control signals in common. if the type[2:0] bits in csnbcr (n = 2 or 3) are set to 100, the synchronous dram interface can be selected. do not set this value to csnbcr unless n = 2 or 3, otherwise the operation of this lsi is not guaranteed. the sdram that can be connected to this lsi is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the a10 pin for setting precharge mode in read and write command cycles. the control signals for direct connection of sdram are rasu , rasl , casu , casl , rd/ wr , dqmuu, dqmul, dqmlu, dqmll, cke, cs2 , and cs3 . all the signals other than cs2 and cs3 are common to all areas, and signals other than cke are valid when cs2 or cs3 is asserted. sdram can be connected to up to 2 spaces. the data bus width of the area that is connected to sdram can be set to 32 or 16 bits. burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as the sdram operating mode. commands for sdram can be specified by rasu , rasl , casu , casl , rd/wr, and specific address signals. these commands are shown below. ? nop ? auto-refresh (ref) ? self-refresh (self) ? all banks pre-charge (pall) ? specified bank pre-charge (pre) ? bank active (actv) ? read (read) ? read with pre-charge (reada) ? write (writ) ? write with pre-charge (writa) ? write mode register (mrs) the byte to be accessed is specified by dqmuu, dqmul, dqmlu, and dqmll. for the relationship between dqmxx and the byte to be accessed, refer to section 7.5, endian/access size and data alignment. figures 7.14 and 7.15 show examples of the connection of sdram with the lsi. rev. 1.0, 11/02, page 199 of 690 this lsi a15 a14 a13 a2 ckio cke rd/ d31 d16 dqmuu dqmul d15 d0 dqmlu dqmll 64m synchronous dram (1m 16-bit 4-bank) a13 a12 a11 a0 clk cke dq15 dq0 dqmu dqml a13 a12 a11 a0 clk cke dq15 dq0 dqmu dqml note: x is u or l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 7.14 example of 64-mbit synchronous dram connection (32-bit data bus) rev. 1.0, 11/02, page 200 of 690 this lsi 64m synchronous dram (1m 16-bit 4-bank) a14 a13 a12 a1 ckio cke rd/ d15 d0 dqmlu dqmll a13 a12 a11 a0 clk cke dq15 dq0 dqmu dqml note: x is u or l . . . . . . . . . . . . . . . . . . . . . . . . figure 7.15 example of 64-mbit synchronous dram (16-bit data bus) 7.8.2 address multiplexing an address multiplexing is specified so that sdram can be connected without external multiplexing circuitry according to the setting of bits bsz[1:0] in csnbcr, axrow[1:0] and axcol[1:0] in sdcr. tables 7.10 to 7.15 show the relationship between the settings of bits bsz[1:0], axrow[1:0], and axcol[1:0] and the bits output at the address pins. do not specify those bits in the manner other than this table, otherwise the operation of this lsi is not guaranteed. a25 to a18 are not multiplexed and the original values of address are always output at these pins. when the data bus width is 16 bits (bsz[1:0] = 10), a0 of sdram specifies a word address. therefore, connect this a0 pin of sdram to the a1 pin of the lsi; the a1 pin of sdram to the a2 pin of the lsi, and so on. when the data bus width is 32 bits (bsz[1:0] = 11), the a0 pin of sdram specifies a longword address. therefore, connect this a0 pin of sdram to the a2 pin of the lsi; the a1 pin of sdram to the a3 pin of the lsi, and so on. rev. 1.0, 11/02, page 201 of 690 table 7.10 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (1)-1 setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 11 (32 bits) 00 (11 bits) 00 (8 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a25 a17 a16 a24 a16 a15 a23 a15 unused a14 a22 * 2 a22 * 2 a12 (ba1) a13 a21 * 2 a21 * 2 a11 (ba0) specifies bank a12 a20 l/h * 1 a10/ap specifies address/precharge a11 a19 a11 a9 a10 a18 a10 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 a9 a1 a0 a8 a0 unused example of connected memory 64-mbit product (512 kwords x 32 bits x 4 banks, column 8 bits product): 1 device 16-mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 2 devices notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification rev. 1.0, 11/02, page 202 of 690 table 7.10 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (1)-2 setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 11 (32 bits) 01 (12 bits) 00 (8 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a25 a17 a16 a24 a16 unused a15 a23 * 2 a23 * 2 a13 (ba1) a14 a22 * 2 a22 * 2 a12 (ba0) specifies bank a13 a21 a13 a11 address a12 a20 l/h * 1 a10/ap specifies address/precharge a11 a19 a11 a9 a10 a18 a10 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 a9 a1 a0 a8 a0 unused example of connected memory 128-mbit product (1 mword x 32 bits x 4 banks, column 8 bits product): 1 device 64-mbit product (1 mword x 16 bits x 4 banks, column 8 bits product): 2 devices notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification rev. 1.0, 11/02, page 203 of 690 table 7.11 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (2)-1 setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 11 (32 bits) 01 (12 bits) 01 (9 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a26 a17 a16 a25 a16 unused a15 a24 * 2 a24 * 2 a13 (ba1) a14 a23 * 2 a23 * 2 a12 (ba0) specifies bank a13 a22 a13 a11 address a12 a21 l/h * 1 a10/ap specifies address/precharge a11 a20 a11 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 a10 a1 a0 a9 a0 unused example of connected memory 256-mbit product (2 mwords x 32 bits x 4 banks, column 9 bits product): 1 device 128-mbit product (2 mwords x 16 bits x 4 banks, column 9 bits product): 2 devices notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification * 3 only the rasl pin is asserted because the a25 pin specified the bank address. rasu is not asserted. rev. 1.0, 11/02, page 204 of 690 table 7.11 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (2)-2 setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 11 (32 bits) 01 (12 bits) 10 (10 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a27 a17 a16 a26 a16 unused a15 a25 * 2 a25 * 2 * 3 a13 (ba1) a14 a24 * 2 a24 * 2 a12 (ba0) specifies bank a13 a23 a13 a11 address a12 a22 l/h * 1 a10/ap specifies address/precharge a11 a21 a11 a9 a10 a20 a10 a8 a9 a19 a9 a7 a8 a18 a8 a6 a7 a17 a7 a5 a6 a16 a6 a4 a5 a15 a5 a3 a4 a14 a4 a2 a3 a13 a3 a1 a2 a12 a2 a0 address a1 a11 a1 a0 a10 a0 unused example of connected memory 512-mbit product (4 mwords x 32 bits x 4 banks, column 10 bits product): 1 device 256-mbit product (4 mwords x 16 bits x 4 banks, column 10 bits product): 2 devices notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification * 3 only the rasl pin is asserted because the a25 pin specified the bank address. rasu is not asserted. rev. 1.0, 11/02, page 205 of 690 table 7.12 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (3) setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 11 (32 bits) 10 (13 bits) 01 (9 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a26 a17 unused a16 a25 * 2 * 3 a25 * 2 * 3 a14 (ba1) a15 a24 * 2 a24 * 2 a13 (ba0) specifies bank a14 a23 a14 a12 a13 a22 a13 a11 address a12 a21 l/h * 1 a10/ap specifies address/precharge a11 a20 a11 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 a10 a1 a0 a9 a0 unused example of connected memory 512-mbit product (4 mwords x 32 bits x 4 banks, column 9 bits product): 1 device 256-mbit product (4 mwords x 16 bits x 4 banks, column 9 bits product): 2 devices notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification * 3 only the rasl pin is asserted because the a25 pin specified the bank address. rasu is not asserted. rev. 1.0, 11/02, page 206 of 690 table 7.13 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (4)-1 setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 10 (16 bits) 00 (11 bits) 00 (8 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a25 a17 a16 a24 a16 a15 a23 a15 a14 a22 a14 unused a13 a21 * 2 a21 * 2 a12 (ba1) a12 a20 * 2 a20 * 2 a11 (ba0) specifies bank a11 a19 l/h * 1 a10/ap specifies address/precharge a10 a18 a10 a9 a9 a17 a9 a8 a8 a16 a8 a7 a7 a15 a7 a6 a6 a14 a6 a5 a5 a13 a5 a4 a4 a12 a4 a3 a3 a11 a3 a2 a2 a10 a2 a1 a1 a9 a1 a0 address a0 a8 a0 unused example of connected memory 16-mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 1 device notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification rev. 1.0, 11/02, page 207 of 690 table 7.13 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (4)-2 setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 10 (16 bits) 01 (12 bits) 00 (8 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a25 a17 a16 a24 a16 a15 a23 a15 unused a14 a22 * 2 a22 * 2 a13 (ba1) a13 a21 * 2 a21 * 2 a12 (ba0) a12 a20 a12 a11 specifies bank address a11 a19 l/h * 1 a10/ap specifies address/precharge a10 a18 a10 a9 a9 a17 a9 a8 a8 a16 a8 a7 a7 a15 a7 a6 a6 a14 a6 a5 a5 a13 a5 a4 a4 a12 a4 a3 a3 a11 a3 a2 a2 a10 a2 a1 a1 a9 a1 a0 address a0 a8 a0 unused example of connected memory 64-mbit product (1 mword x 16 bits x 4 banks, column 8 bits product): 1 device notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification rev. 1.0, 11/02, page 208 of 690 table 7.14 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (5)-1 setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a26 a17 a16 a25 a16 a15 a24 a15 unused a14 a23 * 2 a23 * 2 a13 (ba1) a13 a22 * 2 a22 * 2 a12 (ba0) specifies bank a12 a21 a12 a11 address a11 a20 l/h * 1 a10/ap specifies address/precharge a10 a19 a10 a9 a9 a18 a9 a8 a8 a17 a8 a7 a7 a16 a7 a6 a6 a15 a6 a5 a5 a14 a5 a4 a4 a13 a4 a3 a3 a12 a3 a2 a2 a11 a2 a1 a1 a10 a1 a0 address a0 a9 a0 unused example of connected memory 128-mbit product (2 mwords x 16 bits x 4 banks, column 9 bits product): 1 device notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification rev. 1.0, 11/02, page 209 of 690 table 7.14 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (5)-2 setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 10 (16 bits) 01 (12 bits) 10 (10 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a27 a17 a16 a26 a16 a15 a25 a15 unused a14 a24 * 2 a24 * 2 a13 (ba1) a13 a23 * 2 a23 * 2 a12 (ba0) specifies bank a12 a22 a12 a11 address a11 a21 l/h * 1 a10/ap specifies address/precharge a10 a20 a10 a9 a9 a19 a9 a8 a8 a18 a8 a7 a7 a17 a7 a6 a6 a16 a6 a5 a5 a15 a5 a4 a4 a14 a4 a3 a3 a13 a3 a2 a2 a12 a2 a1 a1 a11 a1 a0 address a0 a10 a0 unused example of connected memory 256-mbit product (4 mwords x 16 bits x 4 banks, column 10 bits product): 1 device notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification rev. 1.0, 11/02, page 210 of 690 table 7.15 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (6)-1 setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a26 a17 a16 a25 a16 unused a15 a24 * 2 a24 * 2 a14 (ba1) a14 a23 * 2 a23 * 2 a13 (ba0) specifies bank a13 a22 a13 a12 a12 a21 a12 a11 address a11 a20 l/h * 1 a10/ap specifies address/precharge a10 a19 a10 a9 a9 a18 a9 a8 a8 a17 a8 a7 a7 a16 a7 a6 a6 a15 a6 a5 a5 a14 a5 a4 a4 a13 a4 a3 a3 a12 a3 a2 a2 a11 a2 a1 a1 a10 a1 address a0 a9 a0 a0 unused example of connected memory 256-mbit product (4 mwords x 16 bits x 4 banks, column 9 bits product): 1 device notes: * 1 l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2 bank address specification * 3 only the rasl pin is asserted because the a25 pin specified the bank address. rasu is not asserted. rev. 1.0, 11/02, page 211 of 690 table 7.15 relationship between a2/3bsz[1:0], a2/3row[1:0], and address multiplex output (6)-2 setting a2/3 bsz[1:0] a2/3 row[1:0] a2/3 col[1:0] 10 (16 bits) 10 (13 bits) 10 (10 bits) output pin of this lsi row address output cycle column address output cycle synchronous dram pin function a17 a27 a17 a16 a26 a16 unused a15 a25 * 2 * 3 a25 * 2 * 3 a14 (ba1) a14 a24 * 2 a24 * 2 a13 (ba0) specifies bank a13 a23 a13 a12 a12 a22 a12 a11 address a11 a21 l/h * 1 a10/ap specifies address/precharge a10 a20 a10 a9 a9 a19 a9 a8 a8 a18 a8 a7 a7 a17 a7 a6 a6 a16 a6 a5 a5 a15 a5 a4 a4 a14 a4 a3 a3 a13 a3 a2 a2 a12 a2 a1 a1 a11 a1 a0 address a0 a10 a0 unused example of connected memory 512-mbit product (8 mwords x 16 bits x 4 banks, column 10 bits product): 1 device notes: * 1. l/h is a bit used in the command specification; it is fixed at l or h according to the access mode. * 2. bank address specification * 3. only the rasl pin is asserted because the a25 pin specified the bank address. rasu is not asserted. rev. 1.0, 11/02, page 212 of 690 7.8.3 burst read a burst read occurs in the following cases in this lsi. ? 16-byte transfer in cache miss. ? 16-byte transfer in dmac (access to non-cacheable region) ? access size in reading is larger than data bus width. this lsi always accesses the sdram with burst length 1. for example, read access of burst length 1 is performed consecutively 4 times to read 16-byte continuous data from the sdram that is connected to a 32-bit data bus. table 7.16 shows the relationship between the access size and the number of bursts. table 7.16 relationship between access size and number of bursts bus width access size number of bursts 8 bits 1 16 bits 1 32 bits 2 16 bits 16 bits 8 8 bits 1 16 bits 1 32 bits 1 32 bits 16 bits 4 rev. 1.0, 11/02, page 213 of 690 figure 7.16 shows a timing chart in burst read. in burst read, an actv command is output in the tr cycle, the read command is issued in the tc1, tc2, and tc3 cycles, the reada command is issued in the tc4 cycle, and the read data is received at the rising edge of the external clock (ckio) in the td1 to td4 cycles. the tap cycle is used to wait for the completion of an auto- precharge induced by the read command in the sdram. in the tap cycle, a new command will not be issued to the same bank. however, access to another cs space or another bank in the same sdram space is enabled. the number of tap cycles is specified by the trp[1:0] bits of the cs3wcr register. tc4 ckio a25 to a0 rd/ / dqmxx * 2 d31 to d0 tap dackn * 3 tr tc2 tc3 tc1 td4 tde td2 td3 td1 a12/a11 * 1 / notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. trw tw figure 7.16 synchronous dram burst read wait specification timing (auto pre-charge) rev. 1.0, 11/02, page 214 of 690 7.8.4 single read a read access ends in one cycle when data exists in non-cacheable region and the data bus width is larger than or equal to access size. as the burst length is set to 1 in synchronous dram burst read/single write mode, only the required data is output. consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. figure 7.17 shows the basic timing chart for single read. ckio a25 to a0 rd/ dqmxx * 2 d31 to d0 tap dackn * 3 tr tc1 tde td1 tw a12/a11 * 1 notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll * 3 the waveform for dackn is when active low is specified. figure 7.17 basic timing for single read (auto pre-charge) rev. 1.0, 11/02, page 215 of 690 7.8.5 burst write a burst write occurs in the following cases in this lsi. ? copyback of the cache ? 16-byte transfer in dmac (access to non-cacheable region) ? access size in writing is larger than data bus width. this lsi always accesses sdram with burst length 1. for example, write access of burst length 1 is performed continuously 4 times to write 16-byte continuous data to the sdram that is connected to a 32-bit data bus. the relationship between the access size and the number of bursts is shown in table 7.16. rev. 1.0, 11/02, page 216 of 690 figure 7.18 shows a timing chart for burst writes. in burst write, an actv command is output in the tr cycle, the writ command is issued in the tc1, tc2, and tc3 cycles, and the writa command is issued to execute an auto-precharge in the tc4 cycle. in the write cycle, the write data is output simultaneously with the write command. after the write command with the auto- precharge is output, the trw1 cycle that waits for the auto-precharge initiation is followed by the tap cycle that waits for completion of the auto-precharge induced by the writa command in the sdram. in the tap cycle, a new command will not be issued to the same bank. however, access to another cs space or another bank in the same sdram space is enabled. the number of trw1 cycles is specified by the trwl[1:0] bits of the cs3wcr register. the number of tap cycles is specified by the trp[1:0] bits of the cs3wcr register. tc4 ckio a25 to a0 rd/ / dqmxx * 2 d31 to d0 tap dackn * 3 tr tc2 tc3 tc1 trwl a12/a11 * 1 / notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.18 basic timing for synchronous dram burst write (auto pre-charge) rev. 1.0, 11/02, page 217 of 690 7.8.6 single write a write access ends in one cycle when data is written in non-cacheable region and the data bus width is larger than or equal to access size. this is called single write. figure 7.19 shows the basic timing chart for single write. ckio a25 to a0 rd/ dqmxx * 2 d31 to d0 tap dackn * 3 tr tc1 trwl a12/a11 * 1 notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.19 basic timing for single write (auto pre-charge) rev. 1.0, 11/02, page 218 of 690 7.8.7 bank active the synchronous dram bank function is used to support high-speed accesses to the same row address. when the bactv bit in sdcr is 1, accesses are performed using commands (read, writ) without auto-precharge. this function is called bank-active function. this function is valid only for either the upper or lower bits of area 3. when area 3 is set to bank-active mode, area 2 should be set to normal space or byte-selection sram. when areas 2 and 3 are both set to sdram or both the upper and lower bits of area 3 are connected to sdram, auto pre-charge mode must be set. in this case, precharging is not performed when the access ends. when accessing the same row address in the same bank, it is possible to issue the read or writ command immediately, without issuing an actv command. as synchronous dram is internally divided into several banks, it is possible to activate one row address in each bank. if the next access is to a different row address, a pre command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an actv command followed by a read or writ command. if this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. in a write, when auto-precharge is performed, a command cannot be issued for a period of trwl + tpc cycles after issuance of the writa command. when bank active mode is used, read or writ commands can be issued successively if the row address is the same. the number of cycles can thus be reduced by trwl + tpc cycles for each write. there is a limit on t ras , the time for placing each bank in the active state. if there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of t ras . a burst read cycle without auto-precharge is shown in figure 7.20, a burst read cycle for the same row address in figure 7.21, and a burst read cycle for different row addresses in figure 7.22. similarly, a burst write cycle without auto-precharge is shown in figure 7.23, a single write cycle for the same row address in figure 7.24, and a single write cycle for different row addresses in figure 7.25. when bank active mode is set, if only accesses to the respective banks in the area 3 space are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 7.20 or 7.23, followed by repetition of the cycle in figure 7.21 or 7.24. an access to a different area during this time has no effect. if there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 7.22 or 7.25 is executed instead of that in figure 7.21 or 7.24. in bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. rev. 1.0, 11/02, page 219 of 690 tc4 ckio a25 to a0 rd/ / dqmxx * 2 d31 to d0 dackn * 3 tr tc2 tc3 tc1 td4 td2 td3 td1 tw tde a12/a11 * 1 / notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.20 burst read timing (no auto precharge) rev. 1.0, 11/02, page 220 of 690 tc4 tc2 tc3 tc1 td4 tde td2 td3 td1 tw ckio a25 to a0 rd/ / dqmxx * 2 d31 to d0 dackn * 3 a12/a11 * 1 / notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.21 burst read timing (bank active, same row address) rev. 1.0, 11/02, page 221 of 690 tc4 tpw tp tc2 tc3 tc1 td4 td2 td3 td1 tw tde tr ckio a25 to a0 rd/ / dqmxx * 2 d31 to d0 dackn * 3 a12/a11 * 1 / notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.22 burst read timing (bank active, different row addresses) rev. 1.0, 11/02, page 222 of 690 tr tc1 ckio a25 to a0 rd/ / dqmxx * 2 d31 to d0 dackn * 3 a12/a11 * 1 / notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.23 single write timing (no auto precharge) rev. 1.0, 11/02, page 223 of 690 tnop tc1 ckio a25 to a0 rd/ / dqmxx * 2 d31 to d0 dackn * 3 a12/a11 * 1 / notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.24 single write timing (bank active, same row address) rev. 1.0, 11/02, page 224 of 690 tpw tp tc1 tr ckio a25 to a0 rd/ / dqmxx * 2 d31 to d0 dackn * 3 a12/a11 * 1 / notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.25 single write timing (bank active, different row addresses) rev. 1.0, 11/02, page 225 of 690 7.8.8 refreshing this lsi has a function for controlling synchronous dram refreshing. auto-refreshing can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in sdcr. a continuous refreshing can be performed by setting the rrc[2:0] bits in rtcsr. if synchronous dram is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the rmode bit and the rfsh bit to 1. 1. auto-refreshing refreshing is performed for the number of times specified by bits rrc[2:0] in rtcsr at intervals determined by the input clock selected by bits cks[2:0] in rtcsr, and the value set in rtcor. the value of these bits should be set so as to satisfy the refresh interval stipulation for the synchronous dram used. first make the settings for rtcor, rtcnt, and the rmode and rfsh bits in sdcr, then make bits cks[2:0] and rrc[2:0] settings in rtcsr. when the clock is selected by bits cks[2:0], rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refresh request is generated and auto-refresh is performed for the number of times specified by bits rrc[2:0]. at the same time, rtcnt is cleared to zero and the count- up is restarted. figure 7.26 shows the auto-refresh cycle timing. after starting, the auto refreshing, pall command is issued in the tp cycle to make all the banks to pre-charged state from active state when some bank is being pre-charged. then ref command is issued in the trr cycle after inserting idle cycles of which number is specified by the trp[1:0] bits in csnwcr. a new command is not issued for the duration of the number of cycles specified by the trc[1:0] bits in csnwcr after the trr cycle. the trc[1:0] bits must be set so as to satisfy the sdram refreshing cycle time stipulation (t rc ). a nop cycle is inserted between the tp cycle and trr cycle when the setting value of the trp[1:0] bits in csnwcr is longer than or equal to 2 cycles. rev. 1.0, 11/02, page 226 of 690 tpw tp trr trc trc trc hi-z ckio a25 to a0 rd/ / dqmxx * 2 d31 to d0 dackn * 3 a12/a11 * 1 / notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.26 auto-refresh timing 2. self-refreshing self-refresh mode in which the refresh timing and refresh addresses are generated within the synchronous dram. self-refreshing is activated by setting both the rmode bit and the rfsh bit in sdcr to 1. after starting the self-refreshing, pall command is issued in tp cycle after the completion of the pre-charging bank. a self command is then issued after inserting idle cycles of which number is specified by the trp[1:0] bits in csnwsr. synchronous dram cannot be accessed while in the self-refresh state. self-refresh mode is cleared by clearing the rmode bit to 0. after self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the trc[1:0] bits in csnwcr. self- refresh timing is shown in figure 7.27. settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. when self-refreshing is activated from the state in which auto-refreshing is set, auto- refreshing is restarted if the rfsh bit is set to 1 and the rmode bit is cleared to 0 when self- refresh mode is cleared. if the transition from clearing of self-refresh mode to the start of auto- refreshing takes time, this time should be taken into consideration when setting the initial value of rtcnt. making the rtcnt value 1 less than the rtcor value will enable refreshing to be started immediately. rev. 1.0, 11/02, page 227 of 690 after self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the lsi standby function, and is maintained even after recovery from standby mode other than through a power-on reset. in case of a power-on reset, the bus state controller?s registers are initialized, and therefore the self-refresh state is cleared. tpw tp trr trc trc trc hi-z trc trc ckio cke a25 to a0 rd/ / dqmxx * 2 d31 to d0 dackn * 3 a12/a11 * 1 / notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.27 self-refresh timing 3. relationship between refresh requests and bus cycle if a refresh request is generated during a bus cycle, refresh waits for the bus cycle to be completed. if a refresh request is generated while the bus is released by the bus arbitration function, refresh waits for the bus mastership to be obtained. if a new refresh request is generated while refresh is waiting, the first refresh request is canceled. to perform refresh correctly, the bus cycle and the bus-owned period must be shorter than the refresh interval. if a bus request is issued during self-refreshing, the bus is not released until the refresh is completed. rev. 1.0, 11/02, page 228 of 690 7.8.9 low-frequency mode when the slow bit in sdcr is set to 1, output of commands, addresses, and write data, and fetch of read data are performed at a timing suitable for operating sdram at a low frequency. figure 7.28 shows the access timing in low-frequency mode. in this mode, commands, addresses, and write data are output in synchronization with the falling edge of ckio, which is half a cycle delayed than the normal timing. read data is fetched at the rising edge of ckio, which is half a cycle faster than the normal timing. this timing allows the hold time of commands, addresses, write data, and read data to be extended. if sdram is operated at a high frequency with the slow bit set to 1, the setup time of commands, addresses, write data, and read data are not guaranteed. take the operating frequency and timing design into consideration when making the slow bit setting. ckio a25 to a0 rd/ d31 to d0 tc1 dackn * 3 tr td1 tw a12/a11 * 1 tde tap tr tc1 tnop trwl tap cke dqmxx * 2 notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. figure 7.28 low-frequency mode access timing rev. 1.0, 11/02, page 229 of 690 7.8.10 power-on sequence in order to use synchronous dram, mode setting must first be performed after powering on. to perform synchronous dram initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous dram mode register. in synchronous dram mode register setting, the address signal value at that time is latched by a combination of the csn , ras , cas , and rd/ wr signals. if the value to be set is x, the bus state controller provides for value x to be written to the synchronous dram mode register by performing a write to address h'a4fd4000 + x for area 2 synchronous dram, and to address h'a4fd5000 + x for area 3 synchronous dram. in this operation the data is ignored, but the mode write is performed as a byte-size access. to set burst read/single write, cas latency 2 to 3, wrap type = sequential, and burst length 1 supported by the lsi, arbitrary data is written in a byte-size access to the addresses shown in table 7.17. in this time 0 is output at the external address pins of a12 or later. table 7.17 access address in sdram mode register write (1) setting for area 2 (sdmr2) burst read/single write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h a4fd4440 h 0000440 3h a4fd4460 h 0000460 32 bits 2 h a4fd4880 h 0000880 3h a4fd48c0 h 00008c0 burst read/burst write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h a4fd4040 h 0000040 3h a4fd4060 h 0000060 32 bits 2 h a4fd4080 h 0000080 3h a4fd40c0 h 00000c0 rev. 1.0, 11/02, page 230 of 690 (2) setting for area 3 (sdmr3) burst read/single write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h a4fd5440 h 0000440 3h a4fd5460 h 0000460 32 bits 2 h a4fd5880 h 0000880 3h a4fd58c0 h 00008c0 burst read/burst write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h a4fd5040 h 0000040 3h a4fd5060 h 0000060 32 bits 2 h a4fd5080 h 0000080 3h a4fd50c0 h 00000c0 mode register setting timing is shown in figure 7.29. a pall command (all bank pre-charge command) is firstly issued. a ref command (auto refresh command) is then issued 8 times. an mrs command (mode register write command) is finally issued. idle cycles, of which number is specified by the trp[1:0] bits in csnwcr, are inserted between the pall and the first ref. idle cycles, of which number is specified by the trc[1:0] bits in csnwcr, are inserted between ref and ref, and between the 8th ref and mrs. idle cycles, of which number is one or more, are inserted between the mrs and a command to be issued next. it is necessary to keep idle time of certain cycles for sdram before issuing pall command after power-on. refer the manual of the sdram for the idle time to be needed. when the pulse width of the reset signal is longer then the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time. rev. 1.0, 11/02, page 231 of 690 tpw tp trr trc trc tmw hi-z tnop trc trr trc ref ref mrs pall notes: * 1 address pin to be connected to the a10 pin of sdram. * 2 xx is uu, ul, lu, or ll. * 3 the waveform for dackn is when active low is specified. ckio a25 to a0 rd/ dqmxx * 2 d31 to d0 dackn * 3 a12/a11 * 1 figure 7.29 synchronous dram mode write timing (based on jedec) 7.9 burst rom interface the burst rom interface is provided to access rom that has the page mode function, such as flash memory, in high speed. basically the access to the rom is performed in the same way as for normal space. when the first cycle is terminated, however, negation of the rd signal is not executed. the accesses after the 2nd access are performed by exchanging only the address. in the accesses after the 2nd access, the address is changed at the falling edge of ckio. the number of wait cycles specified by the w[3:0] bits in csnwcr are inserted for the first access cycle. the number of wait cycles specified by the bw[1:0] bits in csnwcr are inserted for the second and subsequent access cycles. in the access to the burst rom, the bs signal is asserted only to the first access cycle. an external wait input is valid only to the first access cycle. in the single access or write access that do not perform the burst operation in the burst rom interface, access timing is same as a normal space. table 7.18 lists a relationship between bus width, access size, and the number of bursts. figure 7.30 shows a timing chart. rev. 1.0, 11/02, page 232 of 690 table 7.18 relationship between bus width, access size, and number of bursts bus width access size number of bursts 8 bits 8 bits 1 16 bits 2 32 bits 4 16 bytes 16 16 bits 8 bits 1 16 bits 1 32 bits 2 16 bytes 8 ckio address data dack t1 tw tw tb2 twb tb2 twb tb2 twb t2 rd/ figure 7.30 burst rom access (bus width 8 bits, access size 32 bits (number of burst 4), access wait for the 1st time 2, access wait for 2nd time and after 1) rev. 1.0, 11/02, page 233 of 690 7.10 byte-selection sram interface the byte-selection sram interface is for outputting the byte-selection signal ( wen ) in both read and write bus cycles. this interface has 16-bit data pins and accesses sram that has an upper byte-selection pin and a lower byte-selection pin, such as ub and lb. the write access timing is the same as that for the normal space interface. the read access timing differs from that for the normal space interface in the wen timing, and a byte-selection signal is output from the wen pin. the basic access timing is shown in figure 7.31. note that in a write cycle, data is written in accordance with the byte-selection pin ( wen ) timing. check the data sheet of the memory to be used for the actual timing. ckio a25 to a0 rd/ d31 to d0 d31 to d0 rd/ dackn * t1 t2 high write read note: * the waveform for dackn is when active low is specified. figure 7.31 byte-selection sram basic access timing rev. 1.0, 11/02, page 234 of 690 a15 a0 i/o15 i/o0 a17 a2 rd/ d31 d16 d15 d0 a15 a0 i/o15 i/o0 this lsi 64 k 16 bits sram . . . . . . . . . . . . . . . . . . . . . figure 7.32 example of connection with 32-bit data-width byte-selection sram this lsi a16 a1 rd/ d15 d0 a15 a0 i/o 15 i/o 0 64kx16bit sram figure 7.33 example of connection with 16-bit data-width byte-selection sram rev. 1.0, 11/02, page 235 of 690 7.11 wait between access cycles as the operating frequency of lsis becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. as a result of these collisions, the reliability of the device is low and malfunctions may occur. a function that avoids data collisions by inserting wait cycles between continuous access cycles has been newly added. the number of wait cycles between access cycles can be set by bits iww[1:0], iwrwd[1:0], iwrws[1:0], iwrrd[1:0], and iwrrs[1:0] in csnbcr, and bits dmaiw[1:0] and dmaiwa in cmncr. the conditions for setting the wait cycles between access cycles (idle cycles) are shown below. 1. continuous accesses are write-read or write-write 2. continuous accesses are read-write for different spaces 3. continuous accesses are read-write for the same space 4. continuous accesses are read-read for different spaces 5. continuous accesses are read-read for the same space 6. data output from an external device caused by dma single transfer is followed by data output from another device that includes this lsi (dmaiwa = 0) 7. data output from an external device caused by dma single transfer is followed by any type of access (dmaiwa = 1) 7.12 bus arbitration this lsi supports bus arbitration. this lsi has bus mastership in the normal state and releases bus mastership after receiving a bus request from another device. to prevent device malfunction while the bus mastership is transferred between master and slave, the lsi negates all of the bus control signals before bus release. when the bus mastership is received, all of the bus control signals are first negated and then driven appropriately. in this case, output buffer conflicts can be prevented because the master and slave drive the same signals with the same values. in addition, to prevent noise while the bus control signal is in the high-impedance state, pull-up resistors must be connected to these control signals. bus mastership is transferred at the boundary of bus cycles. namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. the release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. even when from outside the lsi it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between access cycles. therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the csn signal or other bus control signals. the states that do not allow bus mastership release are shown below. rev. 1.0, 11/02, page 236 of 690 1. 16-byte transition because of a cache miss 2. during copyback operation for the cache 3. between the read and write cycles of a tas instruction 4. multiple bus cycles generated when data bus width is smaller than the access size (for example, between bus cycles when longword access is made to memory with a data bus width of 8 bits.) 5. 16-byte transfer by the dmac if self-refresh mode is specified for the sdram, the master device cannot release the bus. if the master clock stops because a transition is underway to standby mode or the frequency is changed, or if this lsi is being reset, the master device cannot release the bus. to prevent the slave from issuing bus requests in such a case, the slave must be put into the sleep state so that no slave access cycles are generated. the refresh request and bus request are accepted during the dma burst transfer. bus mastership is maintained until a new bus request is received. bus mastership is released immediately after the completion of the bus cycle in progress when an external bus request ( breq ) is asserted (low level) and a bus acknowledge signal ( back ) is asserted (low level). bus use is resumed when a negation (high level) of breq , which shows that the slave has released the bus, has been received. sdram issues all bank pre-charge commands (palls) when active banks exist and releases the bus after completion of a pall command. the bus release sequence is as follows. the address bus and data bus are placed in a high- impedance state synchronized with the rising edge of ckio. the bus mastership enable signal is asserted 0.5 cycles after the above timing, synchronized with the falling edge of ckio. bus control signals ( bs , csn , rasu , rasl , casu , casl , dqmxx, wen , rd , and rd/ wr ) are made to the high-impedance states at the subsequent rising edge of ckio. bus request signals are sampled at the falling edge of ckio. the sequence for re-claiming bus mastership from a slave is described below. after detecting the negation of breq at the falling edge of ckio, the bus enable signal is negated at the subsequent falling edge of the clock. the address and data signals are driven at the subsequent rising edge of ckio. figure 7.34 shows the bus arbitration timing. rev. 1.0, 11/02, page 237 of 690 ckio a25 to a0 other bus control signals data figure 7.34 bus arbitration in an original slave device designed by the user, multiple bus accesses are generated continuously to reduce the overhead caused by bus arbitration. in this case, to execute sdram refresh correctly, the slave device must be designed to release the bus mastership within the refresh interval time. the bus release by the breq and back signal handshaking requires some overhead. if the slave has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. reducing the cycles required for master to slave bus mastership transitions streamlines the system design. 7.13 others reset: the bus state controller (bsc) can be initialized completely only at power-on reset. at power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. all control registers are initialized. in standby, sleep, and manual reset, control registers of the bus state controller are not initialized. at manual reset, the current bus cycle being executed is completed and then the access wait state is entered. if a 16-byte transfer is performed by a cache or if another lsi on-chip bus master module is executed when a manual reset occurs, the current access is cancelled in longword units because the access request is cancelled by the bus master at manual reset. if a manual reset is requested during cache fill operations, the contents of the cache cannot be guaranteed. since the rtcnt continues counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh cycle. on-chip peripheral module access: to access an on-chip module register, two or more peripheral module clock (p ) cycles are required. care must be taken in system design. rev. 1.0, 11/02, page 238 of 690 dmas311b_000020020100 rev. 1.0, 11/02, page 239 of 690 section 8 direct memory access controller (dmac) this lsi includes the direct memory access controller (dmac). the dmac can be used in place of the cpu to perform high-speed transfers between external devices with dack (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip peripheral modules. 8.1 features ? four channels (two channels can receive an external request) ? 4-gbyte physical address space ? data transfer unit: byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword 4) ? maximum transfer count: 16777216 transfers ? address mode: dual address mode or single address mode can be selected. ? transfer requests: external request, on-chip peripheral module request, or auto request can be selected. the following modules can issue an on-chip peripheral module request. scif0, scif2, cmt, usb, and a/d converter ? bus modes: cycle steal mode (normal mode and intermittent mode 16/64) or burst mode can be selected. ? selectable channel priority levels: the channel priority levels are selectable between fixed mode and round-robin mode. ? interrupt request: an interrupt request can be generated to the cpu after transfers end. ? external request detection: low-/high-level or rising/falling edge detection of dreq input can be selected. ? transfer request acknowledge signal: active levels for dack can be set independently. ? transfer end signal: active level for tend can be set. tend is output at the same timing as dack in the last dma transfer. (only channel 0) rev. 1.0, 11/02, page 240 of 690 figure 8.1 shows the block diagram of the dmac. on-chip peripheral module peripheral bus internal bus external rom dreq0, dreq1 dein dack0, dack1 tend0 external ram external i/o (memory mapped) external i/o (with acknowledge- ment) bus interface bus state controller request priority control start-up control register control transfer count control sar_n dar_n dmatcr_n chcr_n dmaor dmars0?1 [legend] dmaor: dma operation register sarn: dma source address register darn: dma destination address register dmatcrn: dma transfer count register chcrn: dma channel control register dmars0/1: dma extension resource selector dein: dma transfer-end interrupt request to the cpu n : 0, 1, 2, 3 dmac module scif0, scif2 cmt, usb a/d converter figure 8.1 block diagram of dmac rev. 1.0, 11/02, page 241 of 690 8.2 input/output pins the external pins for the dmac are described below. table 8.1 lists the configuration of the pins that are connected to external bus. the dmac has pins for 2 channels (channels 0 and 1) for external bus use. channel 0 has the dma transfer end signal. table 8.1 pin configuration channel name symbol i/o function 0 dma transfer request dreq0 i dma transfer request input from external device to channel 0 dma transfer request acknowledge dack0 o dma transfer request acknowledge output from channel 0 to external device dma transfer end tend0 o transfer end output in channel 0 1 dma transfer request dreq1 i dma transfer request input from external device to channel 1 dma transfer request acknowledge dack1 o dma transfer request acknowledge output from channel 1 to external device 8.3 register descriptions the dmac has the following registers. see section 24, list of registers, for the addresses of these registers and the states of them in each processing state. the sar for channel 0 is expressed such as sar_0. 1. channel 0 ? dma source address register_0 (sar_0) ? dma destination address register_0 (dar_0) ? dma transfer count register_0 (dmatcr_0) ? dma channel control register_0 (chcr_0) 2. channel 1 ? dma source address register_1 (sar_1) ? dma destination address register_1 (dar_1) ? dma transfer count register_1 (dmatcr_1) ? dma channel control register _1 (chcr_1) rev. 1.0, 11/02, page 242 of 690 3. channel 2 ? dma source address register_2 (sar_2) ? dma destination address register_2 (dar_2) ? dma transfer count register_2 (dmatcr_2) ? dma channel control register_2 (chcr_2) 4. channel 3 ? dma source address register_3 (sar_3) ? dma destination address register_3 (dar_3) ? dma transfer count register_3 (dmatcr_3) ? dma channel control register_3 (chcr_3) 5. common ? dma operation register (dmaor) ? dma extended resource selector 0 (dmars0) ? dma extended resource selector 1 (dmars1) 8.3.1 dma source address registers (sar) sar are 32-bit readable/writable registers that specify the source address of a dma transfer. during a dma transfer, these registers indicate the next source address. when the data of an external device with dack is transferred in single address mode, sar is ignored. to transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. when transferring data in 16-byte units, a 16-byte boundary must be set for the source address value. the initial value is undefined. the sar retains the current value in software standby or module standby mode. 8.3.2 dma destination address registers (dar) dar are 32-bit readable/writable registers that specify the destination address of a dma transfer. during a dma transfer, these registers indicate the next destination address. when the data of an external device with dack is transferred in single address mode, dar is ignored. to transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. when transferring data in 16-byte units, a 16-byte boundary must be set for the source address value. the initial value is undefined. the dar retains the current value in software standby or module standby mode. rev. 1.0, 11/02, page 243 of 690 8.3.3 dma transfer count registers (dmatcr) dmatcr are 32-bit readable/writable registers that specify the dma transfer count. the number of transfers is 1 when the setting is h?00000001, 16777215 when h?00ffffff is set, and 16777216 (the maximum) when h?00000000 is set. during a dma transfer, these registers indicate the remaining transfer count. the upper 8 bits of dmatcr are always read as 0. the write value should always be 0. to transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. the initial value is undefined. the dmatcr retains the current value in software standby or module standby mode. 8.3.4 dma channel control registers (chcr) chcr are 32-bit readable/writable registers that control the dma transfer mode. bit bit name initial value r/w descriptions 31 to 24 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 23 do 0 r/w dma overrun selects whether dreq is detected by overrun 0 or by overrun 1. this bit is valid only in chcr_0 and chcr_1. this bit is always read as 0 in chcr_2 and chcr_3. the write value should always be 0. 0: detects dreq by overrun 0 1: detects dreq by overrun 1 22 tl 0 r/w transfer end level selects whether the tend signal output is high active or low active. this bit is valid only in chcr_0. there are no tend pins in chcr_1 to chcr_3. therefore this setting is invalid. this bit is always read as 0. the write value should always be 0. 0: low-active output of tend 1: high-active output of tend 21 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 244 of 690 bit bit name initial value r/w descriptions 17 am 0 r/w acknowledge mode selects whether dack is output in data read cycle or in data write cycle in dual address mode. in single address mode, dack is always output regardless of the specification by this bit. this bit is valid only in chcr_0 and chcr_1. this bit is always read as 0 in chcr_2 and chcr_3. the write value should always be 0. 0: dack output in read cycle (dual address mode) 1: dack output in write cycle (dual address mode) 16 al 0 r/w acknowledge level specifies the dack signal output is high active or low active. this bit is valid only in chcr_0 and chcr_1. this bit is always read as 0 in chcr_2 and chcr_3. the write value should always be 0. 0: low-active output of dack 1: high-active output of dack 15 14 dm1 dm0 0 0 r/w r/w destination address mode specify whether the dma destination address is incremented, decremented, or left fixed. (in single address mode, the dm1 and dm0 bits are ignored when data is transferred to an external device with dack.) 00: fixed destination address 01: destination address is incremented (+1 in byte-size transfer, +2 in word-size transfer, +4 in longword-size transfer, +16 in 16-byte transfer) 10: destination address is decremented (?1 in byte-size transfer, ?2 in word-size transfer, ?4 in longword-size transfer, setting prohibited in 16-byte transfer) 11: setting prohibited rev. 1.0, 11/02, page 245 of 690 bit bit name initial value r/w descriptions 13 12 sm1 sm0 0 0 r/w r/w source address mode specifies whether the dma source address is incremented, decremented, or left fixed. (in single address mode, the sm1 and sm0 bits are ignored when data is transferred from an external device with dack.) 00: fixed source address 01: source address is incremented (+1 in byte-size transfer, +2 in word-size transfer, +4 in longword-size transfer, +16 in 16-byte transfer) 10: source address is decremented (?1 in byte-size transfer, ?2 in word-size transfer, ?4 in longword-size transfer, setting prohibited in 16-byte transfer) 11: setting prohibited 11 10 9 8 rs3 rs2 rs1 rs0 0 0 0 0 r/w r/w r/w r/w resource select specifies which transfer requests will be sent to the dmac. the chan g in g of transfer request source should be done in the state that the dma enable bit (de) is set to 0. 0000: external request, dual address mode 0001: setting prohibited 0010: external request/single address mode external address space external device with dack 0011: external request/single address mode external device with dack external address space 0100: auto request 0101: setting prohibited 0110: setting prohibited 0111: setting prohibited 1000: dma extended resource selector specification 1001: setting prohibited 1010: setting prohibited 1011: setting prohibited 1100: setting prohibited 1101: setting prohibited 1110: peripheral module request, a/d converter 1111: peripheral module request, cmt note: external request specification is valid only in chcr_0 and chcr_1. none of the external request specification can be set in channels chcr_2 and chcr_3. rev. 1.0, 11/02, page 246 of 690 bit bit name initial value r/w descriptions 7 6 dl ds 0 0 r/w r/w dreq level and dreq edge select select the detection method of the dreq pin input and the detection level. these bits are valid only in chcr_0 and chcr_1. these bits are alwa y s read as 0 in chcr_2 and chcr_3. the write value should always be 0. in channels 0 and 1, also, if the transfer request source is specified as an on-chip peripheral module or if an auto-request is specified, these bits are invalid. 00: dreq detected in low level 01: dreq detected at falling edge 10: dreq detected in high level 11: dreq detected at rising edge 5 tb 0 r/w transfer bus mode specifies the bus mode when dma transfers data. 0: cycle steal mode 1: burst mode 4 3 ts1 ts0 0 0 r/w r/w transfer size specify the size of data to be transferred. select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: byte size 01: word size (two bytes) 10: longword size (four bytes) 11: 16-byte unit (four longword transfers) 2 ie 0 r/w interrupt enable specifies whether or not an interrupt request is generated to the cpu at the end of the dma transfer. setting this bit to 1 generates an interrupt request (dei) to the cpu when the te bit is set to 1. 0: interrupt request disabled 1: interrupt request enabled rev. 1.0, 11/02, page 247 of 690 bit bit name initial value r/w descriptions 1te0 r/(w) * transfer end flag indicates that the dma transfer ends. the te bit is set to 1 when data transfer ends when dmatcr becomes to 0. the te bit is not set to 1 in the following cases. ? dma transfer ends due to an nmi interrupt or dma address error before dmatcr becomes to 0. ? dma transfer is ended by clearing the de bit and the dme bit in the dma operation register (dmaor). this bit can only be cleared by writing 0 after reading 1. even if the de bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: during the dma transfer or dma transfer has been aborted [clearing conditions] ? writing 0 after reading te = 1 ? power-on reset ? manual reset 1: data transfer ends by the specified count (dmatcr = 0) 0 de 0 r/w dma enable enables or disables the dma transfer. in auto request mode, dma transfer starts by setting the de bit and dme bit in dmaor to 1. in this time, all of the bits te, nmif in dmaor, and ae must be 0. in an external request or peripheral module request, dma transfer starts if dma transfer request is generated by the devices or peripheral modules after setting the bits de and dme to 1. in this case, however, all of the bits te, nmif, and ae must be 0 an in the case of auto request mode. clearing the de bit to 0 can terminate the dma transfer. 0: dma transfer disabled 1: dma transfer enabled note: * only 0 can be written for clearing the flags. rev. 1.0, 11/02, page 248 of 690 8.3.5 dma operation register (dmaor) dmaor is a 16-bit readable/writable register that specifies the priority level of channels at the dma transfer. this register shows the dma transfer status. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 cms1 cms0 0 0 r/w r/w cycle steal mode select select either normal mode or intermittent mode in cycle steal mode. it is necessary that all channels' bus modes are set to cycle steal mode to make valid intermittent mode. 00: normal mode 01: setting prohibited 10: intermittent mode 16 executes one dma transfer in each of 16 clocks of an external bus clock. 11: intermittent mode 64 executes one dma transfer in each of 64 clocks of an external bus clock. 11, 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 pr1 pr0 0 0 r/w r/w priority mode select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: ch0 > ch1 > ch2 > ch3 01: ch0 > ch2 > ch3 > ch1 10: setting prohibited 11: round-robin mode 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 249 of 690 bit bit name initial value r/w description 2ae0 r/(w) * address error flag indicates that an address error occurred by the dmac. if this bit is set, dma transfer is not enabled even if the de bit in chcr and the dme bit in dmaor are set to 1. this bit can only be cleared by writing 0 after reading 1. 0: no dmac address error [clearing conditions] ? writing 0 after reading ae = 1 ? power-on reset ? manual reset 1: dmac address error. dma transfer disabled. [setting condition] dmac address error occurrence 1nmif0 r/(w) * nmi flag indicates that an nmi interrupt occurred. if this bit is set, dma transfer is not enabled even if the de bit in chcr and the dme bit in dmaor are set to 1. this bit can only be cleared by writing 0 after reading 1. when the nmi is input, the dma transfer in progress can be done in one transfer unit. when the dmac is not in operation, the nmif bit is set to 1 even if the nmi interrupt was input. 0: no nmi interrupt [clearing conditions] ? writing 0 after reading nmif = 1 ? power-on reset ? manual reset 1: nmi input. dma transfer disabled. [setting condition] nmi interrupt occurrence 0 dme 0 r/w dma master enable enables or disables dma transfers on all channels. if the dme bit and the de bit in chcr are set to 1, dma transfers are enabled. in this time, all of the bits te in chcr, nmif in dmaor, and ae must be 0. if this bit is cleared during transfer, transfers in all the channels can be terminated. 0: disable dma transfers on all channels 1: enable dma transfers on all channels note: * only 0 can be written for clearing the flags. rev. 1.0, 11/02, page 250 of 690 8.3.6 dma extended resource selectors 0, 1 (dmars0, dmars1) dmars is a 16-bit readable/writable register that specifies the dma transfer request sources from peripheral modules in each channel. dmars0 specifies for channels 0 and 1, dmars1 for channels 2 and 3. this register can set the transfer request of scif0, scif2 and usb. when mid/rid other than the values listed in table 8.2 is set, the operation of this lsi is not guaranteed. the transfer request from dmars is valid only when the resource select bits (rs3 to rs0) has been set to b'1000 for chcr_0 to chcr_3. otherwise, even if dmars has been set, transfer request source is not accepted. ? dmars0 bit bit name initial value r/w description 15 14 13 12 11 10 c1mid5 c1mid4 c1mid3 c1mid2 c1mid1 c1mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request source module id5 to id0 for dma channel 1 (mid) see table 8.2. 9 8 c1rid1 c1rid0 0 0 r/w r/w transfer request resource register id1 to id0 for dma channel 1 (rid) see table 8.2. 7 6 5 4 3 2 c0mid5 c0mid4 c0mid3 c0mid2 c0mid1 c0mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request source module id5 to id0 for dma channel 0 (mid) see table 8.2 1 0 c0rid1 c0rid0 0 0 r/w r/w transfer request resource register id1 to id0 for dma channel 0 (rid) see table 8.2. rev. 1.0, 11/02, page 251 of 690 ? dmars1 bit bit name initial value r/w description 15 to 10 c3mid5 to c3mid0 all 0 r/w transfer request resource module id5 to id0 for dma channel 3 (mid) see table 8.2. 9 8 c3rid1 c3rid0 0 0 r/w r/w transfer request resource register id1 and id0 for dma channel 3 (rid) see table 8.2. 7 to 2 c2mid5 to c2mid0 all 0 r/w transfer request resource module id5 to id0 for dma channel 2 (mid) see table 8.2. 1 0 c2rid1 c2rid0 0 0 r/w r/w transfer request resource register id1 and id0 for dma channel 2 (rid) see table 8.2. table 8.2 transfer request sources peripheral module setting value for one channel (mid + rid) mid rid function h'21 b'01 transmit scif0 h'22 b'001000 b'10 receive h'29 b'01 transmit scif2 h'2a b'001010 b'10 receive h'73 b'11 transmit usb h'70 b'011100 b'00 receive rev. 1.0, 11/02, page 252 of 690 8.4 operation when there is a dma transfer request, the dmac starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. in bus mode, burst mode or cycle steal mode can be selected. 8.4.1 transfer flow after the dma source address registers (sar), dma destination address registers (dar), dma transfer count registers (dmatcr), dma channel control registers (chcr), dma operation register (dmaor), and dma extended resource selector (dmars) are set, the dmac transfers data according to the following procedure: 1. checks to see if transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0) 2. when a transfer request is generated and transfer is enabled, the dmac transfers 1 transfer unit of data (depending on the ts0 and ts1 settings). for an auto request, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value will be decremented for each transfer. the actual transfer flows vary by address mode and bus mode. 3. when the specified number of transfer have been completed (when dmatcr reaches 0), the transfer ends normally. if the ie bit in chcr is set to 1 at this time, a dei interrupt is sent to the cpu. 4. when an address error or an nmi interrupt is generated, the transfer is aborted. transfers are also aborted when the de bit in chcr or the dme bit in dmaor are cleared to 0. rev. 1.0, 11/02, page 253 of 690 figure 8.2 is a flowchart of this procedure. normal end nmif = 1 or ae = 1 or de = 0 or dme = 0? bus mode, transfer request mode, dreq detection method initial settings (sar, dar, dmatcr, chcr, dmaor, dmars) transfer (1 transfer unit); dmatcr ? 1 dmatcr, sar and dar updated dei interrupt request (when ie = 1) te = 1 no yes no yes no yes yes no yes no * 3 * 2 start transfer aborted dmatcr = 0? transfer request occurs? * 1 de, dme = 1 and nmif, ae, te = 0? nmif = 1 or ae = 1 or de = 0 or dme = 0? transfer end notes: * 1 in auto-request mode, transfer begins when nmif, ae, and te bits are 0 and the de and dme bits are set to 1. * 2 dreq = level detection in burst mode (external request) or cycle-steal mode. * 3 dreq = edge detection in burst mode (external request), or auto-request mode in burst mode. figure 8.2 dmac transfer flowchart rev. 1.0, 11/02, page 254 of 690 8.4.2 dma transfer requests dma transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by external devices and on-chip peripheral modules that are neither the source nor the destination. transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. the request mode is selected in the rs3 to rs0 bits in the dma channel control register (chcr), and dmars0 and dmars1. auto-request mode: when there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bit in chcr and the dme bit in dmaor are set to 1, the transfer begins so long as the ae and nmif bits in dmaor are 0. external request mode: in this mode a transfer is performed at the request signals (dreq0 and dreq1) of an external device. this mode is valid only in channels 0 and 1. choose one of the modes shown in table 8.3 according to the application system. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon a request at the dreq input. table 8.3 selecting external request modes with rs bits rs3 rs2 rs1 rs0 address mode source destination 0000dual address mode any any 1 0 single address mode external memory, memory-mapped external device external device with dack 1 external device with dack external memory, memory-mapped external device choose to detect dreq by either the edge or level of the signal input with the dl bit and ds bit of chcr_0 and chcr_1 as shown in table 8.4. the source of the transfer request does not have to be the data transfer source or destination. rev. 1.0, 11/02, page 255 of 690 table 8.4 selecting external request detection with dl, ds bits chcr_0 or chcr_1 dl ds detection of external request 0 low level detection 0 1 falling edge detection 0 high level detection 1 1 rising edge detection when dreq is accepted, the dreq pin becomes request accept disabled state. after issuing acknowledge signal dack for the accepted dreq, the dreq pin again becomes request accept enabled state. when dreq is used for level detection, there are the following two cases depending on the timing to detect the next dreq after outputting dack. a case wherein transfer is aborted after the same number of transfers has been performed as requests (overrun 0) and wherein another transfer is aborted after transfers have been performed for (the number of requests plus 1) times (overrun 1). the do bit in chcr selects overrun 0 or overrun 1. table 8.5 selecting external request detection with do bit chcr_0 or chcr_1 do external request 0 overrun 0 1 overrun 1 rev. 1.0, 11/02, page 256 of 690 on-chip peripheral module request mode: in this mode a transfer is performed at the transfer request signal of an on-chip peripheral module. transfer request signals comprise the transmit data empty transfer request and receive data full transfer request from the scif0 and scif2 set by dmars0/1, the compare-match timer transfer request from the cmt, and transfer requests from the usb. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon the input of a transfer request signal. when a transmit data empty transfer request of the scif is set as the transfer request, the transfer destination must be the scif?s transmit data register. likewise, when receive data full transfer request of the scif is set as the transfer request, the transfer source must be the scif?s receive data register. these conditions also apply to the usb. any address can be specified for data source and destination, when transfer request is generated by the cmt. table 8.6 selecting on-chip peripheral module request modes with rs3 to rs0 bits rs3 rs2 rs1 rs0 dma transfer request source dma transfer request signal source destination bus mode 1 1 1 0 adc ad-conversion end request addr any cycle steal 1 111cmt compare-match transfer request any any burst/ cycle steal table 8.7 selecting on-chip peripheral module request modes with rs3 to rs0 bits chcr dmars rs[3:0] mid rid dma transfer request source dma transfer request signal source destination bus mode 01 scif0 transmitter txi0 (transmit fifo data empty) any scftdr_0 cycle steal 001000 10 scif0 receiver rxi0 (receive fifo data full) scfrdr_0 any cycle steal 01 scif2 transmitter txi2 (transmit fifo data empty) any scftdr_2 cycle steal 001010 10 scif2 receiver rxi2 (receive fifo data full) scfrdr_2 any cycle steal 11 usb transmitter ep2 fifo empty transfer request any epdr2 cycle steal 1000 011100 00 usb receiver ep1 fifo full transfer request epdr1 any cycle steal rev. 1.0, 11/02, page 257 of 690 8.4.3 channel priority when the dmac receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. two modes (fixed mode and round-robin mode) are selected by bits pr1 and pr0 in the dma operation register (dmaor). fixed mode: in these modes, the priority levels among the channels remain fixed. there are two kinds of fixed modes as follows: ch0 > ch1 > ch2 > ch3 ch0 > ch2 > ch3 > ch1 these are selected by the pr1 and the pr0 bits in the dma operation register (dmaor). rev. 1.0, 11/02, page 258 of 690 round-robin mode: each time one byte, word, longword, or 16-byte is transferred on one channel, the priority order is rotated. the channel on which the transfer was just finished rotates to the bottom of the priority order. the round-robin mode operation is shown in figure 8.3. the priority of round-robin mode is ch0 > ch1 > ch2 > ch3 immediately after a reset. ch 1 > ch2 > ch3 > ch0 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 ch3 > ch0 > ch1 > ch2 ch0 > ch1 > ch2 > ch3 (1) when channel 0 transfers initial priority order initial priority order initial priority order initial priority order priority order after transfer priority order does not change channel 2 becomes bottom priority. the priority of channels 0 and 1, which were higher than channel 2, are also shifted. if immediately after there is a request to transfer channel 1 only, channel 1 becomes bottom priority and the priority of channels 3 and 0, which were higher than channel 1, are also shifted. channel 1 becomes bottom priority. the priority of channel 0, which was higher than channel 1, is also shifted. channel 0 becomes bottom priority priority order after transfer priority order after transfer priority order after transfer post-transfer priority order when there is an immediate transfer request to channel 1 only (2) when channel 1 transfers (3) when channel 2 transfers (4) when channel 3 transfers figure 8.3 round-robin mode rev. 1.0, 11/02, page 259 of 690 figure 8.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. the dmac operates as follows: 1. transfer requests are generated simultaneously to channels 0 and 3. 2. channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. a channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. when the channel 0 transfer ends, channel 0 becomes lowest priority. 5. at this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. when the channel 1 transfer ends, channel 1 becomes lowest priority. 7. the channel 3 transfer begins. 8. when the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority. transfer request waiting channel(s) dmac operation channel priority (1) channels 0 and 3 (3) channel 1 0 > 1 > 2 > 3 (2) channel 0 transfer start (4) channel 0 transfer ends (5) channel 1 transfer starts (6) channel 1 transfer ends (7) channel 3 transfer starts (8) channel 3 transfer ends 1 > 2 > 3 > 0 2 > 3 > 0 > 1 0 > 1 > 2 > 3 priority order changes priority order changes priority order changes none 3 3 1,3 figure 8.4 channel priority in round-robin mode rev. 1.0, 11/02, page 260 of 690 8.4.4 dma transfer types dma transfer has two types; single address mode transfer and dual address mode transfer. they depend on the number of bus cycles of access to source and destination. a data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. the dmac supports the transfers shown in table 8.8. table 8.8 supported dma transfers destination source external device with dack external memory memory- mapped external device on-chip peripheral module external device with dack not available dual, single dual, single not available external memory dual, single dual dual dual memory-mapped external device dual, single dual dual dual on-chip peripheral module not available dual dual dual notes: 1. dual: dual address mode 2. single: single address mode 3. a 16-byte transfer is available only for the registers to which longword-size access is enabled in the on-chip peripheral modules. rev. 1.0, 11/02, page 261 of 690 address modes ? dual address mode in dual address mode, both the transfer source and destination are accessed by an address. the source and destination can be located externally or internally. dma transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. at this time, transfer data is temporarily stored in the dmac. in the transfer between external memories as shown in figure 8.5, data is read to the dmac from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar the sar value is an address, data is read from the transfer source module, and the data is temporarily stored in the dmac. the dar value is an address and the value stored in the data buffer in the dmac is written to the transfer destination module. dmac dmac first bus cycle second bus cycle figure 8.5 data flow of dual address mode auto request, external request, and on-chip peripheral module request are available for the transfer request. dack can be output in read cycle or write cycle in dual address mode. channel control register (chcr) can specify whether the dack is output in read cycle or write cycle. figure 8.6 shows an example of dma transfer timing in dual address mode. rev. 1.0, 11/02, page 262 of 690 ckio a25 to a0 note: in transfer between external memories, with dack output in the read cycle, dack output timing is the same as that of csn. d31 to d0 dackn (active-low) transfer source address transfer destination address data read cycle data write cycle (1st cycle) (2nd cycle) figure 8.6 example of dma transfer timing in dual mode (source: ordinary memory, destination: ordinary memory) ? single address mode in single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the dack signal, and the other device is accessed by address. in this mode, the dmac performs one dma transfer in one bus cycle, accessing one of the external devices by outputting the dack transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. for example, in the case of transfer between external memory and an external device with dack shown in figure 8.7, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. rev. 1.0, 11/02, page 263 of 690 dmac this lsi dack dreq external address bus external data bus external memory external device with dack data flow figure 8.7 data flow in single address mode two kinds of transfer are possible in single address mode: (1) transfer between an external device with dack and a memory-mapped external device, and (2) transfer between an external device with dack and external memory. in both cases, only the external request signal (dreq) is used for transfer requests. figures 8.8 shows example of dma transfer timing in single address mode. address output to external memory space select signal to external memory space select signal to external memory space data output from external device with dack dack signal (active-low) to external device with dack write strobe signal to external memory space address output to external memory space data output from external memory space dack signal (active-low) to external device with dack read strobe signal to external memory space (a) external device with dack external memory space (ordinary memory) (b) external memory space (ordinary memory) external device with dack ckio a25 to a0 d31 to d0 dackn ckio a25 to a0 d31 to d0 dackn figure 8.8 example of dma transfer timing in single address mode rev. 1.0, 11/02, page 264 of 690 bus modes: there are two bus modes: cycle steal and burst. select the mode in the tb bits of channel control register (chcr). a. cycle-steal mode ? normal mode in the normal mode of cycle-steal, the bus right is given to another bus master after a one- transfer-unit (byte, word, long-word, or 16 bytes unit) dma transfer. when another transfer request occurs, the bus rights are obtained from the other bus master and a transfer is performed for one transfer unit. when that transfer ends, the bus right is passed to the other bus master. this is repeated until the transfer end conditions are satisfied. in cycle-steal mode, transfer areas are not affected regardless of settings of the transfer request source, transfer source, and transfer destination. figure 8.9 shows an example of dma transfer timing in cycle steal mode. transfer conditions shown in the figure are: ? dual address mode ? dreq low level detection cpu cpu cpu dmac dmac cpu dmac dmac cpu dreq bus cycle bus right returned to cpu once read/write read/write figure 8.9 dma transfer example in cycle-steal normal mode (dual address, dreq low level detection) ? intermittent mode 16 and intermittent mode 64 in intermittent mode of cycle steal, dmac returns the bus right to other bus master whenever a unit of transfer (byte, word, longword, or 16 bytes) is complete. if the next transfer request occurs after that, dmac gets the bus right from other bus master after waiting for 16 or 64 clocks in b count. dmac then transfers data of one unit and returns the bus right to other bus master. these operations are repeated until the transfer end condition is satisfied. it is thus possible to make lower the ratio of bus occupation by dma transfer than the normal mode of cycle steal. when dmac gets again the bus right, dma transfer can be postponed in case of entry updating due to cache miss. this intermittent mode can be used for all transfer section; transfer requester, source, and destination. the bus modes, however, must be cycle steal mode in all channels. rev. 1.0, 11/02, page 265 of 690 figure 8.10 shows an example of dma transfer timing in cycle steal intermittent mode. transfer conditions shown in the figure are: ? dual address mode ? dreq low level detection dreq cpu cpu bus cycle cpu more than 16 or 64 b (change by the cpu's condition of using bus) dmac dmac cpu cpu dmac dmac cpu read/write read/write figure 8.10 example of dma transfer in cycle steal intermittent mode (dual address, dreq low level detection) b. burst mode once the bus right is obtained, the transfer is performed continuously until the transfer end condition is satisfied. in external request mode with low level detection of the dreq pin, however, when the dreq pin is driven high, the bus passes to the other bus master after the dmac transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. burst mode cannot be used for other than the cmt when the on-chip peripheral module is the transfer request source. figure 8.11 shows dma transfer timing in burst mode. cpu cpu cpu dmac dmac dmac dmac dmac dmac cpu dreq bus cycle read read read write write write figure 8.11 dma transfer example in burst mode (dual address, dreq low level detection) rev. 1.0, 11/02, page 266 of 690 relationship between request modes and bus modes by dma transfer category: table 8.9 shows the relationship between request modes and bus modes by dma transfer category. table 8.9 relationship of request modes and bus modes by dma transfer category address mode transfer category request mode bus mode transfer size (bits) usable channels dual external device with dack and external memory external b/c 8/16/32/128 0, 1 external device with dack and memory- mapped external device external b/c 8/16/32/128 0, 1 external memory and external memory all * 1 b/c 8/16/32/128 0 to 3 * 5 external memory and memory-mapped external device all * 1 b/c 8/16/32/128 0 to 3 * 5 memory-mapped external device and memory-mapped external device all * 1 b/c 8/16/32/128 0 to 3 * 5 external memory and on-chip peripheral module all * 2 b/c * 3 8/16/32/128 * 4 0 to 3 * 5 memory-mapped external device and on-chip peripheral module all * 2 b/c * 3 8/16/32/128 * 4 0 to 3 * 5 on-chip peripheral module and on-chip peripheral module all * 2 b/c * 3 8/16/32/128 * 4 0 to 3 * 5 single external device with dack and external memory external b/c 8/16/32 0, 1 external device with dack and memory- mapped external device external b/c 8/16/32 0, 1 b: burst, c: cycle steal notes: 1. external requests, auto requests, and on-chip peripheral module requests are all available. in the case of on-chip peripheral module requests, however, the cmt is only available. 2. external requests, auto requests, and on-chip peripheral module requests are all available. however, with the exception of the cmt, the module must be designated as the transfer request source or the transfer destination. 3. only cycle steal except for the cmt as the transfer source. 4. access size permitted for the on-chip peripheral module register functioning as the transfer source or transfer destination. 5. if the transfer request is an external request, channels 0 and 1 are only available. bus mode and channel priority order: when a given channel 1 is transferring in burst mode and there is a transfer request to a channel 0 with a higher priority, the transfer of channel 0 will begin immediately. at this time, if the priority is set in fixed mode (ch0 > ch1), the channel 1 transfer will continue when the channel 0 transfer has completely finished, even if channel 0 is operating in cycle steal mode or in burst mode. rev. 1.0, 11/02, page 267 of 690 if the priority is set in round-robin mode, channel 1 will begin operating again after channel 0 completes the transfer of one transfer unit, even if channel 0 is in cycle steal mode or in burst mode. the bus will then switch between the two in the order channel 1, channel 0, channel 1, channel 0. even if the priority is set in fixed mode or in round-robin mode, it will not give the bus to the cpu since channel 1 is in burst mode. this example is illustrated in figure 8.12. cpu dma ch1 dma ch1 dma ch0 dma ch1 dma ch0 dma ch1 dma ch1 cpu ch0 ch1 ch0 round-robin mode in dmac ch0 and ch1 dmac ch1 burst mode cpu cpu priority: round-robin mode ch0: cycle-steal mode ch1: burst mode dmac ch1 burst mode figure 8.12 bus state when multiple channels are operating 8.4.5 number of bus cycle states and dreq pin sampling timing number of bus cycle states: when the dmac is the bus master, the number of bus cycle states is controlled by the bus state controller (bsc) in the same way as when the cpu is the bus master. for details, see section 7, bus state controller (bsc). dreq pin sampling timing: ckio bus cycle dreq (rising) dack (active-high) cpu cpu acceptance start 2nd acceptance 1st acceptance cpu dmac non sensitive period figure 8.13 example of dreq input detection in cycle steal mode edge detection rev. 1.0, 11/02, page 268 of 690 ckio bus cycle bus cycle dreq (overrun 0 at high level) dack (active-high) cpu cpu cpu dmac ckio dreq (overrun 1 at high level) dack (active-high) cpu cpu cpu dmac non sensitive period 1st acceptance 2nd acceptance acceptance start acceptance start 1st acceptance 2nd acceptance non sensitive period figure 8.14 example of dreq input detection in cycle steal mode level detection ckio bus cycle dreq (rising) dack (active-high) cpu cpu dmac dmac non sensitive period busrst acceptance figure 8.15 example of dreq input detection in burst mode edge detection rev. 1.0, 11/02, page 269 of 690 ckio bus cycle bus cycle dreq (overrun 0 at high level) dack (active-high) cpu 1st acceptance cpu dmac ckio dreq (overrun 1 at high level) dack (active-high) cpu cpu dmac dmac 2nd acceptance acceptance start acceptance start acceptance start non sensitive non sensitive 1st acceptance 2nd acceptance 3rd acceptance figure 8.16 example of dreq input detection in burst mode level detection ckio bus cycle dack dreq tend cpu cpu cpu dmac last dma transfer dmac figure 8.17 example of dma transfer end signal (in cycle steal level detection) rev. 1.0, 11/02, page 270 of 690 ckio address data dackn t1 t2 taw t1 t2 tend0 note: tend0 is asserted during the last transfer unit of dma transfer. when the transfer unit is divided into several bus cycles and is negated between bus cycles, tend0 is also divided. figure 8.18 bsc ordinary memory access (no wait, idle cycle 1, longword access to 16-bit device) cpgs312b_000020020100 rev. 1.0, 11/02, page 271 of 690 section 9 clock pulse generator (cpg) this lsi has a clock pulse generator (cpg) that generates an internal clock (i ), a peripheral clock (p ), and a bus clock (b ). the cpg consists of oscillators, pll circuits, and divider circuits. 9.1 features ? seven clock modes selection of seven clock modes depending on the frequency ranges and crystal oscillation or external clock input. ? three clocks generated independently an internal clock for the cpu and cache (i ); a peripheral clock (p ) for the peripheral modules; a bus clock (b = ckio) for the external bus interface. ? frequency change function internal and peripheral clock frequencies can be changed independently using the phase-locked loop (pll) circuit and divider circuit within the cpg. frequencies are changed by software using the frequency control register (frqcr) settings. ? power-down mode control the clock can be stopped for sleep mode and software standby mode and specific modules can be stopped using the module standby function. a block diagram of the cpg is shown in figure 9.1. rev. 1.0, 11/02, page 272 of 690 xtal_usb extal_usb ckio pll circuit 1 ( 1, 2, 3, 4) crystal oscillator pll circuit 2 ( 1, 2, 4) 1 1/2 1/3 1/4 cpg oscillator circuit unit internal clock (i ) internal bus bus interface frqcr: stbcr: stbcr2: stbcr3: uclkcr: frequency control register standby control register standby control register 2 standby control register 3 usb clock control register peripheral clock (p ) bus clock (b = ckio) xtal extal md2 md1 md0 frqcr uclkcr stbcr stbcr2 stbcr3 cpg control unit usb clock clock frequency control circuit standby control circuit divider 1 crystal oscillator figure 9.1 block diagram of clock pulse generator rev. 1.0, 11/02, page 273 of 690 the clock pulse generator blocks function as follows: 1. pll circuit 1 pll circuit 1 doubles, triples, quadruples, or leaves unchanged the input clock frequency from the ckio pin or pll circuit 2. the multiplication rate is set by the frequency control register. when this is done, the phase of the rising edge of the internal clock is controlled so that it will synchronize with the phase of the rising edge of the ckio pin. 2. pll circuit 2 pll circuit 2 leaves unchanged, doubles, or quadruples the input clock frequency coming from the crystal oscillator or extal pin. the multiplication ratio is fixed by the clock-operating mode. the clock-operating mode is set by pins md0, md1, and md2. for more details on clock operating modes, refer to table 9.2. 3. crystal oscillator this oscillator circuit is used when a crystal resonator is connected to the xtal and extal pins. this crystal oscillator operates according to the clock operating mode setting. 4. divider 1 divider 1 generates a clock at the operating frequency used by the internal or peripheral clock. the operating frequency can be 1, 1/2, 1/3, or 1/4 times the output frequency of pll circuit 1, as long as it stays at or above the clock frequency of the ckio pin. the division ratio is set in the frequency control register. 5. clock frequency control circuit the clock frequency control circuit controls the clock frequency using the md0, md1, and md2 pins and the frequency control register. 6. standby control circuit the standby control circuit controls the state of the on-chip oscillator and other modules during clock switching and software/standby modes. 7. frequency control register the frequency control register has control bits assigned for the following functions: clock output/non-output from the ckio pin, the frequency multiplication ratio of pll circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. 8. standby control register the standby control register has bits for controlling the power-down modes. see section 11, power-down modes, for more information. 9. usb clock control register the source clock generating the usb clock is set in the usb clock control register. rev. 1.0, 11/02, page 274 of 690 9.2 input/output pins table 9.1 lists the cpg pins and their functions. table 9.1 clock pulse generator pins and functions pin name symbol i/o description md0 i set the clock-operating mode. md1 i set the clock-operating mode. mode control pins md2 i set the clock-operating mode. xtal o connects a crystal resonator. crystal oscillator pins for system clock (clock input pins) extal i connects a crystal resonator. also used to input an external clock. clock i/o pin ckio i/o inputs or outputs an external clock. xtal_usb o connects a crystal resonator for the usb. crystal oscillator pins for usb (clock input pins) extal_usb i connects a crystal resonator for the usb. also used to input an external clock. note: the values of the mode control pins are sampled only in a power-on reset. this can prevent the erroneous operation of the lsi. rev. 1.0, 11/02, page 275 of 690 9.3 clock operating modes table 9.2 shows the relationship between the mode control pins (md2 to md0) combinations and the clock operating modes. table 9.3 shows the usable frequency ranges in the clock operating modes and the frequency range of the input clock. table 9.2 clock operating modes pin values clock i/o mode md2 md1 md0 source output pll2 on/off pll1 on/off ckio frequency 0 0 0 0 extal ckio on ( 1) on ( 1, 2, 3, 4) (extal) 1 0 0 1 extal ckio on ( 4) on ( 1, 2, 3, 4) (extal) 4 2 010 crystal resonator ckio on ( 4) on ( 1, 2, 3, 4) (crystal) 4 4 100 crystal resonator ckio on ( 1) on ( 1, 2, 3, 4) (crystal) 5 1 0 1 extal ckio on ( 2) on ( 1, 2, 3, 4) (extal) 2 6 110 crystal resonator ckio on ( 2) on ( 1, 2, 3, 4) (crystal) 2 7 111 ckio ? off on ( 1, 2, 3, 4) (ckio) mode 0: an external clock is input from the extal pin and executes waveform shaping by pll circuit 2 before being supplied inside this lsi. mode 1: an external clock is input from the extal pin and its frequency is multiplied by 4 by pll circuit 2 before being supplied inside this lsi, allowing a low-frequency external clock to be used. mode 2: the on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 4 by pll circuit 2 before being supplied inside this lsi, allowing a low-frequency external clock to be used. mode 4: the on-chip crystal oscillator operates and executes waveform shaping by pll circuit 2 before being supplied inside this lsi. mode 5: an external clock is input from the extal pin and its frequency is multiplied by 2 by pll circuit 2 before being supplied inside this lsi, allowing a low-frequency external clock to be used. mode 6: the on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 2 by pll circuit 2 before being supplied inside this lsi, allowing a low crystal frequency to be used. rev. 1.0, 11/02, page 276 of 690 mode 7: in this mode, the ckio pin is an input, an external clock is input to this pin, and executes waveform shaping, and also frequency multiplication according to the setting, by pll circuit 1 before being supplied to this lsi. as pll circuit 1 compensates for fluctuations in the ckio pin load, this mode is suitable for connection of synchronous dram. table 9.3 possible combination of clock modes and frqcr values clock mode frqcr * 1 pll1 pll2 clock rate * 2 (i:b:p) input clock/crystal resonator frequency range ckio frequency range h'1000 on ( 1) on ( 1) 1:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1001 on ( 1) on ( 1) 1:1:1/2 20.00 mhz to 66.67 mhz 20.00 mhz to 66.67 mhz h'1003 on ( 1) on ( 1) 1:1:1/4 20.00 mhz to 66.67 mhz 20.00 mhz to 66.67 mhz h'1101 on ( 2) on ( 1) 2:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1103 on ( 2) on ( 1) 2:1:1/2 20.00 mhz to 66.67 mhz 20.00 mhz to 66.67 mhz h'1111 on ( 2) on ( 1) 1:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1113 on ( 2) on ( 1) 1:1:1/2 20.00 mhz to 66.67 mhz 20.00 mhz to 66.67 mhz h'1202 on ( 3) on ( 1) 3:1:1 26.70 mhz to 33.34 mhz 26.70 mhz to 33.34 mhz h'1222 on ( 3) on ( 1) 1:1:1 26.70 mhz to 33.34 mhz 26.70 mhz to 33.34 mhz h'1303 on ( 4) on ( 1) 4:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1313 on ( 4) on ( 1) 2:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz 0 h'1333 on ( 4) on ( 1) 1:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1001 on ( 1) on ( 4) 4:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz h'1003 on ( 1) on ( 4) 4:4:1 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz h'1103 on ( 2) on ( 4) 8:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1, 2 h'1113 on ( 2) on ( 4) 4:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz h'1000 on ( 1) on ( 1) 1:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1001 on ( 1) on ( 1) 1:1:1/2 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1003 on ( 1) on ( 1) 1:1:1/4 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1101 on ( 2) on ( 1) 2:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1103 on ( 2) on ( 1) 2:1:1/2 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1111 on ( 2) on ( 1) 1:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1113 on ( 2) on ( 1) 1:1:1/2 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1202 on ( 3) on ( 1) 3:1:1 26.70 mhz to 33.34 mhz 26.70 mhz to 33.34 mhz h'1222 on ( 3) on ( 1) 1:1:1 26.70 mhz to 33.34 mhz 26.70 mhz to 33.34 mhz h'1303 on ( 4) on ( 1) 4:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1313 on ( 4) on ( 1) 2:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz 4 h'1333 on ( 4) on ( 1) 1:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz rev. 1.0, 11/02, page 277 of 690 clock mode frqcr * 1 pll1 pll2 clock rate * 2 (i:b:p) input clock / crystal resonator frequency range ckio frequency range h'1000 on ( 1) on ( 2) 2:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.34 mhz h'1001 on ( 1) on ( 2) 2:2:1 10.00 mhz to 33.34 mhz 20.00 mhz to 66.67 mhz h'1003 on ( 1) on ( 2) 2:2:1/2 10.00 mhz to 33.34 mhz 20.00 mhz to 66.67 mhz h'1101 on ( 2) on ( 2) 4:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.33 mhz h'1103 on ( 2) on ( 2) 4:2:1 10.00 mhz to 33.34 mhz 20.00 mhz to 66.67 mhz h'1111 on ( 2) on ( 2) 2:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.34 mhz h'1113 on ( 2) on ( 2) 2:2:1 10.00 mhz to 33.34 mhz 20.00 mhz to 66.67 mhz h'1202 on ( 3) on ( 2) 6:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.34 mhz h'1222 on ( 3) on ( 2) 2:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.34 mhz h'1303 on ( 4) on ( 2) 8:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.33 mhz h'1313 on ( 4) on ( 2) 4:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.33 mhz 5 h'1333 on ( 4) on ( 2) 2:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.34 mhz h'1000 on ( 1) on ( 2) 2:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.34 mhz h'1001 on ( 1) on ( 2) 2:2:1 10.00 mhz to 33.34 mhz 20.00 mhz to 66.67 mhz h'1003 on ( 1) on ( 2) 2:2:1/2 10.00 mhz to 33.34 mhz 20.00 mhz to 66.67 mhz h'1101 on ( 2) on ( 2) 4:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.33 mhz h'1103 on ( 2) on ( 2) 4:2:1 10.00 mhz to 33.34 mhz 20.00 mhz to 66.67 mhz h'1111 on ( 2) on ( 2) 2:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.34 mhz h'1113 on ( 2) on ( 2) 2:2:1 10.00 mhz to 33.34 mhz 20.00 mhz to 66.67 mhz h'1202 on ( 3) on ( 2) 6:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.34 mhz h'1222 on ( 3) on ( 2) 2:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.34 mhz h'1303 on ( 4) on ( 2) 8:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.33 mhz h'1313 on ( 4) on ( 2) 4:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.33 mhz 6 h'1333 on ( 4) on ( 2) 2:2:2 10.00 mhz to 16.67 mhz 20.00 mhz to 33.34 mhz rev. 1.0, 11/02, page 278 of 690 clock mode frqcr * 1 pll1 pll2 clock rate * 2 (i:b:p) input clock / crystal resonator frequency range ckio frequency range h'1000 on ( 1) off 1:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1001 on ( 1) off 1:1:1/2 20.00 mhz to 66.67 mhz 20.00 mhz to 66.67 mhz h'1003 on ( 1) off 1:1:1/4 20.00 mhz to 66.67 mhz 20.00 mhz to 66.67 mhz h'1101 on ( 2) off 2:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1103 on ( 2) off 2:1:1/2 20.00 mhz to 66.67 mhz 20.00 mhz to 66.67 mhz h'1111 on ( 2) off 1:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1113 on ( 2) off 1:1:1/2 20.00 mhz to 66.67 mhz 20.00 mhz to 66.67 mhz h'1202 on ( 3) off 3:1:1 26.70 mhz to 33.34 mhz 26.70 mhz to 33.34 mhz h'1222 on ( 3) off 1:1:1 26.70 mhz to 33.34 mhz 26.70 mhz to 33.34 mhz h'1303 on ( 4) off 4:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz h'1313 on ( 4) off 2:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz 7 h'1333 on ( 4) off 1:1:1 20.00 mhz to 33.34 mhz 20.00 mhz to 33.34 mhz notes: * 1 this lsi cannot operate in an frqcr value other than that listed in table 9.3. * 2 taking input clock frequency ratio as 1. cautions: 1. the input to divider 1 is the output of the pll circuit 1. 2. the frequency of the internal clock (i ) is: ? the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 1. do not set the internal clock frequency lower than the ckio pin frequency. 3. the frequency of the peripheral clock (p ) is: the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 1. the peripheral clock frequency should not be set higher than the frequency of the ckio pin, higher than 33.34 mhz, or lower than 13 mhz when the usb is used. 4. 1, 2, 3, or 4 can be used as the multiplication ratio of pll circuit 1. 1, 1/2, 1/ 3, or 1/4 can be selected as the division ratios of divider 1. set the rate in the frequency control register. 5. the output frequency of pll circuit 1 is the product of the ckio frequency and the multiplication ratio of pll circuit 1. use the output frequency under 133.34 mhz. rev. 1.0, 11/02, page 279 of 690 9.4 register descriptions the cpg has the following registers. refer to section 24, list of registers, for the addresses of the registers and the state of each register in each processor state. ? frequency control register (frqcr) ? usb clock control register (uclkcr) 9.4.1 frequency control register (frqcr) the frequency control register (frqcr) is a 16-bit readable/writable register used to specify whether a clock is output from the ckio pin, the on/off state of pll circuit 1, pll standby, the frequency multiplication ratio of pll circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. only word access can be used on frqcr. as for the combination of the clock rate, refer to table 9.3, possible combination of clock modes and frqcr values. the combinations listed in table 9.3 should only be set on frqcr. bit bit name initial value r/w description 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 ckoen 1 r/w clock output enable specifies to output a clock from the ckio pin or to fix the ckio pin low when software standby is canceled (after an interrupt before status1 becomes low and status0 becomes low). the ckio pin is fixed low during status1 = low and status0 = high, when the ckoen bit is cleared to 0. therefore, the malfunction of an external circuit because of an unstable ckio clock in releasing software standby mode can be prevented. in clock operating mode 7, the ckio pin is in the input state regardless of this bit. 0: fixes the ckio pin low in software standby mode. 1: outputs a clock from the ckio pin. 11, 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 280 of 690 bit bit name initial value r/w description 9 8 stc1 stc0 0 0 r/w r/w frequency multiplication ratio 00: 1 time 01: 2 times 10: 3 times 11: 4 times 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 4 ifc1 ifc0 0 0 r/w r/w internal clock frequency division ratio specify the frequency division ratio of the internal clock with respect to the output frequency of pll circuit 1. 00: 1 time 01: 1/2 time 10: 1/3 time 11: 1/4 time 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 pfc1 pfc0 1 1 r/w r/w peripheral clock frequency division ratio specify the frequency division ratio of the peripheral clock with respect to the output frequency of pll circuit 1. 00: 1 time 01: 1/2 time 10: 1/3 time 11: 1/4 time rev. 1.0, 11/02, page 281 of 690 9.4.2 usb clock frequency control register (uclkcr) uclkcr is an 8-bit readable/writable register. word-size access is used to write to this register. this writing should be performed with h'a5 in the upper byte and the write data in the lower byte. bit bit name initial value r/w description 7 6 usscs1 usscs0 1 1 r/w r/w source clock selection bit these bits select the source clock. 00: clock stopped 01: setting prohibited 10: setting prohibited 11: external input clock 5 usben 1 r/w usb on-chip oscillator enable this bit controls the operation of the usb on-chip oscillator. 0: usb on-chip oscillator stopped 1: usb on-chip oscillator operates 4 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9.4.3 usage notes note the following when using the usb. if these are used incorrectly, the correct clocks may not be generated, causing faulty operation of the usb. 1. uclkcr is used only for generation of the usb clocks. when the usb is not used, it is recommended that uclkcr be cleared to h'00 to halt the clock. 2. halt the usb before changing the values of uclkcr. halt the usb by stopping the clock supply using the usb module stop bits in stbcr3. 3. uclkcr is initialized only by a power-on reset. in a manual reset, they retain their current set values. 4. use the usb module with p > 13 mhz. otherwise, the operation of this lsi is not guaranteed. rev. 1.0, 11/02, page 282 of 690 9.5 changing frequency the frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of pll circuit 1 or by changing the division rates of divider 1. all of these are controlled by software through the frequency control register. the methods are described below. 9.5.1 changing multiplication rate a pll settling time is required when the multiplication rate of pll circuit 1 is changed. the on- chip wdt counts the settling time. 1. in the initial state, the multiplication rate of pll circuit 1 is 1. 2. set a value that will become the specified oscillation settling time in the wdt and stop the wdt. the following must be set: wtcsr.tme = 0: wdt stops wtcsr.cks[2:0]: division ratio of wdt count clock wtcnt: initial counter value 3. set the desired value in the stc[1:0] bits. the division ratio can also be set in the ifc[1:0] bits and pfc[1:0] bits. 4. the processor pauses internally and the wdt starts incrementing. the internal and peripheral clocks both stop and the wdt is supplied with the clock. the clock will continue to be output at the ckio pin. 5. supply of the clock that has been set begins at wdt count overflow, and the processor begins operating again. the wdt stops after it overflows. 9.5.2 changing division ratio the wdt will not count unless the multiplication rate is changed simultaneously. 1. in the initial state, ifc[1:0] = 00 and pfc[1:0] = 11. 2. set the ifc[1:0], pfc[1:0] bits to the new division ratio. the values that can be set are limited by the clock mode and the multiplication rate of pll circuit 1. note that if the wrong value is set, the processor will malfunction. 3. the clock is immediately supplied at the new division ratio. 9.5.3 modification of clock operating mode the values of the mode control pins (md2 to md0) that define a clock-operating mode are reflected at power-on reset. rev. 1.0, 11/02, page 283 of 690 9.6 usage notes when using an external crystal resonator: place the crystal resonator, capacitors cl1 and cl2, and damping resistance r as close as possible to the extal and xtal pins. to prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components. note: the values for cl1, cl2, and damping resistance should be determined after consultation with the crystal resonator manufacturer. xtal extal this lsi cl2 r cl1 avoid crossing signal lines figure 9.2 points for attention when using crystal resonator decoupling capacitors: as far as possible, insert a laminated ceramic capacitor of 0.1 to 1 f as a passive capacitor for each v ss /v ss q and v cc /v cc q pair. mount the passive capacitors as close as possible to the chip?s power supply pins, and use components with a frequency characteristic suitable for the chip?s operating frequency, as well as a suitable capacitance value. digital system v ss /v ss q and v cc /v cc q pairs: 2-5, 17-19, 26-28, 32-34, 44-46, 57-59, 69-71, 78-80, 87-89, 111-113, 130-132, 133-138, 159-161, 178-180, 182-184, 199-204 on-chip oscillator v ss /v ss q and v cc /v cc q pairs: 6-9, 149-150, 151-152, 205-208 when using a pll oscillator circuit: keep the wiring from the pll v cc and pll v ss connection pattern to the power supply pins short, and make the pattern width wide, to minimize the inductance value. in clock mode 7, connect the extal pin to v cc q (3.3-v power) with pull-up resistor, and leave the xtal pin open. rev. 1.0, 11/02, page 284 of 690 v cc -pll2 v cc -pll1 v cc v ss v ss -pll2 v ss -pll1 avoid crossing signal lines power supply figure 9.3 points for attention when using pll oscillator circuit notes on wiring power supply pins: to avoid crossing signal lines, wire v cc ? pll1, v cc ? pll2, v ss ? pll1, and v ss ? pll2 as three patterns from the power supply source on the board so that they are independent of digital v cc and v ss . wdts311a_000020020100 rev. 1.0, 11/02, page 285 of 690 section 10 watchdog timer (wdt) this lsi includes the watchdog timer (wdt) and can be reset by the overflow of the counter when the value of the counter has not been updated because of an erroneous system operation. the wdt is a single-channel timer that uses a peripheral clock as an input and counts the clock settling time when clearing software standby mode and temporary standbys, such as frequency changes. it can also be used as a conventional watchdog timer or an interval timer. 10.1 features ? can be used to ensure the clock settling time use the wdt to clear software standby mode and the temporary standbys which occur when the clock frequency is changed. ? can switch between watchdog timer mode and interval timer mode. ? generates internal resets in watchdog timer mode internal resets occur after counter overflow. power-on reset and manual reset are available. ? interrupt generation in interval timer mode an interval timer interrupt is generated when the counter overflows. ? choice of eight counter input clocks eight clocks ( 1 to 1/4096) that are obtained by dividing the peripheral clock can be selected. rev. 1.0, 11/02, page 286 of 690 figures 10.1 shows a block diagram of the wdt. wtcsr standby control bus interface wtcnt divider clock selector clock standby mode peripheral clock standby cancellation reset control clock selection wdt overflow internal reset request interrupt control interrupt request wtcsr: wtcnt: legend watchdog timer control/status register watchdog timer counter figure 10.1 block diagram of wdt 10.2 register descriptions the wdt has the following two registers. refer to section 24, list of registers for the details of the addresses of these registers and the state of registers in each operating mode. ? watchdog timer counter (wtcnt) ? watchdog timer control/status register (wtcsr) 10.2.1 watchdog timer counter (wtcnt) the watchdog timer counter (wtcnt) is an 8-bit readable/writable register that increments on the selected clock. when an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval timer mode. the wtcnt counter is not initialized by an internal reset due to the wdt overflow. the wtcnt counter is initialized to h'00 only by a power-on reset using the resetp pin. use a word access to write to the wtcnt counter, with h'5a in the upper byte. use a byte access to read wtcnt. rev. 1.0, 11/02, page 287 of 690 note: wtcnt differs from other registers in that it is more difficult to write to. see section 10.2.3, notes on register access, for details. 10.2.2 watchdog timer control/status register (wtcsr) the watchdog timer control/status register (wtcsr) is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and enable bits. wtcsr holds its value in an internal reset due to the wdt overflow. wtcsr is initialized to h'00 only by a power-on reset using the resetp pin. when used to count the clock settling time for canceling a software standby, it retains its value after counter overflow. use a word access to write to the wtcsr counter, with h'a5 in the upper byte. use a byte access to read wtcsr. note: wtcsr differs from other registers in that it is more difficult to write to. see section 10.2.3, notes on register access, for details. rev. 1.0, 11/02, page 288 of 690 bit bit name initial value r/w description 7tme0r/wtimer enable starts and stops timer operation. clear this bit to 0 when using the wdt in software standby mode or when changing the clock frequency. 0: timer disabled: count-up stops and wtcnt value is retained 1: timer enabled 6wt/ it 0 r/w timer mode select selects whether to use the wdt as a watchdog timer or an interval timer. 0: use as interval timer 1: use as watchdog timer note: if wt/ it is modified when the wdt is running, the up-count may not be performed correctly. 5 rsts 0 r/w reset select selects the type of reset when wtcnt overflows in watchdog timer mode. in interval timer mode, this setting is ignored. 0: power-on reset 1: manual reset 4 wovf 0 r/w watchdog timer overflow indicates that wtcnt has overflowed in watchdog timer mode. this bit is not set in interval timer mode. 0: no overflow 1: wtcnt has overflowed in watchdog timer mode 3 iovf 0 r/w interval timer overflow indicates that wtcnt has overflowed in interval timer mode. this bit is not set in watchdog timer mode. 0: no overflow 1: wtcnt has overflowed in interval timer mode rev. 1.0, 11/02, page 289 of 690 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select the clock to be used for the wtcnt count from the eight types obtainable by dividing the peripheral clock. the overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (p ) is 15 mhz. 000 p (17 s) 001 p /4 (68 s) 010 p /16 (273 s) 011 p /32 (546 s) 100 p /64 (1.09 ms) 101 p /256 (4.36 ms) 110 p /1024 (17.48 ms) 111 p /4096 (69.91 ms) note: if bits cks2 to cks0 are modified when the wdt is running, the up-count may not be performed correctly. ensure that these bits are modified only when the wdt is not running. 10.2.3 notes on register access the watchdog timer counter (wtcnt) and watchdog timer control/status register (wtcsr) are more difficult to write to than other registers. the procedure for writing to these registers is given below. ? these registers must be written by a word transfer instruction. they cannot be written by a byte or longword transfer instruction. when writing to wtcnt, set the upper byte to h'5a and transfer the lower byte as the write data, as shown in figure 10.2. when writing to wtcsr, set the upper byte to h'a5 and transfer the lower byte as the write data. this transfer procedure writes the lower byte data to wtcnt or wtcsr. 15 8 7 0 h'5a write data wtcnt write 15 8 7 0 h'a5 write data wtcsr write figure 10.2 writing to wtcnt and wtcsr rev. 1.0, 11/02, page 290 of 690 10.3 operation 10.3.1 canceling software standbys the wdt is used to cancel software standby mode with an interrupt such as an nmi. the procedure when using an nmi interrupt is described below. (the wdt does not run when resets are used for canceling, so keep the resetp or resetm pin low until the clock stabilizes.) 1. before transitioning to software standby mode, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2 to cks0 bits in wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. move to software standby mode by executing a sleep instruction, after that clock stops. 4. the wdt starts counting by detecting the edge change of the nmi signal. 5. when the wdt count overflows, the cpg starts supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set. 6. since the wdt continues counting from h'00, clear the stby bit in the stbcr register to 0 in the interrupt processing program and this will stop the wdt. when the stby bit remains 1, the lsi again enters the software standby mode when the wdt has counted up to h'80. this software standby mode can be canceled by power-on resets. rev. 1.0, 11/02, page 291 of 690 10.3.2 changing frequency to change the frequency used by the pll, use the wdt. when changing the frequency only by switching the divider, do not use the wdt. 1. before changing the frequency, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2 to cks0 bits of wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. the divided clock set by cks2 to cks0 bits in wtcsr will be used for the base clock of p after the frequency is changed. 3. when the frequency control register (frqcr) is written, the processor stops temporarily. the wdt starts counting. 4. when the wdt count overflows, the cpg resumes supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set. 5. the counter stops at the values h'00. 6. before changing wtcnt after the execution of the frequency change instruction, always confirm that the value of wtcnt is h'00 by reading wtcnt. 10.3.3 using watchdog timer mode 1. set the wt/ it bit in wtcsr to 1, set the reset type in the rsts bit, set the type of count clock in the cks2 to cks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in watchdog timer mode. 3. while operating in watchdog timer mode, rewrite the counter periodically to h'00 to prevent the counter from overflowing. 4. when the counter overflows, the wdt sets the wovf flag in wtcsr to 1 and generates the reset signal specified by the rsts bit. the counter then resumes counting. 10.3.4 using interval timer mode when operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. this enables interrupts to be generated at set periods. 1. clear the wt/ it bit in wtcsr to 0, set the type of count clock in the cks2 to cks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in interval timer mode. 3. when the counter overflows, the wdt sets the iovf flag in wtcsr to 1 and an interval timer interrupt request is sent to the intc. the counter then resumes counting. rev. 1.0, 11/02, page 292 of 690 lpws300a_000020011000 rev. 1.0, 11/02, page 293 of 690 section 11 power-down modes this lsi has four types of the power-down modes: sleep mode, software standby mode, module standby function, and hardware standby mode. 11.1 features this lsi has the following power-down modes and function: 1. sleep mode 2. software standby mode 3. module standby function (cache, tlb, ubc, dmac, h-udi, and on-chip peripheral module) 4. hardware standby mode table 11.1 shows the transition conditions for entering the modes from the program execution state, as well as the cpu and peripheral module states in each mode and the procedures for canceling each mode. rev. 1.0, 11/02, page 294 of 690 table 11.1 states of power-down modes state mode transition conditions cpg cpu cpu register on-chip peripheral modules pins external memory canceling condition sleep mode execute sleep instruction with stby bit cleared to 0 in stbcr run halt held run * 3 refresh 1. interrupt 2. reset software standby mode execute sleep instruction with stby bit set to 1 in stbcr halt halt held halt * 1 * 3 self- refresh 1. interrupt 2. reset module standby function set mstp bit of stbcr, stbcr2, and stbcr3 to 1 run run held specified module halts * 2 refresh 1. clear mstp bit to 0 2. power-on reset hardware standby mode drive ca pin low halt halt held halt * 1 * 4 ? power-on reset notes: * 1 the rtc still runs if the start bit in rcr2 is set to 1 (see section 15, realtime clock (rtc)). * 2 depends on the on-chip peripheral module. * 3 refer to table a.1, i/o port states in each processing state, in appendix. * 4 hi-z except extal, xtal, extal2, xtal2, extal_usb, xtal_usb, status1, and status0. rev. 1.0, 11/02, page 295 of 690 11.2 input/output pins table 11.2 lists the pins used for the power-down modes. table 11.2 pin configuration pin name symbol i/o description processing state status1, status0 o operating state of the processor. hh: reset hl: sleep mode lh: standby mode ll: normal operation note: h means high level, and l means low level. power-on reset resetp i reset input signal. power-on reset occurs at low- level. manual reset resetm i reset input signal. manual reset occurs at low-level. hardware standby ca i normal operation at high-level and hardware standby mode is entered at low-level. 11.3 register descriptions there are following five registers used for the power-down modes. refer to section 24, list of registers, for the details of the addresses of these registers and the state of registers in each operating mode. ? standby control register (stbcr) ? standby control register 2 (stbcr2) ? standby control register 3 (stbcr3) rev. 1.0, 11/02, page 296 of 690 11.3.1 standby control register (stbcr) stbcr is an 8-bit readable/writable register that specifies the state of the power-down mode. bit bit name initial value r/w description 7 stby 0 r/w standby specifies transition to software standby mode. 0: executing sleep instruction puts chip into sleep mode 1: executing sleep instruction puts chip into software standby mode 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 stbxtl 0 r/w standby crystal specifies stop/start of the crystal oscillator in standby mode. 0: crystal oscillator stops in standby mode. 1: crystal oscillator continues operation in standby mode. 3 ? 0rreserved this bit is always read as 0. the write value should always be 0. 2 mstp2 0 r/w module stop 2 specifies halting the clock supply to the tmu when the mstp2 bit has been set to 1. 0: tmu runs 1: clock supply to tmu halted 1 mstp1 0 r/w module stop 1 specifies halting the clock supply to the rtc when the mstp1 bit has been set to 1. 0: rtc runs 1: clock supply to rtc halted 0 ? 0rreserved this bit is always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 297 of 690 11.3.2 standby control register 2 (stbcr2) stbcr2 is an 8-bit readable/writable register that controls the operation of modules in the power- down mode. bit bit name initial value r/w description 7 mstp10 0 r/w module stop bit 10 when the mstp10 bit is set to 1, the clock supply to the h-udi is halted. 0: h-udi runs 1: clock supply to h-udi is halted 6 mstp9 0 r/w module stop bit 9 when the mstp9 bit is set to 1, the clock supply to the ubc is halted. 0: ubc runs 1: clock supply to ubc is halted 5 mstp8 0 r/w module stop bit 8 when the mstp8 bit is set to 1, the clock supply to the dmac is halted. 0: dmac runs 1: clock supply to dmac is halted 4 ? 0rreserved this bit is always read as 0. the write value should always be 0. 3 mstp6 0 r/w module stop bit 6 when the mstp6 bit is set to 1, the clock supply to the tlb is halted. 0: tlb runs 1: clock supply to tlb is halted 2 mstp5 0 r/w module stop bit 5 when the mstp5 bit is set to 1, the clock supply to cache memory is halted. 0: cache memory runs 1: clock supply to cache memory is halted rev. 1.0, 11/02, page 298 of 690 bit bit name initial value r/w description 1, 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11.3.3 standby control register 3 (stbcr3) stbcr3 is an 8-bit readable/writable register that controls the operation of modules in the power- down mode. bit bit name initial value r/w description 7 mstp37 0 r/w module stop bit 37 when the mstp37 bit is set to 1, the clock supply to the usb is halted. 0: usb runs 1: clock supply to usb is halted 6 ? 0rreserved this bit is always read as 0. the write value should always be 0. 5 mstp35 0 r/w module stop bit 35 when the mstp35 bit is set to 1, the clock supply to the cmt is halted. 0: cmt runs 1: clock supply to cmt is halted 4 mstp34 0 r/w module stop bit 34 when the mstp34 bit is set to 1, the clock supply to the tpu is halted. 0: tpu runs 1: clock supply to tpu is halted 3 mstp33 0 r/w module stop bit 33 when the mstp33 bit is set to 1, the clock supply to the adc is halted. 0: adc runs 1: clock supply to adc is halted rev. 1.0, 11/02, page 299 of 690 bit bit name initial value r/w description 2 mstp32 0 r/w module stop bit 32 when the mstp32 bit is set to 1, the clock supply to the irda is halted. 0: irda runs 1: clock supply to irda is halted 1 mstp31 0 r/w module stop bit 31 when the mstp31 bit is set to 1, the clock supply to the scif2 is halted. 0: scif2 runs 1: clock supply to scif2 is halted 0 mstp30 0 r/w module stop bit 30 when the mstp30 bit is set to 1, the clock supply to the scif0 is halted. 0: scif0 runs 1: clock supply to scif0 is halted 11.4 sleep mode 11.4.1 transition to sleep mode executing the sleep instruction when the stby bit in stbcr is 0 causes a transition from the program execution state to sleep mode. although the cpu halts immediately after executing the sleep instruction, the contents of its internal registers remain unchanged. the on-chip peripheral modules continue to run in sleep mode and the clock continues to be output to the ckio pin. in sleep mode, the status1 pin is set high and the status0 pin low. 11.4.2 canceling sleep mode sleep mode is canceled by an interrupt (nmi, irq, irl, pint, and on-chip peripheral module) or reset. interrupts are accepted in sleep mode even when the bl bit in sr is 1. if necessary, save spc and ssr to the stack before executing the sleep instruction. canceling with an interrupt: when an nmi, irq, irl, pint, or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception processing is executed. a code indicating the interrupt source is set in intevt and intevt2. canceling with a reset: sleep mode is canceled by a power-on reset or a manual reset. rev. 1.0, 11/02, page 300 of 690 11.5 software standby mode 11.5.1 transition to software standby mode the lsi switches from a program execution state to software standby mode by executing the sleep instruction when the stby bit is 1 in stbcr. in software sta ndby mode, not only the cpu but also the clock and on-chip peripheral modules halt. the clock output from the ckio pin also halts. the contents of the cpu and cache registers remain unchanged. some registers of on-chip peripheral modules are, however, initialized. for more details on the states of on-chip peripheral modules registers in software standby mode, refer to section 24.3, register states in each operating mode. the procedure for moving to software standby mode is as follows: 1. clear the tme bit in the wdt?s timer control register (wtcsr) to 0 to stop the wdt. 2. clear the wdt?s timer counter (wtcnt) to 0 and set the cks2 to cks0 bits in wtcsr to appropriate values to secure the specified oscillation settling time. 3. after the stby bit in stbcr is set to 1, a sleep instruction is executed. 4. software standby mode is entered and the clocks within the lsi are halted. the status1 pin output goes low and the status0 pin output goes high. 11.5.2 canceling software standby mode software standby mode is canceled by an interrupt (nmi, irq, irl, pint, or rtc) or a reset. canceling with an interrupt: the on-chip wdt can be used for hot starts. when the chip detects an nmi, irq* 1 , irl* 1 , pint* 1 , or rtc* 1 interrupt, the clock will be supplied to the entire chip and software standby mode canceled after the time set in the wdt?s timer control/status register has elapsed. the status1 and status0 pins both go low. interrupt exception handling then begins and a code indicating the interrupt source is set in intevt and intevt2. after branching to the interrupt handling routine occurs, clear the stby bit in stbcr. wtcnt stops automatically. if the stby bit is not cleared, wtcnt continues operation and transits to software standby mode* 2 when it reaches h'80. this function prevents data from being broken in case of a voltage rise when the power supply is unstable. at this time, a manual reset is not accepted until the stby bit is cleared to 0. interrupts are accepted in software standby mode even when the bl bit in sr is 1. if necessary, save spc and ssr to the stack before executing the sleep instruction. immediately after an interrupt is detected, the phase of the clock output of the ckio pin may be unstable, until software standby mode is cancelled. rev. 1.0, 11/02, page 301 of 690 notes: 1. only when the rtc is being used can standby mode be canceled using irq, irl, pint, or rtc. 2. use a power-on reset to cancel software standby mode. wtcnt value h'ff h'80 time interrupt request wdt overflow and branch to interrupt handling routine crystal oscillator settling time and pll synchronization time clear the stby bit in stbcr before wtcnt reaches h'80. when the stby bit in stbcr is cleared, wtcnt halts automatically. figure 11.1 canceling standby mode with stby bit in stbcr canceling with a reset: software standby mode is canceled by a reset (power-on or manual). keep the resetp or resetm pins low until the clock oscillation settles. the internal clock will continue to be output to the ckio pin. 11.6 module standby function 11.6.1 transition to module standby function setting the standby control register mstp bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. this function can be used to reduce the power consumption in normal mode. before making a transition to module standby state, be sure to disable the relevant module. in module standby state, the functions of the external pins of the on-chip peripheral modules change depending on the on-chip peripheral module and port settings. with a few exceptions, all registers hold their values prior to halt. rev. 1.0, 11/02, page 302 of 690 11.6.2 canceling module standby function the module standby function can be canceled by clearing the mstp bits to 0 or by a power-on reset. when canceling the module standby function by clearing the corresponding mstp bit, be sure to read the relevant mstp bit to confirm that it has been cleared to 0. 11.7 hardware standby mode 11.7.1 transition to hardware standby mode the lsi enters hardware standby mode by driving the ca pin low. in hardware standby mode, as the same as software standby mode entered by executing the sleep instruction, all modules halt except ones operated by the rtc clock. even in hardware standby mode, supply power to all power supply pins including the rtc power supply pins. as differing from software standby mode, an interrupt or manual reset cannot be accepted in hardware standby mode. when the ca pin is driven low, the lsi enters hardware standby mode in the following procedure depending on the state of cpg. during software standby mode: the lsi enters the hardware standby state with the clock halted. an interrupt or manual reset cannot be accepted. during wdt operation for canceling software standby mode by an interrupt: the cpu restarts the operation after software standby mode is canceled. then, the lsi enters hardware standby mode. during sleep mode: the cpu restarts the operation after sleep mode is canceled. then, the lsi enters hardware standby mode. in hardware standby mode, the ca pin must be held low. 11.7.2 canceling hardware standby mode the hardware standby function can be canceled only by the power-on reset. when the ca pin is driven high while the resetp pin is low, the clock starts oscillating. make sure to hold the resetp pin low until the oscillation stabilizes. then, drive the resetp pin high to start the power-on resetting by the cpu. the operation is not guaranteed when an interrupt or manual reset is input. rev. 1.0, 11/02, page 303 of 690 11.8 timing of status pin changes the timing of the status0 and status1 pin changes is shown in figures 11.2 to 11.9. in case of a reset: a. power-on reset ckio status normal * 2 normal * 2 reset * 1 pll settling time 0 to 5 bcyc * 3 0 to 30 bcyc * 3 notes: * 1. reset: hh (status1 high, status0 high) * 2. normal: ll (status1 low, status0 low) * 3. bcyc: bus clock cycle figure 11.2 power-on reset status output b. manual reset ckio status normal * 3 normal * 3 reset * 2 0 bcyc or more * 1,4 0 to 30 bcyc * 4 during manual reset, status becomes hh (reset) and the internal reset begins after waiting for the executing bus cycle to end. reset: hh (status1 high, status0 high) normal: ll (status1 low, status0 low) bcyc: bus clock cycle notes: * 1 * 2 * 3 * 4 figure 11.3 manual reset status output rev. 1.0, 11/02, page 304 of 690 in case of canceling software standby: a. canceling software standby by interrupt ckio status normal * 2 normal * 2 wdt count oscillation stops standby * 1 interrupt request wdt overflow notes: * 1 standby: lh (status1 low, status0 high) * 2 normal: ll (status1 low, status0 low) figure 11.4 canceling software standby by interrupt status output b. canceling software standby by power-on reset ckio status normal * 5 normal * 5 oscillation stops standby * 4 * 2 0 to 10 bcyc * 6 0 to 30 bcyc * 6 reset reset * 3 * 1 * 1 when software standby mode is cleared with a power-on reset, the wdt does not count. keep low during the pll?s oscillation settling time. * 2 undefined * 3 reset: hh (status1 high, status0 high) * 4 standby: lh (status1 low, status0 high) * 5 normal: ll (status1 low, status0 low) * 6 bcyc: bus clock cycle notes: figure 11.5 canceling software standby by power-on reset status output rev. 1.0, 11/02, page 305 of 690 c. canceling software standby by manual reset ckio status normal * 4 normal * 4 oscillation stops standby * 3 reset * 2 0 to 20 bcyc * 5 reset * 1 notes: * 1 when software standby mode is cleared with a manual reset, the wdt does not count. keep low during the pll ? s oscillation settling time. * 2 reset: hh (status1 high, status0 high) * 3 standby: lh (status1 low, status0 high) * 4 normal: ll (status1 low, status0 low) * 5 bcyc: bus clock cycle figure 11.6 canceling software standby by manual reset status output in case of canceling sleep: a. canceling sleep to interrupt ckio status normal * 2 normal * 2 sleep * 1 interrupt request notes: * 1 sleep: hl (status1 high, status0 low) * 2 normal: ll (status1 low, status0 low) figure 11.7 canceling sleep by interrupt status output rev. 1.0, 11/02, page 306 of 690 b. canceling sleep by power-on reset ckio status normal * 5 normal * 5 sleep * 4 0 to 10 bcyc * 6 0 to 30 bcyc * 6 reset reset * 3 * 2 * 1 * 1 when the pll1 ? s multiplication ratio is changed by a power-on reset, keep low during the pll ? s oscillation settling time. * 2 undefined * 3 reset: hh (status1 high, status0 high) * 4 sleep: hl (status1 high, status0 low) * 5 normal: ll (status1 low, status0 low) * 6 bcyc: bus clock cycle notes: figure 11.8 canceling sleep by power-on reset status output c. canceling sleep by manual reset ckio 0 to 80 bcyc * 5 0 to 30 bcyc * 5 reset status normal * 4 normal * 4 sleep * 3 reset * 2 * 1 notes: * 1 keep low until status becomes reset. * 2 reset: hh (status1 high, status0 high) * 3 sleep: hl (status1 high, status0 low) * 4 normal: ll (status1 low, status0 low) * 5 bcyc: bus clock cycle figure 11.9 canceling sleep by manual reset status output in case of hardware standby: figures 11.10 and 11.11 show examples of pin timing in hardware standby mode. the ca pin is sampled using extal2 (32.768 khz), and a hardware standby request is only detected when the pin is low for two consecutive clock cycles. the ca pin must be held low while the chip is in hardware standby mode. clock oscillation starts when the ca pin is driven high after the resetp pin is driven low. rev. 1.0, 11/02, page 307 of 690 a. normal operation to hardware standby normal * 3 normal * 3 status ca ckio standby * 2 reset * 1 undefined 2 rcyc or more * 5 0 ? 10bcyc * 4 0 ? 30bcyc notes: * 1 reset: hh (status1 high, status0 high) * 2 standby: lh (status1 low, status0 high) * 3 normal: ll (status1 low, status0 low) * 4 bcyc: bus clock cycle * 5 rcyc: extal2 (32.768 khz) cycle figure 11.10 hardware standby mode (when ca goes low in normal operation) b. canceling software standby (during wdt operation) to hardware standby normal * 3 status ca ckio standby * 2 reset * 1 undefined 2 rcyc or more * 5 0 ? 10 bcyc * 4 standby wdt operation notes: * 1 reset: hh (status1 high, status0 high) * 2 standby: lh (status1 low, status0 high) * 3 normal: ll (status1 low, status0 low) * 4 bcyc: bus clock cycle * 5 rcyc: extal2 (32.768 khz) cycle figure 11.11 hardware standby mode timing (when ca goes low during wdt operation while standby mode is canceled) rev. 1.0, 11/02, page 308 of 690 timtmu2a_000020020100 rev. 1.0, 11/02, page 309 of 690 section 12 timer unit (tmu) this lsi includes a three-channel 32-bit timer unit (tmu). 12.1 features ? each channel is provided with an auto-reload 32-bit down counter ? all channels are provided with 32-bit constant registers and 32-bit down counters for an auto- reload function that can be read or written to at any time ? all channels generate interrupt requests when the 32-bit down counter underflows (h'00000000 h'ffffffff) ? only channel 2 is provided with an input capture function ? allows selection among five counter input clocks: external clock (tclk), p /4, p /16, p /64, and p /256 rev. 1.0, 11/02, page 310 of 690 figure 12.1 shows a block diagram of the tmu. prescaler tstr tcr_0 tcnt_0 module bus internal bus tcor_0 tcr_1 tcnt_1 tcor_1 counter controller tclk p tuni0 bus interface ch. 0 interrupt controller interrupt controller interrupt controller counter controller counter controller tuni1 tuni2 ticpi2 tcr_2 tcpr_2 tcnt_2 tcor_2 tmu ch. 1 ch. 2 clock controller tstr: tcr_n: timer start register tcnt_n: tcor_n: tcpr_2: 32-bit timer counter 32-bit timer constant register 32-bit input capture register timer control register (n: 0, 1, 2) legend: figure 12.1 tmu block diagram rev. 1.0, 11/02, page 311 of 690 12.2 input/output pin table 12.1 shows the pin configuration of the tmu. table 12.1 pin configuration name abbreviation i/o description clock input tclk i external clock input pin/input capture control input pin 12.3 register descriptions the tmu has the following registers. refer to section 24, list of registers, for more details of the addresses of these registers and state of these registers in each processing state. for the register name for each channel, tcor for channel 0 is noted as tcor_0. 1. common ? timer start register (tstr) 2. channel 0 ? timer constant register_0 (tcor_0) ? timer counter_0 (tcnt_0) ? timer control register_0 (tcr_0) 3. channel 1 ? timer constant register_1 (tcor_1) ? timer counter_1 (tcnt_1) ? timer control register_1 (tcr_1) 4. channel 2 ? timer constant register_2 (tcor_2) ? timer counter_2 (tcnt_2) ? timer control register_2 (tcr_2) ? input capture register_2 (tcpr_2) rev. 1.0, 11/02, page 312 of 690 12.3.1 timer start register (tstr) tstr is an 8-bit readable/writable register that selects whether to run or halt the timer counters (tcnt). tstr is initialized by satisfying the initialization conditions shown in section 24, list of registers, changing the multiplication ratio of pll1, or setting the mstp2 bit in stbcr to 1. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 str2 0 r/w counter start 2 selects whether to run or halt timer counter 2 (tcnt_2). 0: tcnt_2 count halted 1: tcnt_2 counts 1 str1 0 r/w counter start 1 selects whether to run or halt timer counter 1 (tcnt_1). 0: tcnt_1 count halted 1: tcnt_1 counts 0 str0 0 r/w counter start 0 selects whether to run or halt timer counter 0 (tcnt_0). 0: tcnt_0 count halted 1: tcnt_0 counts rev. 1.0, 11/02, page 313 of 690 12.3.2 timer control registers (tcr) tcr are 16-bit readable/writable registers that control the timer counters (tcnt) and interrupts. tcr control the issuance of interrupts when the flag indicating timer counter (tcnt) underflow has been set to 1, and also carry out counter clock selection. when the external clock has been selected, they also select its edge. only tcr_2 controls the input capture function and the issuance of interrupts during input capture. tcr_0 and tcr_1: bit bit name initial value r/w description 15 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 unf 0 r/(w) * underflow flag status flag that indicates occurrence of a tcnt underflow. 0: tcnt has not underflowed [clearing condition] 0 is written to unf 1: tcnt has underflowed [setting condition] tcnt underflows 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 unie 0 r/w underflow interrupt control controls enabling of interrupt generation when the status flag (unf) indicating tcnt underflow has been set to 1. 0: interrupt due to unf (tuni) is disabled 1: interrupt due to unf (tuni) is enabled rev. 1.0, 11/02, page 314 of 690 bit bit name initial value r/w description 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge select an input edge of the external clock when the external clock is selected. 00: count on rising edge 01: count on falling edge 1x: count on both rising and falling edges note: x: don?t care 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w timer prescaler select the tcnt count clock. 000: count on p /4 001: count on p /16 010: count on p /64 011: count on p /256 100: setting prohibited 101: count on tclk pin input 110: setting prohibited 111: setting prohibited note: * only 0 can be written for clearing the flags. if 1 is written to this bit, the prior value is retained. rev. 1.0, 11/02, page 315 of 690 tcr_2: bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 icpf 0 r/(w) * input capture interrupt flag a function of channel 2 only: the flag is set when input capture is requested via the tclk pin. 0: no input capture request has been issued. [clearing condition] 0 is written to icpf 1: input capture has been requested via the tclk pin. [setting condition] when an input capture is requested via the tclk pin 8 unf 0 r/(w) * underflow flag status flag that indicates occurrence of a tcnt_2 underflow. 0: tcnt_2 has not underflowed [clearing condition] 0 is written to unf 1: tcnt_2 has underflowed [setting condition] tcnt_2 underflows rev. 1.0, 11/02, page 316 of 690 bit bit name initial value r/w description 7 6 icpe1 icpe0 0 0 r/w r/w input capture control a function of channel 2 only: determines whether the input capture function can be used, and when used, whether or not to enable interrupts. use the ckeg1 and ckeg0 bits to designate use of either the rising or falling edge of the tclk pin to set the value of tcnt_2 in tcpr_2. 00: input capture function is not used. 01: setting prohibited 10: input capture function is used. interrupt due to icpf (ticpi2) are not enabled. 11: input capture function is used. interrupt due to icpf (ticpi2) are enabled. 5 unie 0 r/w underflow interrupt control controls enabling of interrupt generation when the status flag (unf) indicating tcnt_2 underflow has been set to 1. 0: interrupt due to unf (tuni2) is not enabled. 1: interrupt due to unf (tuni2) is enabled. 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge select an input edge of the external clock when the external clock is selected, or when the input capture function is used. 00: count/capture register set on rising edge 01: count/capture register set on falling edge 1x: count/capture register set on both rising and falling edge note: x: don?t care. rev. 1.0, 11/02, page 317 of 690 bit bit name initial value r/w description 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w timer prescaler select the tcnt_2 count clock. 000: count on p /4 001: count on p / 16 010: count on p /64 011: count on p /256 100: setting prohibited 101: count on tclk pin input 110: setting prohibited 111: setting prohibited note: * only 0 can be written for clearing the flags. if 1 is written to this bit, the prior value is retained. 12.3.3 timer constant registers (tcor) tcor set the value to be set in tcnt when tcnt underflows. tcor are 32-bit readable/writable registers. their initial value is h'ffffffff. 12.3.4 timer counters (tcnt) tcnt counts down upon input of a clock. the clock input is selected using the tpsc2 to tpsc0 bits in the timer control register (tcr). when a tcnt countdown results in an underflow (h'00000000 h'ffffffff), the underflow flag (unf) in the timer control register (tcr) of the relevant channel is set. the tcor value is simultaneously set in tcnt itself and the countdown continues from that value. initial value of tcnt is h'ffffffff. 12.3.5 input capture register_2 (tcpr_2) tcpr_2 is a read-only 32-bit register used for the input capture function built only into timer 2. the tcpr_2 setting conditions due to the tclk pin are controlled by the input capture function bits (icpe1/icpe0 and ckeg1/ckeg0) in tcr_2. when a tcpr_2 setting indication due to the tclk pin occurs, the value of tcnt_2 is copied into tcpr_2. initial value of tcpr_2 is undefined. rev. 1.0, 11/02, page 318 of 690 12.4 operation each of the three channels has a 32-bit timer counter (tcnt) and a 32-bit timer constant register (tcor). the tcnt counts down. the auto-reload function enables synchronized counting and counting by external events. channel 2 has an input capture function. 12.4.1 counter operation when the str0 to str2 bits in the timer start register (tstr) are set to 1, the corresponding timer counter (tcnt) starts counting. when a tcnt underflows, the unf flag of the corresponding timer control register (tcr) is set. at this time, if the unie bit in tcr is 1, an interrupt request is sent to the cpu. also at this time, the value is copied from tcor to tcnt and the down-count operation is continued. count operation setting procedure: an example of the procedure for setting the count operation is shown in figure 12.2. select operation select counter clock set underflow interrupt generation set timer constant register initialize timer counter start counting (1) (2) (4) (5) (6) set input capture interrupt generation when using input capture function (3) note: when an interrupt has been generated, clear the flag in the interrupt handler that caused it. if interrupts are enabled without clearing the flag, another interrupt will be generated. select the counter clock with the tpsc0-tpsc2 bits in the timer control register. if the external clock is selected, select its edge with the ckeg1 and ckeg0 bits in the timer control register. use the unie bit in the timer control register to set whether to generate an interrupt when timer counter underflows. when using the input capture function, set the icpe bits in the timer control register, including the choice of whether or not to use the interrupt function (channel 2 only). set a value in the timer constant register (the cycle is the set value plus 1). set the initial value in the timer counter. set the str bit in the timer start register to 1 to start operation. (1) (2) (3) (4) (5) (6) figure 12.2 setting count operation rev. 1.0, 11/02, page 319 of 690 auto-reload count operation: figure 12.3 shows the tcnt auto-reload operation. tcnt value tcor h'00000000 str0?str2 unf tcor value set to tcnt during underflow time figure 12.3 auto-reload count operation tcnt count timing: 1. internal clock operation: set the tpsc2 to tpsc0 bits in tcr to select whether one of the four internal clocks created by dividing the peripheral module clock is used (p /4, p /16, p /64, p /256). figure 12.4 shows the timing. p internal clock timer counter input clock tcnt n + 1 n n ? 1 figure 12.4 count timing when internal clock is operating rev. 1.0, 11/02, page 320 of 690 2. external clock operation: set the tpsc2 to tpsc0 bits in tcr to select the external clock (tclk) as the timer clock. use the ckeg1 and ckeg0 bits in tcr to select the detection edge. rise, fall or both may be selected. the pulse width of the external clock must be at least 2 peripheral module clock cycles (p ) for single edges or 3 peripheral module clock cycles (p ) for both edges. a shorter pulse width will result in incorrect operation. figure 12.5 shows the timing for both-edge detection. p external clock input (tclk) tcnt input clock tcnt n + 1 n n ? 1 figure 12.5 count timing when external clock is operating (both edges detected) 12.4.2 input capture function channel 2 has an input capture function. when using the input capture function, set the timer operation clock to internal clock with the tpsc2 to tpsc0 bits in tcr_2. also, specifies use of the input capture function and whether to generate interrupts on using it with the icpe1 to icpe0 bits in tcr_2, and specifies the use of either the rising or falling edge of the tclk pin to set the tcnt_2 value into tcpr_2 with the ckeg1 to ckeg0 bits in tcr_2. the input capture function cannot be used in standby mode. figure 12.6 shows the timing at the rising edge of the tclk pin input. tcnt_2 value tcor_2 h'00000000 tclk tcpr_2 set tcnt_2 value ticpi2 tcor_2 value set to tcnt_2 during underflow time figure 12.6 operation timing when using input capture function (using tclk rising edge) rev. 1.0, 11/02, page 321 of 690 12.5 interrupts there are two sources of tmu interrupts: underflow interrupts (tuni) and interrupts when using the input capture function (ticpi2). 12.5.1 status flag set timing the unf bit is set to 1 when the tcnt underflows. figure 12.7 shows the timing. p tcnt underflow signal unf tuni tcor value h'00000000 figure 12.7 unf set timing 12.5.2 status flag clear timing the status flag can be cleared by writing 0 from the cpu. figure 12.8 shows the timing. p peripheral address bus unf, icpf tcr address t1 t2 tcr write cycle t3 figure 12.8 status flag clear timing rev. 1.0, 11/02, page 322 of 690 12.5.3 interrupt sources and priorities the tmu generates underflow interrupts for each channel. when the interrupt request flag and interrupt enable bit are both set to 1, the relevant interrupt is requested. codes are set in the interrupt event register (intevt and intevt2) for these interrupts and interrupt processing must be executed according to the codes. the relative priorities of channels can be changed using the interrupt controller. for details, see section 5, exception handling, and section 6, interrupt controller (intc). table 12.2 lists tmu interrupt sources. table 12.2 tmu interrupt sources channel interrupt source description priority 0 tuni0 underflow interrupt 0 high 1 tuni1 underflow interrupt 1 tuni2 underflow interrupt 2 2 ticpi2 input capture interrupt 2 low 12.6 usage notes 12.6.1 writing to registers synchronization processing is not performed for timer counting during register writes. when writing to registers, always clear the appropriate start bits for the channel (str2 to str0) in the timer start register (tstr) to halt timer counting. 12.6.2 reading registers synchronization processing is performed for timer counting during register reads. when timer counting and register read processing are performed simultaneously, the register value before tcnt counting down is read. timcmt2a_000020020100 rev. 1.0, 11/02, page 323 of 690 section 13 compare match timer (cmt) the dmac has an on-chip compare match timer (cmt) to generate a dma transfer request. the cmt has 16-bit counter. figure 13.1 shows a cmt block diagram. 13.1 features ? four types of counter input clock can be selected. one of four internal clocks (p /4, p /8, p /16, p /64) can be selected. ? generates a dma transfer request when compare match occurs. (the cpu interrupt is not supported.) ? when the cmt is not used, the operation can be halted by stopping the clock supply to the cmt so that the power consumption can be reduced. internal bus bus interface control circuit clock selection cmstr cmcsr cmcor comparator cmcnt module bus cmt p /4 p /8 p /16 p /64 cmstr: cmcsr: cmcor: cmcnt: compare match timer start register compare match timer control/status register compare match constant register compare match counter [legend] figure 13.1 cmt block diagram rev. 1.0, 11/02, page 324 of 690 13.2 register descriptions the cmt has the following registers. refer to section 24, list of registers, for more detail of the addresses and access size. ? compare match timer start register (cmstr) ? compare match timer control/status register (cmcsr) ? compare match counter (cmcnt) ? compare match constant register (cmcor) 13.2.1 compare match timer start register (cmstr) cmstr is a 16-bit register that selects whether to operate or halt the counter (cmcnt). bit bit name initial value r/w description 15 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 str 0 r/w count start selects whether to operate or halt the compare match counter. 0: cmcnt count operation halted 1: cmcnt count operation rev. 1.0, 11/02, page 325 of 690 13.2.2 compare match timer control/status register (cmcsr) cmcsr is a 16-bit register that indicates the occurrence of compare matches, and sets the enable/disable of dma transfer requests and the clock used for incrementation. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7cmf0 r/(w) * compare match flag indicates whether cmcnt and cmcor values have matched or not. 0: cmcnt and cmcor values have not matched [clearing condition] write 0 to cmf after reading cmf = 1 1: cmcnt and cmcor values have matched 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 cmr 0 r/w compare match request 0: disables a dma transfer request 1: enables a dma transfer request 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 cks1 cks0 0 0 r/w r/w clock select select the clock input to cmcnt from among the four internal clocks obtained by dividing the peripheral clock (p ). when the str bit in cmstr is set to 1, cmcnt begins incrementing with the clock selected by the cks1 and cks0 bits. 00: p /4 01: p /8 10: p /16 11: p /64 note: * only 0 can be written for clearing the flags. rev. 1.0, 11/02, page 326 of 690 13.2.3 compare match counter (cmcnt) cmcnt is a 16-bit register used as an up-counter. when an internal clock is selected with the cks1 and cks0 bits in cmcsr and the str bit in cmstr is set to 1, cmcnt begins incrementing with the selected clock. when the cmcnt value matches that of cmcor, cmcnt is cleared to h'0000 and the cmf flag in cmcsr is set to 1. the initial value of cmcnt is h'0000. 13.2.4 compare match constant register (cmcor) cmcor is a 16-bit register that sets the compare match period with cmcnt. the initial value of cmcor is h'ffff. 13.3 operation 13.3.1 period count operation when an internal clock is selected with the cks1 and cks0 bits in cmcsr and the str bit in cmstr is set to 1, cmcnt begins incrementing with the selected clock. when the cmcnt value matches that of cmcor, cmcnt is cleared to h'0000 and the cmf flag in cmcsr is set to 1. cmcnt begins counting up again from h'0000. figure 13.2 shows the compare match counter operation. counter cleared by cmcor compare match cmcnt value cmcor h'0000 time figure 13.2 counter operation rev. 1.0, 11/02, page 327 of 690 13.3.2 cmcnt count timing one of four clocks (p /4, p /8, p /16, p /64) obtained by dividing the peripheral clock (p ) can be selected by the cks1 and cks0 bits in cmcsr. figure 13.3 shows the timing. n+1 internal clock cmcnt input clock cmcnt n-1 n p figure 13.3 count timing 13.3.3 compare match flag set timing the cmf bit in cmcsr is set to 1 by the compare match signal generated when cmcor and cmcnt match. the compare match signal is generated upon the final state of the match (timing at which the cmcnt matching count value is updated to h'0000). consequently, after cmcor and cmcnt match, a compare match signal will not be generated until a cmcnt clock is input. figure 13.4 shows the cmf bit set timing. cmcor cmcnt input clock compare match signal cmf cmi cmcnt n n 0 p figure 13.4 cmf set timing rev. 1.0, 11/02, page 328 of 690 timtpu8a_000020020100 rev. 1.0, 11/02, page 329 of 690 section 14 16-bit timer pulse unit (tpu) this lsi has an on-chip 16-bit timer pulse unit (tpu) that comprises four 16-bit timer channels. 14.1 features ? maximum 4-pulse output a total of 16 timer general registers (tgra to tgrd 4 ch.) are provided (four each for channels). tgra can be set as an output compare register. tgrb, tgrc, and tgrd for each channel can also be used as timer counter clearing registers. tgrc and tgrd can also be used as buffer registers. ? selection of four counter input clocks for channels 0 to 3 ? the following operations can be set for each channel: waveform output at compare match: selection of 0, 1, or toggle output counter clear operation: counter clearing possible by compare match pwm mode: any pwm output duty cycle can be set maximum of 4-phase pwm output possible ? buffer operation settable for each channel automatic rewriting of output compare register possible ? an interrupt request for each channel compare match and overflow interrupt requests can be enabled or disabled for each source independently rev. 1.0, 11/02, page 330 of 690 table 14.1 lists the functions of the tpu. table 14.1 tpu functions item channel 0 channel 1 channel 2 channel 3 count clock p /1 p /4 p /16 p /64 p /1 p /4 p /16 p /64 p /1 p /4 p /16 p /64 p /1 p /4 p /16 p /64 general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b tgr3a tgr3b general registers/ buffer registers tgr0c tgr0d tgr1c tgr1d tgr2c tgr2d tgr3c tgr3d output pins to0 to1 to2 to3 counter clear function tgr compare match tgr compare match tgr compare match tgr compare match 0 output 1 output compare match output toggle output pwm mode buffer operation interrupt sources 5 sources ? compare match ? overflow 5 sources ? compare match ? overflow 5 sources ? compare match ? overflow 5 sources ? compare match ? overflow legend : possible ?: not possible rev. 1.0, 11/02, page 331 of 690 divider clock selection edge selection comparator buffer counter up output control channel 0 channel 2 channel 1 same as channel 0 channel 3 same as channel 2 clear tgra p to0 to2 to1 to3 p /1 p /4 p /16 p /64 tgrb tgrc tgrd selector clock selection edge selection comparator buffer counter up output control clear tgra tgrb tgrc tgrd selector figure 14.1 block diagram of tpu rev. 1.0, 11/02, page 332 of 690 14.2 input/output pins table 14.2 shows the pin configuration of the tpu. table 14.2 pin configuration channel name symbol i/o function 0 output compare match 0 to0 o tgr0a output compare output/pwm output pin 1 output compare match 1 to1 o tgr1a output compare output/pwm output pin 2 output compare match 2 to2 o tgr2a output compare output/pwm output pin 3 output compare match 3 to3 o tgr3a output compare output/pwm output pin 14.3 register descriptions the tpu has the following registers. refer to section 24, list of registers, for more details of the addresses of these registers and state of these registers in each processing state. for the register name for each channel, tcr for channel 0 is noted as tcr_0. 1. channel 0 ? timer control register_0 (tcr_0) ? timer mode register_0 (tmdr_0) ? timer i/o control register_0 (tior_0) ? timer interrupt enable register_0 (tier_0) ? timer status register_0 (tsr_0) ? timer counter_0 (tcnt_0) ? timer general register a_0 (tgra_0) ? timer general register b_0 (tgrb_0) ? timer general register c_0 (tgrc_0) ? timer general register d_0 (tgrd_0) 2. channel 1 ? timer control register_1 (tcr_1) ? timer mode register_1 (tmdr_1) ? timer i/o control register_1 (tior_1) ? timer interrupt enable register_1 (tier_1) ? timer status register_1 (tsr_1) rev. 1.0, 11/02, page 333 of 690 ? timer counter_1 (tcnt_1) ? timer general register a_1 (tgra_1) ? timer general register b_1 (tgrb_1) ? timer general register c_1 (tgrc_1) ? timer general register d_1 (tgrd_1) 3. channel 2 ? timer control register_2 (tcr_2) ? timer mode register_2 (tmdr_2) ? timer i/o control register_2 (tior_2) ? timer interrupt enable register_2 (tier_2) ? timer status register 2 (tsr_2) ? timer counter_2 (tcnt_2) ? timer general register a_2 (tgra_2) ? timer general register b_2 (tgrb_2) ? timer general register c_2 (tgrc_2) ? timer general register d_2 (tgrd_2) 4. channel 3 ? timer control register_3 (tcr_3) ? timer mode register_3 (tmdr_3) ? timer i/o control register_3 (tior_3) ? timer interrupt enable register_3 (tier_3) ? timer status register_3 (tsr_3) ? timer counter_3 (tcnt_3) ? timer general register a_3 (tgra_3) ? timer general register b_3 (tgrb_3) ? timer general register c_3 (tgrc_3) ? timer general register d_3 (tgrd_3) 5. common ? timer start register (tstr) rev. 1.0, 11/02, page 334 of 690 14.3.1 timer control registers (tcr) tcr are 16-bit registers that control the tcnt channels. tcr register settings should be made only when tcnt operation is stopped. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear select the tcnt clearing source. 000: tcnt clearing disabled 001: tcnt cleared by tgra compare match 010: tcnt cleared by tgrb compare match 011: setting prohibited 100: tcnt clearing disabled 101: tcnt cleared by tgrc compare match 110: tcnt cleared by tgrd compare match 111: setting prohibited 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge select the input clock edge. when the internal clock is counted using both edges, the input clock period is halved (e.g. p /4 both edges = p /2 rising edge). 00: count at rising edge 01: count at falling edge 1x: count at both edges * [legend] x: don?t care note: * internal-clock edge selection is valid when the input clock is p /4 or slower. if the input clock is p /1, this operation is not performed. 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w timer prescaler select the tcnt count clock. the clock source can be selected independently for each channel. table 14.3 shows the clock sources that can be set for each channel. for more information on count clock selection, see table 14.4, tpsc2 to tpsc0 (1) to (4). rev. 1.0, 11/02, page 335 of 690 table 14.3 tpu clock sources internal clock channel p /1 p /4 p /16 p /64 0 1 2 3 [legend] : setting blank: no setting table 14.4 tpsc2 to tpsc0 (1) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 x x setting prohibited note: x: don?t care table 14.4 tpsc2 to tpsc0 (2) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 1 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 x x setting prohibited note: x: don?t care rev. 1.0, 11/02, page 336 of 690 table 14.4 tpsc2 to tpsc0 (3) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 2 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 x x setting prohibited note: x: don?t care table 14.4 tpsc2 to tpsc0 (4) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 3 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 x x setting prohibited note: x: don?t care rev. 1.0, 11/02, page 337 of 690 14.3.2 timer mode registers (tmdr) tmdr are 16-bit readable/writable registers that are used to set the operating mode for each channel. tmdr register settings should be made only when tcnt operation is stopped. bit bit name initial value r/w description 15 to 7 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 6 bfwt 0 r/w buffer write timing specifies tgra and tgrb update timing when tgrc and tgrd are used as a compare match buffer. when tgrc and tgrd are not used as a compare match buffer register, this bit is ignored. 0: tgra and tgrb are rewritten at compare match of each register. 1: tgra and tgrb are rewritten in counter clearing. 5 bfb 0 r/w buffer operation b specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. 0: tgrb operates normally 1: tgrb and tgrd used together for buffer operation 4 bfa 0 r/w buffer operation a specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. 0: tgra operates normally 1: tgra and tgrc used together for buffer operation 3 ? 0rreserved this bit is always read as 0 and cannot be modified. 2 1 0 md2 md1 md0 0 0 0 r/w r/w r/w timer operating mode set the timer-operating mode. 000: normal operation 001: setting prohibited 010: pwm mode 011: setting prohibited 1xx: setting prohibited note: x: don?t care rev. 1.0, 11/02, page 338 of 690 14.3.3 timer i/o control registers (tior) tior are 16-bit registers that control the to pin. tior register settings should be made only when tcnt operation is stopped. care is required since tior is affected by the tmdr setting. bit bit name initial value r/w description 15 to 3 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 2 1 0 ioa2 ioa1 ioa0 0 0 0 r/w r/w r/w i/o control bits ioa2 to ioa0 specify the functions of tgra and the to pin. for details, refer to table 14.5, ioa2 to ioa0. table 14.5 ioa2 to ioa0 bit 2 bit 1 bit 0 channel ioa2 ioa1 ioa0 description 0 always 0 output 0 1 0 output at tgra compare match * 0 1 output at tgra compare match 0 1 1 initial output is 0 output for to pin toggle output at tgra compare match * 0 always 1 output 0 1 0 output at tgra compare match 0 1 output at tgra compare match * 0 to 3 1 1 1 initial output is 1 output for to pin toggle output at tgra compare match * note: * this setting is invalid in pwm mode. rev. 1.0, 11/02, page 339 of 690 14.3.4 timer interrupt enable registers (tier) tier are 16-bit registers that control enabling or disabling of interrupt requests for each channel. bit bit name initial value r/w description 15 to 5 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 4 tciev 0 r/w overflow interrupt enable enables or disables interrupt requests by the tcfv bit when the tcfv bit in tsr is set to 1 (tcnt overflow). 0: interrupt requests by tcfv disabled 1: interrupt requests by tcfv enabled 3 tgied 0 r/w tgr interrupt enable d enables or disables interrupt requests by the tgfd bit when the tgfd bit in tsr is set to 1 (tcnt and tgrd compare match). 0: interrupt requests by tgfd disabled 1: interrupt requests by tgfd enabled 2 tgiec 0 r/w tgr interrupt enable c enables or disables interrupt requests by the tgfc bit when the tgfc bit in tsr is set to 1 (tcnt and tgrc compare match). 0: interrupt requests by tgfc disabled 1: interrupt requests by tgfc enabled 1 tgieb 0 r/w tgr interrupt enable b enables or disables interrupt requests by the tgfb bit when the tgfb bit in tsr is set to 1 (tcnt and tgrb compare match). 0: interrupt requests by tgfb disabled 1: interrupt requests by tgfb enabled 0 tgiea 0 r/w tgr interrupt enable a enables or disables interrupt requests by the tgfa bit when the tgfa bit in tsr is set to 1 (tcnt and tgra compare match). 0: interrupt requests by tgfa disabled 1: interrupt requests by tgfa enabled rev. 1.0, 11/02, page 340 of 690 14.3.5 timer status registers (tsr) tsr are 16-bit registers that indicate the status of each channel. bit bit name initial value r/w description 15 to 5 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 4 tcfv 0 r/(w) * overflow flag status flag that indicates that tcnt overflow has occurred. [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000) 3tgfd0r/(w) * output compare flag d status flag that indicates the occurrence of tgrd compare match. [clearing condition] when 0 is written to tgfd after reading tgfd = 1 [setting condition] when tcnt = tgrd 2tgfc0r/(w) * output compare flag c status flag that indicates the occurrence of tgrc compare match. [clearing condition] when 0 is written to tgfc after reading tgfc = 1 [setting condition] when tcnt = tgrc 1tgfb0r/(w) * output compare flag b status flag that indicates the occurrence of tgrb compare match. [clearing condition] when 0 is written to tgfb after reading tgfb = 1 [setting condition] when tcnt = tgrb rev. 1.0, 11/02, page 341 of 690 bit bit name initial value r/w description 0tgfa0r/(w) * output compare flag a status flag that indicates the occurrence of tgra compare match. [clearing condition] when 0 is written to tgfa after reading tgfa = 1 [setting condition] when tcnt = tgra note: * only 0 can be written for clearing the flags. 14.3.6 timer counters (tcnt) tcnt are 16-bit counters. the initial value of tcnt is h'0000. 14.3.7 timer general registers (tgr) tgr are 16-bit registers. tgrc and tgrd can also be designated for operation as buffer registers*. the initial value of tgr is h'ffff. note: *tgr buffer register combinations are tgra?tgrc and tgrb?tgrd. 14.3.8 timer start register (tstr) tstr is a 16-bit readable/writable register that selects tcnt operation/stoppage for channels 0 to 3. bit bit name initial value r/w description 15 to 4 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 3 2 1 0 cst3 cst2 cst1 cst0 0 0 0 0 r/w r/w r/w r/w counter start select operation or stoppage for tcnt. 0: tcntn count operation is stopped 1: tcntn performs count operation [legend] n = 3 to 0 rev. 1.0, 11/02, page 342 of 690 14.4 operation 14.4.1 overview operation in each mode is outlined below. normal operation: each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation and periodic counting. buffer operation : when a compare match occurs, the value in the buffer register for the relevant channel is transferred to tgr. for update timing from a buffer register, rewriting on compare match occurrence or on counter clearing can be selected. pwm mode: in this mode, a pwm waveform is output. the output level can be set by means of tior. a pwm waveform with a duty cycle of between 0% and 100% can be output, according to the setting of each tgr register. rev. 1.0, 11/02, page 343 of 690 14.4.2 basic functions counter operation: when one of bits cst0 to cst3 is set to 1 in tstr, the tcnt counter for the corresponding channel starts counting. tcnt can operate as a free-running counter, periodic counter, and so on. ? example of count operation setting procedure figure 14.2 shows an example of the count operation setting procedure. select counter clock operation selection select counter clearing source periodic counter set period start count rev. 1.0, 11/02, page 344 of 690 ? free-running count operation and periodic count operation immediately after a reset, the tpu?s tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up- count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. after overflow, tcnt starts counting up again from h'0000. figure 14.3 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 14.3 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr2 to cclr0 in tcr. after the settings have been made, tcnt starts up-count operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. after a compare match, tcnt starts counting up again from h'0000. figure 14.4 illustrates periodic counter operation. tcnt value tgra h'0000 cst bit tgfa time counter cleared by tgra compare match flag cleared by software figure 14.4 periodic counter operation rev. 1.0, 11/02, page 345 of 690 waveform output by compare match: the tpu can perform 0, 1, or toggle output from the corresponding output pin (to pin) using tgra compare match. ? example of setting procedure for waveform output by compare match figure 14.5 shows an example of the setting procedure for waveform output by compare match select waveform output mode output selection set output timing start count rev. 1.0, 11/02, page 346 of 690 figure 14.7 shows an example of toggle output. in this example tcnt has been designated as a periodic counter (with counter clearing performed by compare match b), and settings have been made so that output is toggled by compare match a. tcnt value h'ffff h'0000 to pin time tgrb tgra toggle output counter cleared by tgrb compare match figure 14.7 example of toggle output operation 14.4.3 buffer operation buffer operation, enables tgrc and tgrd to be used as buffer registers. table 14.6 shows the register combinations used in buffer operation. table 14.6 register combinations in buffer operation timer general register buffer register tgra tgrc tgrb tgrd when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. for update timing from a buffer register, rewriting on compare match occurrence or on counter cleaning can be selected. this operation is illustrated in figure 14.8. buffer register timer general register tcnt comparator compare match signal counter clearing signal bfwt bit figure 14.8 compare match buffer operation rev. 1.0, 11/02, page 347 of 690 example of buffer operation setting procedure: figure 14.9 shows an example of the buffer operation setting procedure. set buffer operation buffer operation set rewriting timing start count rev. 1.0, 11/02, page 348 of 690 tcnt value tgrb h'0000 tgrc time tgra n (a) n (tgrb+1) to pin n (a) n (b) n (tgrb+1) n (tgrb+1) n (b) tgra n (b) n (a) figure 14.10 example of buffer operation 14.4.4 pwm modes in pwm mode, pwm waveforms are output from the output pins. 0 or 1 output can be selected as the output level in response to compare match of each tgra. designating tgrb compare match as the counter-clearing source enables the period to be set in that register. all channels can be designated for pwm mode independently. pwm output is generated from the to pin using tgrb as the period register and tgra as duty cycle registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a period register compare match, the output value of each pin is the initial value set in tior. set tior so that the initial output and an output value by compare match are different. if the same levels or toggle outputs are selected, operation is disabled. conditions of duty cycle 0% and 100% are shown below. ? duty cycle 0%: the set value of the period register (tgrb) is tgra + 1 for the duty register (tgra). ? duty cycle 100%: the set value of the duty register (tgra) is 0. in pwm mode, a maximum 4-phase pwm output is possible. rev. 1.0, 11/02, page 349 of 690 example of pwm mode setting procedure: figure 14.11 shows an example of the pwm mode setting procedure. select counter clock pwm mode select counter clearing source select waveform output level rev. 1.0, 11/02, page 350 of 690 examples of pwm mode operation: figure 14.12 shows an example of pwm mode operation. in this example, tgrb compare match is set as the tcnt clearing source, 0 is set as the initial output value of the to pin by tgra, and 1 is set as the output value by tgra compare match. in this case, the value set in tgrb is used as the period, and the value set in tgra as the duty. tcnt value tgrb h'0000 to time tgra counter cleared by tgrb compare match figure 14.12 example of pwm mode operation (1) figure 14.13 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt tgra=1 tgra=2 tgra=3 rewrite timing for tgra period: tgrb=2 0 2 1 2 0 tgra=0 figure 14.13 examples of pwm mode operation (2) rtcs320a_000020020100 rev. 1.0, 11/02, page 351 of 690 section 15 realtime clock (rtc) this lsi has a realtime clock (rtc) with its own 32.768 khz crystal oscillator. a block diagram of the rtc is shown in figure 15.1. 15.1 features the rtc has the following features: ? clock and calendar functions (bcd format): seconds, minutes, hours, date, day of the week, month, and year ? 1-hz to 64-hz timer (binary format) ? start/stop function ? 30-second adjust function ? alarm interrupt: frame comparison of seconds, minutes, hours, date, day of the week, month, and year can be used as conditions for the alarm interrupt ? periodic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds ? carry interrupt: a carry interrupt indicates when a carry occurs during a counter read ? automatic leap year adjustment rev. 1.0, 11/02, page 352 of 690 module bus rtc peripheral bus interrupt control circuit prescaler ( 2) bus interface carry detection circuit ati pri cui r64cnt reset rseccnt rmincnt rhrcnt rwkcnt 16.384 khz rdaycnt rmoncnt ryrcnt comparator rsecar rminar rhrar rwkar rdayar rcr1 rcr2 rcr3 30- second adj extal2 32.768 khz 128 hz xtal2 externally connected circuit oscillator circuit prescaler ( 128) ryrar rmonar r64cnt: rseccnt: rmincnt: rhrcnt: rwkcnt: rdaycnt: rmoncnt: ryrcnt: rsecar: 64-hz counter second counter minute counter hour counter day of the week counter date counter month counter year counter second alarm register rhrar: rminar: rwkar: rdayar: rmonar: ryrar: rcr1: rcr2: rcr3: minute alarm register hour alarm register day of the week alarm register date alarm register month alarm register year alarm register rtc control register 1 rtc control register 2 rtc control register 3 legend: figure 15.1 rtc block diagram rev. 1.0, 11/02, page 353 of 690 15.2 input/output pins table 15.1 shows the rtc pin configuration. table 15.1 pin configuration pin abbreviation i/o function crystal oscillator for rtc extal2 i connects crystal to rtc oscillator * crystal oscillator for rtc xtal2 o connects crystal to rtc oscillator * power-supply for rtc v cc -rtc ? power-supply pin for rtc gnd for rtc v ss -rtc ? gnd pin for rtc note: * pull up (vccq (3.3 v power)) extal2 and leave xtal2 open, when the rtc is not used. 15.3 register descriptions the rtc has the following registers. refer to section 24, list of registers, for more detail of the address and access size. ? 64-hz counter (r64cnt) ? second counter (rseccnt) ? minute counter (rmincnt) ? hour counter (rhrcnt) ? day of week counter (rwkcnt) ? date counter (rdaycnt) ? month counter (rmoncnt) ? year counter (ryrcnt) ? second alarm register (rsecar) ? minute alarm register (rminar) ? hour alarm register (rhrar) ? day of week alarm register (rwkar) ? date alarm register (rdayar) ? month alarm register (rmonar) ? year alarm register (ryrar) ? rtc control register 1 (rcr1) ? rtc control register 2 (rcr2) ? rtc control register 3 (rcr3) rev. 1.0, 11/02, page 354 of 690 15.3.1 64-hz counter (r64cnt) the 64-hz counter (r64cnt) is an 8-bit read-only register that indicates the state of the divider circuit between 64 hz and 1 hz. r64cnt is reset to h'00 by setting the reset bit in rcr2 or the adj bit in rcr2 to 1. r64cnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 ? 0rreserved this bit is always read as 0. 6 to 0 ?? r 64-hz counter each bit (bits 6 to 0) indicates the state of the rtc divider circuit between 64 hz and 1 hz. bit frequency 6: 1 hz 5: 2 hz 4: 4 hz 3: 8 hz 2: 16 hz 1: 32 hz 0: 64 hz 15.3.2 second counter (rseccnt) the second counter (rseccnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded second section. the count operation is performed by a carry for each second of the 64 - hz counter. the range of second that can be set is 00 to 59 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rseccnt is not initialized by a power-on reset or manual reset, or in standby mode. rev. 1.0, 11/02, page 355 of 690 bit bit name initial value r/w description 7 ? 0rreserved this bit is always read as 0. the write value should always be 0. 6 to 4 ?? r/w 10-unit of the second counter in the bcd-code. the range that can be set is 0 to 5 (decimal). 3 to 0 ?? r/w 1-unit of the second counter in the bcd-code. the range that can be set is 0 to 9 (decimal). 15.3.3 minute counter (rmincnt) the minute counter (rmincnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded minute section. the count operation is performed by a carry for each minute of the second counter. the range of minute that can be set is 00 to 59 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rmincnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 ? 0rreserved this bit is always read as 0. the write value should always be 0. 6 to 4 ?? r/w 10-unit of the minute counter in the bcd-code. the range that can be set is 0 to 5 (decimal). 3 to 0 ?? r/w 1-unit of the minute counter in the bcd-code. the range that can be set is 0 to 9 (decimal). 15.3.4 hour counter (rhrcnt) the hour counter (rhrcnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded hour section. the count operation is performed by a carry for each 1 hour of the minute counter. the range of hour that can be set is 00 to 23 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rhrcnt is not initialized by a power-on reset or manual reset, or in standby mode. rev. 1.0, 11/02, page 356 of 690 bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5, 4 ?? r/w 10-unit of the hour counter in the bcd-code. the range that can be set is 0 to 2 (decimal). 3 to 0 ?? r/w 1-unit of the hour counter in the bcd-code. the range that can be set is 0 to 9 (decimal). 15.3.5 day of week counter (rwkcnt) the day of week counter (rwkcnt) is an 8-bit readable/writable register used for setting/counting in the day of week section. the count operation is performed by a carry for each day of the date counter. the range for day of the week that can be set is 0 to 6 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rwkcnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 to 0 ?? r/w counter for the day of week in the bcd-code. the range that can be set is 0 to 6 (decimal). code day of week 0: sunday 1: monday 2: tuesday 3: wednesday 4: thursday 5: friday 6: saturday rev. 1.0, 11/02, page 357 of 690 15.3.6 date counter (rdaycnt) the date counter (rdaycnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded date section. the count operation is performed by a carry for each day of the hour counter. the range of date that can be set changes within 01 to 31 (decimal) with some months and in leap years. please confirm the correct setting. errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rdaycnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5, 4 ?? r/w 10-unit of the date counter in the bcd-code. the range that can be set is 0 to 3 (decimal). 3 to 0 ?? r/w 1-unit of the date counter in the bcd-code. the range that can be set is 0 to 9 (decimal). 15.3.7 month counter (rmoncnt) the month counter (rmoncnt) is an 8-bit readable/writable register used for setting/counting in the bcd-coded month section. the count operation is performed by a carry for each month of the date counter. the range of month that can be set is 01 to 12 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rmoncnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 ?? r/w 10-unit of the month counter in the bcd-code. the range that can be set is 0 to 1 (decimal). 3 to 0 ?? r/w 1-unit of the month counter in the bcd-code. the range that can be set is 0 to 9 (decimal). rev. 1.0, 11/02, page 358 of 690 15.3.8 year counter (ryrcnt) the year counter (ryrcnt) is a 16-bit readable/writable register used for setting/counting in the bcd-coded year section. the four digits of the western calendar year are counted. the count operation is performed by a carry for each year of the month counter. the range for year that can be set is 0000 to 9999 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2 or using a carry flag. ryrcnt is not initialized by a power-on reset or manual reset, or in standby mode. leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result of 0. the year counter value 0000 is recognized as a leap year. bit bit name initial value r/w description 15 to 12 ?? r/w 1000-unit of the year counter in the bcd-code. the range that can be set is 0 to 9 (decimal). 11 to 8 ?? r/w 100-unit of the year counter in the bcd-code. the range that can be set is 0 to 9 (decimal). 7 to 4 ?? r/w 10-unit of the year counter in the bcd-code. the range that can be set is 0 to 9 (decimal). 3 to 0 ?? r/w 1-unit of the year counter in the bcd-code. the range that can be set is 0 to 9 (decimal). 15.3.9 second alarm register (rsecar) the second alarm register (rsecar) is an 8-bit readable/writable register, and an alarm register corresponding to the second counter rseccnt. when the enb bit is set to 1, a comparison with the rseccnt value is performed. for alarm registers rsecar, rminar, rhrar, rwkar, rdayar, and rmonar, a comparison with the corresponding counter value is performed for those whose enb bit is set to 1, and for rcr3, a comparison is performed when the yaen bit is set to 1. if all of those match, an rtc alarm interrupt is generated. the range of second alarm that can be set is 00 to 59 (decimal). errant operation will result if any other value is set. the enb bit in rsecar is initialized to 0 by a power-on reset, and it is not initialized by manual reset and standby mode. the remaining rsecar fields are not initialized by a power-on reset or manual reset, or in standby mode. rev. 1.0, 11/02, page 359 of 690 bit bit name initial value r/w description 7 enb 0 r/w second alarm enable specifies whether to compare rseccnt with rsecar to generate a second alarm. 0: not compared 1: compared 6 to 4 ?? r/w 10-unit of second alarm setting in the bcd-code. the range that can be set is 0 to 5 (decimal). 3 to 0 ?? r/w 1-unit of second alarm setting in the bcd-code. the range that can be set is 0 to 9 (decimal). 15.3.10 minute alarm register (rminar) the minute alarm register (rminar) is an 8-bit readable/writable register, and an alarm register corresponding to the minute counter rmincnt. when the enb bit is set to 1, a comparison with the rmincnt value is performed. for alarm registers rsecar, rminar, rhrar, rwkar, rdayar, and rmonar, a comparison with the corresponding counter value is performed for those whose enb bit is set to 1, and for rcr3, a comparison is performed when the yaen bit is set to 1. if all of those match, an rtc alarm interrupt is generated. the range of minute alarm that can be set is 00 to 59 (decimal). errant operation will result if any other value is set. the enb bit in rminar is initialized by a power-on reset, and it is not initialized by manual reset and standby mode. the remaining rminar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w minute alarm enable specifies whether to compare rmincnt with rminar to generate a second alarm. 0: not compared 1: compared 6 to 4 ?? r/w 10-unit of minute alarm setting in the bcd-code. the range that can be set is 0 to 5 (decimal). 3 to 0 ?? r/w 1-unit of minute alarm setting in the bcd-code. the range that can be set is 0 to 9 (decimal). rev. 1.0, 11/02, page 360 of 690 15.3.11 hour alarm register (rhrar) the hour alarm register (rhrar) is an 8-bit readable/writable register, and an alarm register corresponding to the hour counter rhrcnt. when the enb bit is set to 1, a comparison with the rhrcnt value is performed. for alarm registers rsecar, rminar, rhrar, rwkar, rdayar, and rmonar, a comparison with the corresponding counter value is performed for those whose enb bit is set to 1, and for rcr3, a comparison is performed when the yaen bit is set to 1. if all of those match, an rtc alarm interrupt is generated. the range of hour alarm that can be set is 00 to 23 (decimal). errant operation will result if any other value is set. the enb bit in rhrar is initialized by a power-on reset, and it is not initialized by manual reset and standby mode. the remaining rhrar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w hour alarm enable specifies whether to compare rhrcnt with rhrar to generate a second alarm. 0: not compared 1: compared 6 ? 0rreserved this bit is always read as 0. the write value should always be 0. 5, 4 ?? r/w 10-unit of hour alarm setting in the bcd-code. the range that can be set is 0 to 2 (decimal). 3 to 0 ?? r/w 1-unit of hour alarm setting in the bcd-code. the range that can be set is 0 to 9 (decimal). rev. 1.0, 11/02, page 361 of 690 15.3.12 day of week alarm register (rwkar) the day of week alarm register (rwkar) is an 8-bit readable/writable register, and an alarm register corresponding to the day of week counter rwkcnt. when the enb bit is set to 1, a comparison with the rwkcnt value is performed. for alarm registers rsecar, rminar, rhrar, rwkar, rdayar, and rmonar, a comparison with the corresponding counter value is performed for those whose enb bit is set to 1, and for rcr3, a comparison is performed when the yaen bit is set to 1. if all of those match, an rtc alarm interrupt is generated. the range of day of the week alarm that can be set is 0 to 6 (decimal). errant operation will result if any other value is set. the enb bit in rwkar is initialized by a power-on reset, and it is not initialized by manual reset and standby mode. the remaining rwkar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w day of week alarm enable specifies whether to compare rwkcnt with rwkar to generate a second alarm. 0: not compared 1: compared 6 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 to 0 ?? r/w day of week alarm code the range that can be set is 0 to 6 (decimal). code day of the week 0: sunday 1: monday 2: tuesday 3: wednesday 4: thursday 5: friday 6: saturday rev. 1.0, 11/02, page 362 of 690 15.3.13 date alarm register (rdayar) the date alarm register (rdayar) is an 8-bit readable/writable register, and an alarm register corresponding to the date counter rdaycnt. when the enb bit is set to 1, a comparison with the rdaycnt value is performed. for alarm registers rsecar, rminar, rhrar, rwkar, rdayar, and rmonar, a comparison with the corresponding counter value is performed for those whose enb bit is set to 1, and for rcr3, a comparison is performed when the yaen bit is set to 1. if all of those match, an rtc alarm interrupt is generated. the range of date alarm that can be set is 01 to 31 (decimal). errant operation will result if any other value is set. the rdaycnt range that can be set changes with some months and in leap years. please confirm the correct setting. the enb bit in rdayar is initialized by a power-on reset, and it is not initialized by manual reset and standby mode. the remaining rdayar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w date alarm enable specifies whether to compare rdaycnt with rdayar to generate a second alarm. 0: not compared 1: compared 6 ? 0rreserved this bit is always read as 0. the write value should always be 0. 5, 4 ?? r/w 10-unit of date alarm setting in the bcd-code. the range that can be set is 0 to 3 (decimal). 3 to 0 ?? r/w 1-unit of date alarm setting in the bcd-code. the range that can be set is 0 to 9 (decimal). rev. 1.0, 11/02, page 363 of 690 15.3.14 month alarm register (rmonar) the month alarm register (rmonar) is an 8-bit readable/writable register, and an alarm register corresponding to the month counter rmoncnt. when the enb bit is set to 1, a comparison with the rmoncnt value is performed. for alarm registers rsecar, rminar, rhrar, rwkar, rdayar, and rmonar, a comparison with the corresponding counter value is performed for those whose enb bit is set to 1, and for rcr3, a comparison is performed when the yaen bit is set to 1. if all of those match, an rtc alarm interrupt is generated. the range of month alarm that can be set is 01 to 12 (decimal). errant operation will result if any other value is set. the enb bit in rmonar is initialized by a power-on reset, and it is not initialized by manual reset and standby mode. the remaining rmonar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w month alarm enable specifies whether to compare rmoncnt with rmonar to generate a second alarm. 0: not compared 1: compared 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 ?? r/w 10-unit of month alarm setting in the bcd-code. the range that can be set is 0 to 1 (decimal). 3 to 0 ?? r/w 1-unit of month alarm setting in the bcd-code. the range that can be set is 0 to 9 (decimal). rev. 1.0, 11/02, page 364 of 690 15.3.15 year alarm register (ryrar) the year alarm register (ryrar) is a 16-bit readable/writable register, and an alarm register corresponding to the year counter ryrcnt. when the yaen bit in rcr3 is set to 1, a comparison with the ryrcnt value is performed. for alarm registers rsecar, rminar, rhrar, rwkar, rdayar, and rmonar, a comparison with the corresponding counter value is performed for those whose enb bit is set to 1, and for rcr3, a comparison is performed when the yaen bit is set to 1. if all of those match, an rtc alarm interrupt is generated. the range of year alarm that can be set is 0000 to 9999 (decimal). errant operation will result if any other value is set. the ryrar contents are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 15 to 12 ?? r/w 1000-unit of year alarm setting in the bcd-code. the range that can be set is 0 to 9 (decimal). 11 to 8 ?? r/w 100-unit of year alarm setting in the bcd-code. the range that can be set is 0 to 9 (decimal). 7 to 4 ?? r/w 10-unit of year alarm setting in the bcd-code. the range that can be set is 0 to 9 (decimal). 3 to 0 ?? r/w 1-unit of year alarm setting in the bcd-code. the range that can be set is 0 to 9 (decimal). rev. 1.0, 11/02, page 365 of 690 15.3.16 rtc control register 1 (rcr1) the rtc control register 1 (rcr1) is an 8-bit readable/writable register that affects carry flags and alarm flags. it also selects whether to generate interrupts for each flag. because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. rcr1 is initialized to h'00 by a power-on reset or a manual reset. in a reset, all bits are initialized to 0 except for the cf flag, which is undefined. when using the cf flag, it must be initialized beforehand. this register is not initialized in standby mode. bit bit name initial value r/w description 7 cf undefined r/w carry flag status flag that indicates that a carry has occurred. cf is set to 1 when r64cnt or rseccnt is read during a carry occurrence by r64cnt or rseccnt. a count register value read at this time cannot be guaranteed; another read is required. 0: no carry by r64cnt or rseccnt. [clearing condition] when 0 is written to cf 1: [setting condition] when r64cnt or rseccnt is read during a carry occurrence by r64cnt or rseccnt, or 1 is written to cf 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 cie 0 r/w carry interrupt enable flag when the carry flag (cf) is set to 1, the cie bit enables interrupts. 0: a carry interrupt is not generated when the cf flag is set to 1 1: a carry interrupt is generated when the cf flag is set to 1 3 aie 0 r/w alarm interrupt enable flag when the alarm flag (af) is set to 1, the aie bit enables interrupts. 0: an alarm interrupt is not generated when the af flag is set to 1 1: an alarm interrupt is generated when the af flag is set to 1 rev. 1.0, 11/02, page 366 of 690 bit bit name initial value r/w description 2, 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0af 0 r/walarm flag the af flag is set to 1 when the alarm time set in an alarm register (only registers with enb bit of the corresponding alarm registers and yaen bit in rcr3 set to 1) matches the clock and calendar time. this flag is cleared to 0 when 0 is written, but holds the previous value when 1 is written. 0: clock/calendar and alarm register have not matched. [clearing condition] when 0 is written to af 1: [setting condition] clock/calendar and alarm register have matched (only registers that enb bit and yaen bit is 1) 15.3.17 rtc control register 2 (rcr2) the rtc control register 2 (rcr2) is an 8-bit readable/writable register for periodic interrupt control, 30-second adjustment adj, divider circuit reset, and rtc count start/stop control. it is initialized to h'09 by a power-on reset. it is initialized except for rtcen and start by a manual reset. it is not initialized in standby mode, and retains its contents. bit bit name initial value r/w description 7 pef 0 r/w periodic interrupt flag indicates interrupt generation with the period designated by the pes2 to pes0 bits. when set to 1, pef generates periodic interrupts. 0: interrupts not generated with the period designated by the pes bits. [clearing condition] when 0 is written to pef 1: [setting condition] when interrupts are generated with the period designated by the pes bits or 1 is written to pef rev. 1.0, 11/02, page 367 of 690 bit bit name initial value r/w description 6 5 4 pes2 pes1 pes0 0 0 0 r/w r/w r/w periodic interrupt interval these bits specify the periodic interrupt interval. 000: no periodic interrupts generated 001: periodic interrupt generated every 1/256 second 010: periodic interrupt generated every 1/64 second 011: periodic interrupt generated every 1/16 second 100: periodic interrupt generated every 1/4 second 101: periodic interrupt generated every 1/2 second 110: periodic interrupt generated every 1 second 111: periodic interrupt generated every 2 seconds 3 rtcen 1 r/w controls the operation of the crystal oscillator for the rtc. 0: halts the crystal oscillator for the rtc. 1: runs the crystal oscillator for the rtc. 2 adj 0 r/w 30 second adjustment when 1 is written to the adj bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. the divider circuit will be simultaneously reset. this bit is always read as 0. 0: runs normally. 1: 30-second adjustment. 1 reset 0 r/w reset when 1 is written, initializes the divider circuit (rtc prescaler and r64cnt). this bit is always read as 0. 0: runs normally. 1: divider circuit is reset. rev. 1.0, 11/02, page 368 of 690 bit bit name initial value r/w description 0 start 1 r/w start bit halts and restarts the counter (clock). 0: second/minute/hour/day/week/month/year counter halts. 1: second/minute/hour/day/week/month/year counter runs normally. note: the 64-hz counter always runs unless stopped with the rtcen bit. 15.3.18 rtc control register 3 (rcr3) the rtc control register 3 (rcr3) is an 8-bit readable/writable register that controls the comparison between the bcd-coded year section counter ryrcnt of the rtc and the year alarm register ryrar. bit bit name initial value r/w description 7 yaen 0 r/w year alarm enable when this bit is set to 1, the year alarm register (ryrar) is compared with the year counter (ryrcnt). for alarm registers rsecar, rminar, rhrar, rwkar, rdayar, and rmonar, a comparison with the corresponding counter value is performed for those whose enb bit is set to 1, and for rcr3, a comparison is performed when this bit is set to 1. if all of those match, an rtc alarm interrupt is generated. 6 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 369 of 690 15.4 operation 15.4.1 initial settings of registers after power-on all the registers should be set after the power is turned on. 15.4.2 setting time figure 15.2 shows how to set the time when the clock is stopped. write 1 to reset and 0 to start in the rcr2 register order is irrelevant write 1 to start in the rcr2 register set seconds, minutes, hour, day, day of the week, month and year stop clock, reset divider circuit start clock figure 15.2 setting time rev. 1.0, 11/02, page 370 of 690 15.4.3 reading the time figure 15.3 shows how to read the time. if a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. part (a) in figure 15.3 shows the method of reading the time without using interrupts; part (b) in figure 15.3 shows the method using interrupts. to keep programming simple, method (a) should normally be used. write 0 to cf in rcr1 note: set af to 1 so that alarm flag is not cleared. read rcr1 and check cf write 0 to cie in rcr1 carry flag = 1? no yes clear the carry flag disable the carry interrupt read counter register write 1 to cie in rcr1, and write 0 to cf in rcr1 note: set af in rcr1 to 1 so that alarm flag is not cleared. interrupt generated? no yes enable the carry interrupt clear the carry flag disable the carry interrupt read counter register to read the time without using interrupts (b) to use interrupts (a) write 0 to cie in rcr1 figure 15.3 reading the time rev. 1.0, 11/02, page 371 of 690 15.4.4 alarm function figure 15.4 shows how to use the alarm function. alarms can be generated using seconds, minutes, hours, day of the week, date, month, year, or any combination of these. set the enb or yaen bit for the register on which the alarm is placed to 1, and then set the alarm time in the lower bits. clear the enb or yaen bit for the register on which the alarm is not placed to 0. when the clock and alarm times match, 1 is set in the af bit in rcr1. alarm detection can be checked by reading this bit, but normally it is done by interrupt. if 1 is placed in the aie bit in rcr1, an interrupt is generated when an alarm occurs. disable interrupt to prevent erroneous interruption.(aie bit in rcr1 is cleared) then write 1. clock running set alarm time cancel alarm interrupt always clear, since the flag may have been set while the alarm time was being set. (write 0 to af of rcr1 to clear it. ) clear alarm flag monitor alarm time (wait for interrupt or check alarm flag) figure 15.4 using the alarm function rev. 1.0, 11/02, page 372 of 690 15.4.5 crystal oscillator circuit crystal oscillator circuit constants (recommended values) are shown in table 15.2, and the rtc crystal oscillator circuit in figure 15.5. table 15.2 recommended oscillator circuit constants (recommended values) f osc c in c out 32.768 khz 10 to 22 pf 10 to 22 pf this lsi extal2 xtal2 xtal c in c out r f r d notes: 1. select either the c in or c out side for frequency adjustment variable capacitor according to requirements such as frequency range, stability, etc. 2. built-in resistance value r f (typ value) = 10 m ? , r d (typ value) = 400 k ? 3. c in and c out values include stray capacitance due to the wiring. take care when using a ground plane. 4. the crystal oscillation settling time depends on the mounted circuit constants, stray capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. place the crystal resonator and load capacitors c in and c out as close as possible to the chip. (correct oscillation may not be possible if there is externally induced noise in the extal2 and xtal2 pins.) 6. ensure that the crystal resonator connection pin (extal2, xtal2) wiring is routed as far away as possible from other power lines (except gnd) and signal lines. figure 15.5 example of crystal oscillator circuit connection rev. 1.0, 11/02, page 373 of 690 15.5 notes for usage 15.5.1 register writing during rtc count the following rtc registers cannot be written to during an rtc count (while the start bit in rcr2 = 1). rseccnt, rmincnt, rhrcnt, rdaycnt, rwkcnt, rmoncnt, ryrcnt the rtc count must be halted before writing to any of the above registers. 15.5.2 use of realtime clock (rtc) periodic interrupts the method of using the periodic interrupt function is shown in figure 15.6. a periodic interrupt can be generated periodically at the interval set by the periodic interrupt interval bits (pes0 to pes2) in rcr2. when the time set by the pes0 to pes2 bits has elapsed, the pef bit is set to 1. the pef is cleared to 0 upon periodic interrupt generation when the periodic interrupt interval bits (pes0 to pes2) is set. periodic interrupt generation can be confirmed by reading this bit, but normally the interrupt function is used. set pes0 to pes2, and clear pef to 0, in rcr2 clear pef to 0 set pes, clear pef elapse of time set by pes clear pef figure 15.6 using periodic interrupt function 15.5.3 standby mode after register setting if the standby mode is entered after the rtc registers are set, the time cannot be counted correctly. after setting the registers, wait for 2 rtc clock cycles or longer before the standby mode is entered. rev. 1.0, 11/02, page 374 of 690 scis3c2b_000020020100 rev. 1.0, 11/02, page 375 of 690 section 16 serial communication interface with fifo (scif) this lsi has a two-channel serial communication interface with on-chip fifo buffers (serial communication interface with fifo: scif). the scif can perform asynchronous and clock synchronous serial communication. 64-stage fifo registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 16.1 features ? asynchronous mode serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia). there is a choice of eight serial data communication formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even/odd/none ? lsb-first transfer ? receive error detection: parity, framing, and overrun errors ? break detection: if a framing error is followed by at least one frame at the space ?0? (low) level, a break is detected. ? clock synchronous mode serial data communication is synchronized with a clock. serial data communication can be carried out with other chips that have a synchronous communication function. ? data length: 8 bits ? lsb-first transfer ? full-duplex communication capability the transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. the transmitter and receiver both have a 64-stage fifo buffer structure, enabling fast and continuous serial data transmission and reception. ? on-chip baud rate generator allows any bit rate to be selected. ? choice of serial clock source: internal clock from baud rate generator or external clock from sck pin. rev. 1.0, 11/02, page 376 of 690 ? six interrupt sources in asynchronous mode there are six interrupt sources ? transmit-data-stop, transmit-fifo-data-empty, receive-fifo- data-full, receive-error (framing/parity error), break-receive, and receive-data-ready interrupts. ? two interrupt sources in clock synchronous mode there are two interrupt sources ? transmit-fifo-data-empty and receive-fifo-data-full interrupts. ? the dma controller (dmac) can be activated to execute a data transfer in the event of a transmit-fifo-data-empty, transmit-data-stop, or receive-fifo-data-full interrupt. the dmac requests of transmit-fifo-data-empty and transmit-data-stop interrupts are the same. ? on-chip modem control functions ( cts and rts ) ? on-chip transmit-data-stop functions (only in asynchronous mode) ? when not in use, the scif can be stopped by halting its clock supply to reduce power consumption. ? the amount of data in the transmit/receive fifo registers and the number of receive errors in the receive data in the receive fifo register can be ascertained. rev. 1.0, 11/02, page 377 of 690 figure 16.1 shows a block diagram of the scif. scif4 module data bus scfrdr (64-stage) rxd txd sck scftdr (64-stage) sctsr scrsr scfdr scfcr scfer scssr scscr scsmr sctdsr scbrr transmission/ reception control baud rate generator clock parity generation parity check external clock p p /4 p /16 p /64 scif bus interface peripheral bus scrsr: receive shift register scfrdr: receive fifo data register sctsr: transmit shift register scftdr: transmit fifo data register scsmr: serial mode register scscr: serial control register scfer: fifo error count register scssr: serial status register scbrr: bit rate register scfcr: fifo control register scfdr: fifo data count register sctdsr: transit data stop register scif interrupt note: figure 16.1 block diagram of scif rev. 1.0, 11/02, page 378 of 690 16.2 input/output pins table 16.1 shows the scif pin configuration. table 16.1 pin configuration channel pin name abbreviation * 1 i/o function 0 serial clock sck0 sck input/output clock input/output receive data rxd0 rxd * 2 input receive data input transmit data txd0 txd * 2 output transmit data output modem control cts0 cts input transmission possible modem control rts0 rts output transmit request 2 serial clock sck2 sck input/output clock input/output receive data rxd2 rxd * 2 input receive data input transmit data txd2 txd * 2 output transmit data output modem control cts2 cts input transmission possible modem control rts2 rts output transmit request notes: * 1. the pins are collectively called sck, rxd, txd, cts , and rts without channel number in the following descriptions. * 2. these pins are made to function as serial pins by setting scif operation with the te and re bits in scscr. rev. 1.0, 11/02, page 379 of 690 16.3 register descriptions the scif has the following internal registers. for details on register addresses and register states in each processing state, refer to section 24, list of registers. 1. channel 0 ? serial mode register 0 (scsmr_0) ? bit rate register 0 (scbrr_0) ? serial control register 0 (scscr_0) ? transmit data stop register 0 (sctdsr_0) ? fifo error count register 0 (scfer_0) ? serial status register 0 (scssr_0) ? fifo control register 0 (scfcr_0) ? fifo data count register 0 (scfdr_0) ? transmit fifo data register 0 (scftdr_0) ? receive fifo data register 0 (scfrdr_0) 2. channel 2 ? serial mode register 2 (scsmr_2) ? bit rate register 2 (scbrr_2) ? serial control register 2 (scscr_2) ? transmit data stop register 2 (sctdsr_2) ? fifo error count register 2 (scfer_2) ? serial status register 2 (scssr_2) ? fifo control register 2 (scfcr_2) ? fifo data count register 2 (scfdr_2) ? transmit fifo data register 2 (scftdr_2) ? receive fifo data register 2 (scfrdr_2) rev. 1.0, 11/02, page 380 of 690 16.3.1 receive shift register (scrsr) scrsr is the register used to receive serial data. the scif sets serial data input from the rxd pin in scrsr in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to the receive fifo data register, scfrdr, automatically. scrsr cannot be directly read or written to by the cpu. 16.3.2 receive fifo data register (scfrdr) scfrdr is a 64-stage 8-bit fifo register that stores received serial data. when the scif has received one byte of serial data, it transfers the received data from scrsr to scfrdr where it is stored, and completes the receive operation. scrsr is then enabled for reception, and consecutive receive operations can be performed until the receive fifo data register is full (64 data bytes). scfrdr is a read-only register, and cannot be written to by the cpu. if a read is performed when there is no receive data in the receive fifo data register, an undefined value will be returned. when the receive fifo data register is full of receive data, subsequent serial data is lost. bit bit name initial value r/w description 7 to 0 scfrd7 to scfrd0 undefined r serial receive data fifo 16.3.3 transmit shift register (sctsr) sctsr is the register used to transmit serial data. to perform serial data transmission, the scif first transfers transmit data from scftdr to sctsr, then sends the data sequentially to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from scftdr to sctsr, and transmission is started automatically. sctsr cannot be directly read or written to by the cpu. rev. 1.0, 11/02, page 381 of 690 16.3.4 transmit fifo data register (scftdr) scftdr is an 8-bit 64-stage fifo data register that stores data for serial transmission. if sctsr is empty when transmit data is written to scftdr, the scif transfers the transmit data written in scftdr to sctsr and starts serial transmission. scftdr is a write-only register, and cannot be read by the cpu. the next data cannot be written when scftdr is filled with 64 bytes of transmit data. data written in this case is ignored. bit bit name initial value r/w description 7 to 0 scftd7 to scftd0 undefined w serial transmit data fifo 16.3.5 serial mode register (scsmr) scsmr is a 16-bit readable/writable register used to set the scif?s serial transfer format and select the baud rate generator clock source and the sampling rate. rev. 1.0, 11/02, page 382 of 690 bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 src2 src1 src0 0 0 0 r/w r/w r/w sampling control select the sampling rate in asynchronous mode. this setting is valid only in asynchronous mode. 000: sampling rate 1/16 001: sampling rate 1/5 010: sampling rate 1/11 011: sampling rate 1/13 100: sampling rate 1/29 101: setting prohibited 110: setting prohibited 111: setting prohibited 7 c/a 0 r/w communication mode selects whether the sci operates in the asynchronous or clock synchronous mode. 0: asynchronous mode 1: clock synchronous mode 6 chr 0 r/w character length selects seven or eight bits as the data length. this setting is only valid in asynchronous mode. in clock synchronous mode, the data length is always eight bits, regardless of the chr setting. 0: 8-bit data 1: 7-bit data * note: * when the 7-bit data is selected, the msb bit (bit 7) in the transmit fifo data register (scftdr) is not transmitted. rev. 1.0, 11/02, page 383 of 690 bit bit name initial value r/w description 5 pe 0 r/w parity enable selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. this setting is only valid in asynchronous mode. in synchronous mode, parity bit addition and checking is not performed, regardless of the pe setting. 0: parity bit addition and checking disabled 1: parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/e bit. 4 o/e 0 r/w parity mode selects either even or odd parity for use in parity addition and checking. the o/e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking. the o/e bit setting is invalid when parity addition and checking is disabled in asynchronous and clock synchronous mode. 0: even parity * 1 1: odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. rev. 1.0, 11/02, page 384 of 690 bit bit name initial value r/w description 3 stop 0 r/w stop bit length selects one or two bits as the stop bit length. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. this setting is only valid in asynchronous mode. in clock synchronous mode, this setting is invalid since stop bits are not added. 0: one stop bit * 1 1: two stop bits * 2 notes: 1. in transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. in transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. 2 ? 0rreserved this bit is always read as 0. the write value should always be 0. 1 0 cks1 cks0 0 0 r/w r/w clock select select the clock source for the on-chip baud rate generator. 00: p 01: p /4 10: p /16 11: p /64 note: when the clock synchronous mode is selected (c/a bit = 1), the bits other than cks1 and cks0 bits are all fixed to 0. rev. 1.0, 11/02, page 385 of 690 16.3.6 serial control register (scscr) scscr is a 16-bit readable/writable register that enables or disables the scif transfer operations and interrupt requests, and selects the serial clock source. bit bit name initial value r/w description 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 tsie 0 r/w transmit data stop interrupt enable enables or disables generation of a transmit-data-stop interrupt when the tse bit in scfcr is enabled and the tsf flag in scssr is set to 1. 0: transmit-data-stop interrupt disabled * 1: transmit-data-stop interrupt enabled note: * the interrupt request is cleared by clearing the tsf flag to 0 after reading 1 from it or clearing the tsie bit to 0. 10 erie 0 r/w receive error interrupt enable enables or disables generation of a receive-error (framing or parity error) interrupt when the er flag in scssr is set to 1. 0: receive-error interrupt disabled * 1: receive-error interrupt enabled note: * the interrupt request is cleared by clearing the er flag to 0 after reading 1 from it or clearing the erie bit to 0. rev. 1.0, 11/02, page 386 of 690 bit bit name initial value r/w description 9 brie 0 r/w break interrupt enable enables or disables generation of a break-receive interrupt when the brk flag in scssr is set to 1. 0: break-receive interrupt disabled * 1: break-receive interrupt enabled note: * the interrupt request is cleared by clearing the brk flag to 0 after reading 1 from it or clearing the brie bit to 0. 8 drie 0 r/w receive data ready interrupt enable enables or disables generation of a receive-data-ready interrupt when the dr flag in scssr is set to 1. 0: receive-data-ready interrupt disabled * 1: receive-data-ready interrupt enabled note: * the interrupt request is cleared by clearing the dr flag to 0 after reading 1 from it or clearing the drie bit to 0. 7 tie 0 r/w transmit interrupt enable enables or disables generation of a transmit-fifo-data- empty interrupt request when the tdfe flag in scssr is set to 1. 0: transmit-fifo-data-empty interrupt request disabled * 1: transmit-fifo-data-empty interrupt request enabled note: * the interrupt request is cleared by writing transmit data exceeding the transmit trigger set number to scftdr, reading 1 from the tdfe flag, then clearing it to 0, or clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable enables or disables generation of a receive-fifo-data- full interrupt request when the rdf flag in scssr is set to 1. 0: receive-fifo-data-full interrupt request disabled * 1: receive-fifo-data-full interrupt request enabled note: * the interrupt requests is cleared by reading 1 from the rdf flag, then clearing the flag to 0, or clearing the rie bit to 0. rev. 1.0, 11/02, page 387 of 690 bit bit name initial value r/w description 5 te 0 r/w transmit enable enables or disables the start of serial transmission by the scif. 0: transmission disabled 1: transmission enabled * note: * the serial mode register (scsmr) and fifo control register (scfcr) settings must be made, the transmit format decided, and the transmit fifo reset, before the te bit is set to 1. 4 re 0 r/w receive enable enables or disables the start of serial reception by the scif. 0: reception disabled * 1 1: reception enabled * 2 notes: 1. clearing the re bit to 0 does not affect the dr, er, brk, rdf, fer, per, and orer flags, which retain their state. 2. the serial mode register (scsmr) and fifo control register (scfcr) settings must be made, the receive format decided, and the receive fifo reset, before the re bit is set to 1. 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 388 of 690 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable select the scif clock source. the cke1 and cke0 bits must be set before determining the scif operating mode with scsmr. 00: internal clock/sck pin functions as input pin (input signal ignored) 01: internal clock/sck pin functions as serial clock output * 1 10: external clock/sck pin functions as clock input * 2 11: external clock/sck pin functions as clock input * 2 when data is sampled by the on-chip baud rate generator, set bits cke1 and cke0 to b 00 (internal clock/sck pin functions as input pin (input signal ignored)). when using the sck pin as a port, set bits cke1 and cke0 to b?00. notes: * 1. in synchronous mode, a clock with a frequency equal to the bit rate is output. * 2. in asynchronous mode, a clock with a sampling rate should be input. for example, when the sampling rate is 1/16, a clock with a frequency of 8 times the bit rate should be input. when an external clock is not input, set bits cke1 and cke0 to b 00 or b 01. rev. 1.0, 11/02, page 389 of 690 16.3.7 fifo error count register (scfer) scfer is a 16-bit read-only register that indicates the number of receive errors (framing or parity error). bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 to 8 per5 to per0 all 0 r parity error count indicates the number of data, in which parity errors are generated, in receive data stored in the receive fifo data register (scfrdr) in asynchronous mode. after setting the er bit in scssr, the value of bits 13 to 8 indicates the number of parity error generated data. when all 64 bytes of receive data in scfrdr have parity errors, the per5 to per0 bits indicate 0. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 to 0 fer5 to fer0 all 0 r framing error count indicates the number of data, in which framing errors are generated, in receive data stored in the receive fifo data register (scfrdr) in asynchronous mode. after setting the er bit in scssr, the value of bits 5 to 0 indicates the number of framing error generated data. when all 64 bytes of receive data in scfrdr have framing errors, the fer5 to fer0 bits indicate 0. rev. 1.0, 11/02, page 390 of 690 16.3.8 serial status register (scssr) scssr is a 16-bit readable/writable register that indicates the scif status. however, 1 cannot be written to the orer, tsf, er, tdfe, brk, rdf, and dr flags. also note that in order to clear these flags to 0, they must be read as 1 beforehand. the tend, fer, and per flags are read-only flags and cannot be modified. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 orer 0 r/(w) * overrun error indicates that an overrun error occurred during reception. this bit is only valid in asynchronous mode. 0: reception in progress, or reception has ended successfully * 1 [clearing conditions] ? power-on reset or manual reset ? when 0 is written to orer after reading orer = 1 1: an overrun error occurred during reception * 2 [setting condition] when serial reception is completed while receive fifo is full notes: * 1. the orer flag is not affected and retains its previous state when the re bit in scscr is cleared to 0. * 2. the receive data prior to the overrun error is retained in scfrdr, and the data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1. rev. 1.0, 11/02, page 391 of 690 bit bit name initial value r/w description 8tsf 0 r/(w) * transmit data stop indicates that the number of transmit data matches the value of sctdsr. 0: number of transmit data does not match the value of sctdsr [clearing conditions] ? power-on reset or manual reset ? when 0 is written to tsf after reading tsf = 1 1: number of transmit data matches the value of sctdsr 7er 0 r/(w) * receive error indicates that a framing error or parity error occurred during reception in asynchronous mode. * 1 0: no framing error or parity error occurred during reception [clearing conditions] ? power-on reset or manual reset ? when 0 is written to er after reading er = 1 1: a framing error or parity error occurred during reception [setting conditions] ? when the scif checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 * 2 ? when, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in scsmr notes: * 1. the er flag is not affected and retains its previous state when the re bit in scscr is cleared to 0. when a receive error occurs, the receive data is still transferred to scfrdr, and reception continues. the fer and per bits in scssr can be used to determine whether there is a receive error in the data read from scfrdr. * 2. when the stop length is two bits, only the first stop bit is checked for a value of 1; the second stop bit is not checked. rev. 1.0, 11/02, page 392 of 690 bit bit name initial value r/w description 6 tend 1 r transmit end indicates that there is no valid data in scftdr when the last bit of the transmit character is sent, and transmission has been ended. 0: transmission is in progress [clearing condition] when data is written to scftdr 1: transmission has been ended [setting condition] when there is no transmit data in scftdr on transmission of a 1-byte serial transmit character 5 tdfe 1 r/(w) * transmit fifo data empty indicates that data has been transferred from scftdr to sctsr, the number of data bytes in scftdr has fallen to or below the transmit trigger data number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr), and new transmit data can be written to scftdr. 0: a number of transmit data bytes exceeding the transmit trigger set number have been written to scftdr [clearing condition] when transmit data exceeding the transmit trigger set number is written to scftdr, and 0 is written to tdfe after reading tdfe = 1 1: the number of transmit data bytes in scftdr does not exceed the transmit trigger set number [setting conditions] ? power-on reset or manual reset ? when the number of scftdr transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation * 1 note: * 1 as scftdr is a 64-byte fifo register, the maximum number of bytes that can be written when tdfe = 1 is 64 ? (transmit trigger set number). data written in excess of this will be ignored. the number of data bytes in scftdr is indicated by scfdr. rev. 1.0, 11/02, page 393 of 690 bit bit name initial value r/w description 4brk0 r/(w) * break detect indicates that a receive data break signal has been detected in asynchronous mode. 0: a break signal has not been received [clearing conditions] ? power-on reset or manual reset ? when 0 is written to brk after reading brk = 1 1: a break signal has been received * 1 [setting condition] when data with a framing error is received, followed by the space 0 level (low level) for at least one frame length note: * 1 when a break is detected, the receive data (h'00) following detection is not transferred to scfrdr. when the break ends and the receive signal returns to mark 1, receive data transfer is resumed. 3 fer 0 r framing error indicates a framing error in the data read from scfrdr in asynchronous mode. 0: there is no framing error in the receive data read from scfrdr [clearing conditions] ? power-on reset or manual reset ? when there is no framing error in scfrdr read data 1: there is a framing error in the receive data read from scfrdr [setting condition] when there is a framing error in scfrdr read data rev. 1.0, 11/02, page 394 of 690 bit bit name initial value r/w description 2 per 0 r parity error indicates a parity error in the data read from scfrdr in asynchronous mode. 0: there is no parity error in the receive data read from scfrdr [clearing conditions] ? power-on reset or manual reset ? when there is no parity error in scfrdr read data 1: there is a parity error in the receive data read from scfrdr [setting condition] when there is a parity error in scfrdr read data 1 rdf 0 r/(w) * receive fifo data full indicates that the received data has been transferred from scrsr to scfrdr, and the number of receive data bytes in scfrdr is equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr). 0: the number of receive data bytes in scfrdr is less than the receive trigger set number [clearing conditions] ? power-on reset or manual reset ? when scfrdr is read until the number of receive data bytes in scfrdr falls below the receive trigger set number, and 0 is written to rdf after reading rdf = 1 1: the number of receive data bytes in scfrdr is equal to or greater than the receive trigger set number [setting condition] when scfrdr contains at least the receive trigger set number of receive data bytes * 1 note: * 1 scfrdr is a 64-byte fifo register. when rdf = 1, at least the receive trigger set number of data bytes can be read. if data is read when scfrdr is empty, an undefined value will be returned. the number of receive data bytes in scfrdr is indicated by the lower bits of scfdr. rev. 1.0, 11/02, page 395 of 690 bit bit name initial value r/w description 0dr0 r/(w) * receive data ready indicates that there are fewer than the receive trigger set number of data bytes in scfrdr and no further data will arrive in asynchronous mode. 0: reception is in progress or has ended successfully and there is no receive data left in scfrdr [clearing conditions] ? power-on reset or manual reset ? when all the receive data in scfrdr has been read, and 0 is written to dr after reading dr = 1 1: no further receive data has arrived [setting condition] when scfrdr contains fewer than the receive trigger set number of receive data bytes and no further data will arrive. * 1 note: * 1 the dr bit is set 15 etu after the last data is received at a sampling rate of 1/16 regardless of the setting of the sampling control bits in scsmr. etu: elementary time unit (time for transfer of one bit) note: * only 0 can be written for clearing the flags. 16.3.9 bit rate register (scbrr) scbrr is an 8-bit readable/writable register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in scsmr. bit bit name initial value r/w description 7 to 0 scbr7 to scbr0 h'ff r/w bit rate setting the scbrr setting is found from the following equation. rev. 1.0, 11/02, page 396 of 690 asynchronous mode: 1. when sampling rate is 1/16 n = p 32 2 2n-1 b 10 6 - 1 2. when sampling rate is 1/5 n = p 10 2 2n-1 b 10 6 - 1 3. when sampling rate is 1/11 n = p 22 2 2n-1 b 10 6 - 1 4. when sampling rate is 1/13 n = p 26 2 2n-1 b 10 6 - 1 5. when sampling rate is 1/29 n = p 58 2 2n-1 b 10 6 - 1 clock synchronous mode: n = p 4 2 2n-1 b 10 6 - 1 where b: bit rate (bits/s) n: scbrr setting for baud rate generator asynchronous mode: 0 n 255 clock synchronous mode: 1 n 255 p : peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) scsmr setting n clock cks1 cks0 0p 00 1p /4 0 1 2p /16 1 0 3p /64 1 1 rev. 1.0, 11/02, page 397 of 690 the bit rate error in asynchronous mode is found from the following equation: 1. when sampling rate is 1/16 error (%) = p 10 6 (1+n) b 32 2 2n-1 - 1 100 2. when sampling rate is 1/5 error (%) = p 10 6 (1+n) b 10 2 2n-1 - 1 100 3. when sampling rate is 1/11 error (%) = p 10 6 (1+n) b 22 2 2n-1 - 1 100 4. when sampling rate is 1/13 error (%) = p 10 6 (1+n) b 26 2 2n-1 - 1 100 5. when sampling rate is 1/27 error (%) = p 10 6 (1+n) b 58 2 2n-1 - 1 100 rev. 1.0, 11/02, page 398 of 690 16.3.10 fifo control register (scfcr) scfcr is a 16-bit readable/writable register that resets the data count and sets the trigger data number for the transmit and receive fifo registers, and also contains a loopback test enable bit. bit bit name initial value r/w description 15 tse 0 r/w transmit data stop enable enables or disables the transmit data stop function. this function is enabled only in asynchronous mode. since this function is not supported in clock synchronous mode, clear this bit to 0 in clock synchronous mode. 0: transmit data stop function disabled 1: transmit data stop function enabled 14 tcrst 0 r/w transmit count reset clears the transmit count to 0. this bit is valid only when the transmit data stop function is used. 0: transmit count reset disabled * 1: transmit count reset enabled (clearing to 0) note: * the transmit count is reset (clearing to 0) is performed in power-on reset or manual reset. 13 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 rstrg2 rstrg1 rstrg0 0 0 0 r/w r/w r/w rts output active trigger the rts signal goes high when the number of receive data bytes in scfrdr is equal to or greater than the trigger set number shown in below. 000: 63 001: 1 010: 8 011: 16 100: 32 101: 48 110: 54 111: 60 rev. 1.0, 11/02, page 399 of 690 bit bit name initial value r/w description 7 6 rtrg1 rtrg0 0 0 r/w r/w receive fifo data number trigger set the number of receive data bytes that sets the receive data full (rdf) flag in the serial status register (scssr). the rdf flag is set when the number of receive data bytes in scfrdr is equal to or greater than the trigger set number shown in below. 00: 1 01: 16 10: 32 11: 48 5 4 ttrg1 ttrg0 0 0 r/w r/w transmit fifo data number trigger set the number of remaining transmit data bytes that sets the transmit fifo data register empty (tdfe) flag in the serial status register (scssr). the tdfe flag is set when, as the result of a transmit operation, the number of transmit data bytes in the transmit fifo data register (scftdr) falls to or below the trigger set number shown in below. 00: 32 (32) 01: 16 (48) 10: 2 (62) 11: 0 (64) note: the values in parentheses are the number of empty bytes in scftdr when the flag is set. 3 mce 0 r/w modem control enable enables modem control signals cts and rts . this setting is only valid in asynchronous mode. 0: modem signal disabled * 1: modem signal enabled note: cts is fixed at active 0 regardless of the input value, and rts is also fixed at 0. rev. 1.0, 11/02, page 400 of 690 bit bit name initial value r/w description 2 tfrst 0 r/w transmit fifo data register reset invalidates the transmit data in the transmit fifo data register and resets it to the empty state. 0: reset operation disabled * 1: reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. 1 rfrst 0 r/w receive fifo data register reset invalidates the receive data in the receive fifo data register and resets it to the empty state. 0: reset operation disabled * 1: reset operation enabled note: * a reset operation is performed in the event of a power-on reset or manual reset. 0 loop 0 r/w loopback test internally connects the transmit output pin (txd) and receive input pin (rxd), and rts pin and cts pin, enabling loopback testing. 0: loopback test disabled 1: loopback test enabled rev. 1.0, 11/02, page 401 of 690 16.3.11 fifo data count register (scfdr) scfdr is a 16-bit read-only register that indicates the number of data bytes stored in the transmit fifo data register (scftdr) and receive fifo data register (scfrdr). bits 14 to 8 show the number of transmit data bytes in scftdr, and bits 6 to 0 show the number of receive data bytes in scfrdr. bit bit name initial value r/w description 15 ? 0rreserved this bit is always read as 0. the write value should always be 0. 14 to 8 t6 to t0 all 0 r these bits show the number of untransmitted data bytes in scftdr. a value of h'00 means that there is no transmit data, and a value of h'40 means that scftdr is full of transmit data. 7 ? 0rreserved this bit is always read as 0. the write value should always be 0. 6 to 0 r6 to r0 all 0 r these bits show the number of receive data bytes in scfrdr. a value of h'00 means that there is no receive data, and a value of h'40 means that scfrdr is full of receive data. 16.3.12 transmit data stop register (sctdsr) sctdsr is an 8-bit readable/writable register that sets the number of transmit data bytes. sctdsr is valid only when the tse bit in the fifo control register (scfcr) is enabled. transmit operation is stopped when the number of data bytes set in sctdsr is transmitted. the setting value should be h?00 (one byte) to h?ff (256 bytes). this function is only enabled in asynchronous mode. sctdsr is initialized to h'ff. rev. 1.0, 11/02, page 402 of 690 16.4 operation 16.4.1 overview the scif can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character, and in clock synchronous mode, in which synchronization is achieved with clock pulses. 64-stage fifo buffers are provided for both transmission and reception, reducing the cpu overhead and enabling fast, continuous communication to be performed. 16.4.2 asynchronous mode the transfer format is selected using the serial mode register (scsmr), as shown in table 16.2. the scif clock source is determined by the cke1 and cke0 bits in the serial control register (scscr). ? data length: choice of seven or eight bits ? choice of parity addition and addition of one or two stop bits (the combination of these parameters determines the transfer format and character length) ? detection of framing errors, parity errors, overrun errors, receive-fifo-data-full state, receive- data-ready state, and breaks, during reception ? indication of the number of data bytes stored in the transmit and receive fifo registers ? choice of internal or external clock as the scif clock source ? when internal clock is selected: the scif operates on the baud rate generator clock. ? when external clock is selected: a clock must be input according to the sampling rate. for example, when the sampling rate is 1/16, a clock with a frequency of 8 times the bit rate must be input (the on-chip baud rate generator is not used.) rev. 1.0, 11/02, page 403 of 690 table 16.2 scsmr settings for serial transfer format selection scsmr settings scif transfer format bit 6: chr bit 5: pe bit 3: stop mode data length multiprocessor bit parity bit stop bit length 0 0 0 asynchronous mode 8-bit data none no 1 bit 1 2 bits 10 yes1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 10 yes1 bit 1 2 bits rev. 1.0, 11/02, page 404 of 690 16.4.3 serial operation in asynchronous mode 1. data transfer format table 16.3 shows the transfer formats that can be used in asynchronous mode. any of eight transfer formats can be selected according to the scsmr settings. table 16.3 serial transfer formats scsmr settings serial transfer format and frame length chrpestop 123456789101112 000 s 8-bit data stop 1 s 8-bit data stop stop 1 0 s 8-bit data p stop 1 s 8-bit data p stop stop 100 s 7-bit data stop 1 s 7-bit data stop stop 1 0 s 7-bit data p stop 1 s 7-bit data p stop stop s: start bit stop: stop bit p: parity bit rev. 1.0, 11/02, page 405 of 690 2. clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the serial clock for the scif, according to the setting of the cke1 and cke0 bits in scscr. when an external clock is input at the sck pin, a clock must be input according to the sampling rate. for example, when the sampling rate is 1/16, a clock with a frequency of 8 times the bit rate must be input. 3. data transfer operations a. scif initialization before transmitting and receiving data, it is necessary to clear the te and re bits in scscr to 0, then initialize the scif as described below. when the transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the transmit shift register (sctsr) is initialized. note that clearing the te and re bits to 0 does not change the contents of scssr, scftdr, or scfrdr. the te bit should be cleared to 0 after all transmit data has been sent and the tend bit in scssr has been set to 1. clearing to 0 can also be performed during transmission, but the data being transmitted will go to the high-impedance state after the clearance. before setting te to 1 again to start transmission, the tfrst bit in scfcr should first be set to 1 to reset scftdr. when an external clock is used, the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. rev. 1.0, 11/02, page 406 of 690 figure 16.2 shows a sample scif initialization flowchart. clear te and re bits in scscr to 0 set tfrst and rfrst bits in scfcr to 1 clear the c/a bit in scsmr to 0, and set the transmit/receive format set rtrg1?0 and ttrg1?0 bits in scfcr. clear tfrst and rfrst bits to 0 set te and re bits in scscr to 1, and set rie and tie bits set value in scbrr set cke1 and cke0 bits in scscr to b'00 (leaving te and re bits cleared to 0) 1. set the clock selection in scscr. be sure to clear bits rie, tie, te, and re to 0. 2. set the transmit and receive format in scsmr. 3. write a value corresponding to the bit rate into scbrr. (not necessary if an external clock is used.) 4. wait at least one bit interval, then set the te bit and re bits in scscr to 1. also set the rie and tie bits. setting the te and re bits enables the txd and rxd pins to be used. when transmitting, the txd pin will go to the mark state; when receiving, the rxd pin will go to the idle state. initialization end 1-bit interval elapsed? no wait yes 3 4 2 1 figure 16.2 sample scif initialization flowchart rev. 1.0, 11/02, page 407 of 690 b. serial data transmission figure 16.3 shows a sample flowchart for serial transmission. use the following procedure for serial data transmission after enabling the scif for transmission. read tdfe bit in scssr read tend bit in scssr set scpdr and scpcr clear te bit in scscr to 0 write (64) ? transmit trigger set number) bytes of transmit data to scftdr, read 1 from tdfe bit in scssr, then clear to 0 1. scif status check and transmit data write: read the serial status register (scssr) and check that the tdfe flag is set to 1, then write transmit data to scftdr, read 1 from the tdfe flag, then clear the flag to 0. the number of data bytes that can be written is 64 ? (transmit trigger set number). 2. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, then write data to scftdr, and then clear the tdfe bit to 0. 3. break output at the end of serial transmission: to output a break in serial transmission, set the port sc data register (scpdr) and port sc control register (scpcr), then clear the te bit in scscr to 0. in steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in scftdr indicated by the upper 8 bits of scfdr. start of transmission end of transmission tdfe = 1? no yes all data transmitted? no yes tend = 1? no yes break output? no yes 1 2 3 figure 16.3 sample serial transmission flowchart rev. 1.0, 11/02, page 408 of 690 in serial transmission, the scif operates as described below. 1. when data is written into scftdr, the scif transfers the data from scftdr to sctsr and starts transmitting. confirm that the tdfe flag in the serial status register (scssr) is set to 1 before writing transmit data to scftdr. the number of data bytes that can be written is at least 64 ? (transmit trigger set number). 2. when data is transferred from scftdr to sctsr and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr. when the number of transmit data bytes in scftdr falls to or below the transmit trigger number set in the fifo control register (scfcr), the tdfe flag is set. if the tie bit in scscr is set to 1 at this time, a transmit-fifo-data-empty interrupt (txi) request is generated. when the transmit data stop function is used and the number of data bytes set in the transmit data stop register (sctdsr) is matched, transmit operation is stopped, and the tsf flag in the serial status register (scssr) is set. if the tsie bit in the serial control register (scscr) is set to 1, a transmit-data-stop-interrupt (tdi) request is generated. the vectors of transmit-fifo- data-empty and transmit-data-stop interrupts are the same. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit: one parity bit (even or odd parity) is output. d. a format in which a parity bit is not output can also be selected. e. stop bit(s): one or two 1-bits (stop bits) are output. f. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the scif checks the scftdr transmit data at the timing for sending the stop bit. if data is present, the data is transferred from scftdr to sctsr, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data, the tend flag in scssr is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output. rev. 1.0, 11/02, page 409 of 690 figure 16.4 shows an example of the operation for transmission in asynchronous mode. 01 1 1 0/1 0 1 tdfe tend parity bit parity bit serial data start bit start bit data data stop bit stop bit idle state (mark state) txi interrupt request data written to scftdr and tdfe flag read as 1 and then cleared to 0 by txi interrupt handler one frame d0 d1 d7 d0 d1 d7 0/1 txi interrupt request figure 16.4 example of transmit operation (example with 8-bit data, parity, one stop bit) ? transmit data stop function when a value in the sctdsr register is matched with the number of transmit data bytes, this function stops the transmit operation. interrupts can be generated and the dmac can be activated by setting the tsie bit (interrupt enable bit). figure 16.5 shows an example of operation for the transmit data stop function. tsf flag 0 d0 d1 d6 d7 0/1 0 d0 d1 d6 d7 0/1 start bit transmit data txd parity bit stop bit start bit figure 16.5 example of transmit data stop function rev. 1.0, 11/02, page 410 of 690 figure 16.6 shows a flowchart for the transmit data stop function. start of transmission end of transmission no set transmit data stop number in sctdsr set tse and tsie bits in scfcr to 1 read tsf bit in scssr; if it is 1, clear to 0 after reading 1 from tsf bit yes tsf = 1 ? 1. set the transmit data stop number in sctdsr, then set the tse bit in scfcr to 1.when an interrupt is enabled, also set the tsie bit to 1. 2. if the tsf bit in scssr is set to 1, clear it to 0 after reading 1. when transmit data is written to scftdr in this state, transmit operation is started. 3. if the tsf bit is set to 1 (transmit data stop number is matched with transmit data number), transmit operation is stopped. if the tsie bit is set to 1, an interrupt is generated. serial transmission continuation procedure: set the tcrst bit in scfcr to 1, clear transmit count, and clear the tcrst bit to 0. then follow steps 1, 2, and 3. 1 2 3 figure 16.6 transmit data stop function flowchart rev. 1.0, 11/02, page 411 of 690 c. serial data reception figures 16.7 and 16.8 show sample flowcharts for serial reception. use the following procedure for serial data reception after enabling the scif for reception. read dr, er, and brk flags in scssr read rdf flag in scssr read receive data from scfrdr, and clear rdf flag in scssr to 0 clear re bit in scscr to 0 1. receive error handling and break detection: read the dr, er, and brk flags in scssr to identify any error, perform the appropriate error handling, then clear the dr, er, and brk flags to 0. in the case of a framing error, a break can also be detected by reading the value of the rxd pin. 2. scif status check and receive data read: read scssr and check that rdf = 1, then read the receive data in scfrdr, read 1 from the rdf flag, and then clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. 3. serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of data bytes from scfrdr, read 1 from the rdf flag, and then clear the rdf flag to 0. the number of receive data bytes in scfrdr can be ascertained by reading the lower bits of scfdr. start of reception end of reception dr v er v brk = 1? yes no rdf = 1? no yes all data received? no yes error handling 3 2 1 figure 16.7 sample serial reception flowchart (1) rev. 1.0, 11/02, page 412 of 690 receive error handling break handling read receive data in scfrdr clear dr, er, and brk flags in scssr to 0 1 whether a framing error or parity error has occurred in the receive data read from scfrdr can be ascertained from the fer and per bits in scssr. 2 when a break signal is received, receive data is not transferred to scfrdr while the brk flag is set. however, note that the last data in scfrdr is h'00 and the break data in which a framing error occurred is stored. error handling end er = 1? no yes brk = 1? no yes dr = 1? no yes 1 2 figure 16.8 sample serial reception flowchart (2) rev. 1.0, 11/02, page 413 of 690 in serial reception, the scif operates as described below. 1. the scif monitors the communication line, and if 0 of a start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the scif carries out the following checks. a. stop bit check: the scif checks whether the stop bit is 1. if there are two stop bits, only the first is checked. b. the scif checks whether receive data can be transferred from the receive shift register (scrsr) to scfrdr. c. break check: the scif checks that the brk flag is 0, indicating that the break state is not set. if all the above checks are passed, the receive data is stored in scfrdr. note: reception continues when a receive error (a framing error or parity error) occurs. 4. if the rie bit in scscr is set to 1 when the rdf flag changes to 1, a receive-fifo-data-full interrupt (rxi) request is generated. if the erie bit in scscr is set to 1 when the er flag changes to 1, a receive-error interrupt (eri) request is generated. if the brie bit in scscr is set to 1 when the brk flag changes to 1, a break reception interrupt (bri) request is generated. if the drie bit in scscr is set to 1 when the dr flag changes to 1, a receive-data-ready interrupt (dri) request is generated. the vectors of receive-fifo-data-full and receive-data-ready interrupts are the same. the vectors of receive-error and break reception interrupts are the same. rev. 1.0, 11/02, page 414 of 690 figure 16.9 shows an example of the operation for reception in asynchronous mode. rdf fer eri interrupt request generated by receive error one frame data read and rdf flag read as 1 then cleared to 0 by rxi interrupt handler rxi interrupt request 01 1 1 0/1 0 1 parity bit parity bit serial data start bit start bit data data stop bit stop bit idle state (mark state) d0 d1 d7 d0 d1 d7 0/1 figure 16.9 example of scif receive operation (example with 8-bit data, parity, one stop bit) ? modem function when using a modem function, transmission can be stopped and started again according to the cts input value. when the cts is set to 1 during transmission, the data enters a mark state after transmitting one frame. when cts is set to 0, the next transmit data is output starting with a start bit. figure 16.10 shows an example of operation for the cts control. transmission stops when goes high transmission starts again when goes low 0 d0 d1 d6 d7 0/1 0 d0 d1 d6 d7 0/1 start bit transmit data txd parity bit stop bit start bit figure 16.10 cts cts cts cts control operation rev. 1.0, 11/02, page 415 of 690 when using a modem function and the receive fifo (scfrdr) is at least the number of the rts output trigger, the rts signal goes high. figure 16.11 shows an example of operation for the rts control. goes high when receive data is at least number of output trigger 0 d0 d1 d6 d7 0/1 start bit transmit data txd parity bit stop bit goes low when receive data is less than number of output trigger figure 16.11 rts rts rts rts control operation 16.4.4 clock synchronous mode 64-stage fifo buffers are provided for both transmission and reception, reducing the cpu overhead and enabling fast, continuous communication to be performed. the operating clock source is selected using the serial mode register (scsmr). the scif clock source is determined by the cke1 and cke0 bits in the serial control register (scscr). ? transmit/receive format: fixed 8-bit data ? indication of the number of data bytes stored in the transmit and receive fifo registers ? internal clock or external clock used as the scif clock source when the internal clock is selected: the scif operates on the baud rate generator clock and outputs a serial clock from sck pin. when the external clock is selected: the scif operates on the external clock input through the sck pin. rev. 1.0, 11/02, page 416 of 690 16.4.5 serial operation in clock synchronous mode don't care don't care * * lsb msb note: * high except in continuous transmission/reception serial data serial clock bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 one unit of transfer data (character or frame) figure 16.12 data format in clock synchronous communication in clock synchronous serial communication, data on the communication line is output from a falling edge of the serial clock to the next falling edge. data is guaranteed valid at the rising edge of the serial clock. in serial communication, each character is output starting with the lsb and ending with the msb. after the msb is output, the communication line remains in the state of the msb. in clock synchronous mode, the scif receives data in synchronization with the rising edge of the serial clock. 1. data transfer format a fixed 8-bit data format is used. no parity or multiprocessor bits are added. 2. clock: an internal clock generated by the on-chip baud rate generator or an external clock input through the sck pin can be selected as the serial clock for the scif, according to the setting of the cke1 and cke0 bits in scscr. eight serial clock pulses are output in the transfer of one character, and when no transmission/reception is performed, the clock is fixed high. however, when the operation mode is reception only, the synchronous clock output continues while the re bit is set to 1. to fix the clock high every time one character is transferred, write to the transmit fifo data register (scftdr) the same number of dummy data bytes as the data bytes to be received and set the te and re bits to 1 at the same time to transmit the dummy data. when the specified number of data bytes are transmitted, the clock is fixed high. 3. data transfer operations a. scif initialization: before transmitting and receiving data, it is necessary to clear the te and re bits in scscr to 0, then initialize the scif as described below. rev. 1.0, 11/02, page 417 of 690 when the clock source, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the transmit shift register (sctsr) is initialized. note that clearing the te and re bits to 0 does not change the contents of scssr, scftdr, or scfrdr. the te bit should be cleared to 0 after all transmit data has been sent and the tend bit in scssr has been set to 1. the te bit should not be cleared to 0 during transmission; if attempted, the txd pin will go to the high-impedance state. before setting te to 1 again to start transmission, the tfrst bit in scfcr should first be set to 1 to reset scftdr. rev. 1.0, 11/02, page 418 of 690 figure 16.13 shows sample scif initialization flowcharts. no yes wait end 1-bit interval elapsed? set transmit trigger number in ttrg1 and ttrg0 in scfcr, write transmit data exceeding transmit trigger setting number, and clear tdfe flag to 0 after reading 1 from it initialization clear te and re bits in scscr to 0 set tfrst bit in scfcr to 1 set cke1 and cke0 bits in scscr (leaving te and re bits cleared to 0) set c/a bit in scsmr to 1 set cks1 and cks0 bits set value in scbrr clear tfrst bit to 0 1. be sure to set the tfrst bit in scfcr to 1, to reset the fifos. 2. set the clock selection in scscr. be sure to clear bits rie, tie, te, and re to 0. 3. set the clock source selection in scsmr. 4. write a value corresponding to the bit rate into scbrr. 5. clear the tfrst bit in scfcr to 0. 6. set the transmit trigger number, write transmit data exceeding the transmit trigger setting number, and clear the tdfe flag to 0 after reading it. 7. wait one bit interval. 1 2 3 4 5 6 7 figure 16.13 sample scif initialization flowchart (1) (transmission) rev. 1.0, 11/02, page 419 of 690 no yes wait 1. be sure to set the rfrst bit in scfcr to 1, to reset the fifos. 2. set the clock selection in scscr. be sure to clear bits rie, tie, te, and re to 0. 3. set the clock source selection in scsmr. 4. write a value corresponding to the bit rate into scbrr. 5. clear the rfrst bit in scfcr to 0. 6. wait one bit interval. initialization clear te and re bits in scscr to 0 set rfrst bit in scfcr to 1 set cke1 and cke0 bits in scscr (leaving te and re bits cleared to 0) set c/a bit in scsmr to 1 set cks1 and cks0 bits set value in scbrr clear rfrst bit in scfcr to 0 1-bit interval elapsed? end 1 2 3 4 5 6 figure 16.13 sample scif initialization flowchart (2) (reception) rev. 1.0, 11/02, page 420 of 690 no yes wait 1. be sure to set the tfrst bit in scfcr to 1, to reset the fifos. 2. set the clock selection in scscr. be sure to clear bits rie, tie, te, and re to 0. 3. set the clock source selection in scsmr. 4. write a value corresponding to the bit rate into scbrr. 5. clear the tfrst and rfrst bits in scfcr to 0. 6. set the transmit trigger number, write transmit data exceeding the transmit trigger setting number, and clear the tdfe flag to 0 after reading it. 7. wait one bit interval. initialization clear te and re bits in scscr to 0 set tfrst and rfrst bits in scfcr to 1 set cke1 and cke0 bits in scscr (leaving te and re bits cleared to 0) set c/a bit in scsmr to 1 set cks1 and cks0 bits set value in scbrr clear tfrst and rfrst bits to 0 set transmit trigger number in ttrg1 and ttrg0 in scfcr, write transmit data exceeding transmit trigger setting number, and clear tdfe flag to 0 after reading 1 from it 1-bit interval elapsed? end 1 2 3 4 5 6 7 figure 16.13 sample scif initialization flowchart (3) (simultaneous transmission and reception) rev. 1.0, 11/02, page 421 of 690 b. serial data transmission: figure 16.14 shows sample flowcharts for serial transmission. no yes 1. write the remaining transmit data to scftdr. 2. transmission is started when the te bit in scscr is set to 1. 3. after the end of transmission, clear the te bit to 0. start of transmission write remaining transmit data to scftdr set te bit in scscr when using transmit fifo data interrupt, set tie bit to 1 tend =1? clear te bit in scscr to 0 end of transmission 1 2 3 figure 16.14 sample serial transmission flowchart (1) (first transmission after initialization) no yes no wait yes 1. set the transmit trigger number in scfcr. 2. write transmit data to scftdr, and clear the tdfe flag to 0 after reading 1 from it. 3. wait for one bit interval. 4. transmission is started when the te bit in scscr is set to 1. 5. after the end of transmission, clear the te bit to 0. start of transmission set transmit trigger number in ttrg1 and ttrg0 in scfcr write transmit data exceeding transmit trigger setting number, and clear tdfe flag to 0 after reading 1 from it 1-bit interval elapsed? set te bit in scscr when using transmit fifo data interrupt, set tie bit to 1 tend =1? clear te bit in scscr to 0 end of transmission 1 2 3 4 5 figure 16.14 sample serial transmission flowchart (2) (second and subsequent transmission) rev. 1.0, 11/02, page 422 of 690 c. serial data reception figure 16.15 shows sample flowcharts for serial reception. no yes 1. set the receive trigger number in scfcr. 2. reception is started when the re bit in scscr is set to 1. 3. read receive data while the rdf bit is 1. 4. after the end of reception, clear the re bit to 0. start of reception set receive trigger number in rtrg1 and rtrg0 in scfcr set re bit in scscr when using receive fifo data interrupt, set rie bit to 1 rdf =1? read receive trigger number of receive data bytes from scfrdr clear re bit in scscr to 0 end of reception 1 2 3 4 figure 16.15 sample serial reception flowchart (1) (first reception after initialization) rev. 1.0, 11/02, page 423 of 690 no yes no wait yes 1. set the receive trigger number in scfcr. 2. reset the receive fifo. 3. wait for one bit interval. 4. reception is started when the re bit in scscr is set to 1. 5. read receive data while the rdf bit is 1. 6. after the end of reception, clear the re bit to 0. start of reception set receive trigger number in rtrg1 and rtrg0 in scfcr set rfrst bit in scfcr to 1 clear rfrst bit in scfcr to 0 1-bit interval elapsed? set re bit in scscr when using receive fifo data interrupt, set rie bit to 1 rdf =1? read receive trigger number of receive data bytes from scfrdr clear re bit in scscr to 0 end of reception 1 2 3 4 5 6 figure 16.15 sample serial reception flowchart (2) (second and subsequent reception) rev. 1.0, 11/02, page 424 of 690 d. simultaneous serial data transmission and reception figure 16.16 shows sample flowcharts for simultaneous serial transmission and reception. no yes no yes 1. set the receive trigger number in scfcr. 2. write the remaining transmit data to scftdr, and if there is receive data in the fifo, read receive data until there is less than the receive trigger setting number, read the tdfe and rdf bits in scssr, and if 1, clear to 0. 3. transmission/reception is started when the te and re bits in scscr are set to 1. the te and re bits must be set simultaneously. 4. after the end of transmission/reception, clear the te and re bits to 0. start of simultaneous transmission/reception set receive trigger number in rtrg1 and rtrg0 in scfcr write remaining transmit data to scftdr read tdfe and rdf bits in scssr tdfe =1? rdf =1? write 0 to tdfe and rdf bits in scssr after reading 1 from them set te and re bits in scscr simultaneously when using transmit fifo data interrupt, set tie bit to 1 when using receive fifo data interrupt, set rie bit to 1 tdfe =1? rdf =1? read receive trigger number of receive data bytes from scfrdr clear te and re bits in scscr to 0 end of transmission/reception 2 1 3 4 figure 16.16 sample simultaneous serial transmission and reception flowchart (1) (first transfer after initialization) rev. 1.0, 11/02, page 425 of 690 no yes yes no yes no wait 1. set the receive trigger number and transmit trigger number in scfcr. 2. reset the receive fifo and transmit fifo. 3. write transmit data to scftdr, and if there is receive data in the fifo, read receive data until there is less than the receive trigger setting number, read the tdfe and rdf bits in scssr, and if 1, clear to 0. 4. wait for one bit interval. 5. transmission/reception is started when the te and re bits in scscr are set to 1. the te and re bits must be set simultaneously. 6. after the end of transmission/reception, clear the te and re bits to 0. start of simultaneous transmission/reception set receive trigger number in rtrg1 and rtrg0 in scfcr, and set transmit trigger number in ttrg1 and ttrg0 set tfrst and rfrst bits in scfcr to 1 clear tfrst and rfrst bits in scfcr to 0 write transmit data to scftdr read tdfe and rdf bits in scssr tdfe =1? rdf =1? write 0 to tdfe and rdf bits in scssr after reading 1 from them 1-bit interval elapsed? set te and re bits in scscr simultaneously when using transmit fifo data interrupt, set tie bit to 1 when using receive fifo data interrupt, set rie bit to 1 tdfe =1? rdf =1? read receive trigger number of receive data bytes from scfrdr end of transmission/reception clear te and re bits in scscr to 0 1 2 3 4 5 6 figure 16.16 sample simultaneous serial transmission and reception flowchart (2) (second and subsequent transfer) rev. 1.0, 11/02, page 426 of 690 16.5 scif interrupt sources and dmac the scif supports six interrupts in asynchronous mode?transmit-fifo-data-empty (txi), transmit-data-stop (tdi), receive-error (eri), receive-fifo-data-full (rxi), break-receive (bri), and receive-data-ready (dri). the vectors of transmit-data-stop and transmit-fifo-data-empty interrupts are the same. the vectors of receive-error and break-receive interrupts are the same. the vectors of receive-fifo-data-full and receive-data-ready interrupts are the same. in clock synchronous mode, the scif supports two interrupts?transmit-fifo-data-empty (txi) and receive-fifo-data-full (rxi). table 16.4 shows the interrupt sources. the interrupt sources can be enabled or disabled by means of the tie, rie, erie, brie, drie, and tsie bits in scscr. when the tdfe flag in scssr is set to 1, a txi interrupt request is generated. when the tsf flag in scssr is set to 1, a tdi interrupt request is generated. the dmac can be activated and data transfer performed on generation of txi and tdi interrupt requests. the dmac requests of txi and tdi are assigned to the same vector. when the rdf flag in scssr is set to 1, an rxi interrupt request is generated. the dmac can be activated and data transfer performed on generation of an rxi interrupt request. when using the dmac for transmission/reception, set and enable the dmac before making scif settings. see section 8, direct memory access controller (dmac), for details of the dmac setting procedure. when the er flag in scssr is set to 1, an eri interrupt request is generated. when the brk flag in scssr is set to 1, a bri interrupt request is generated. when the dr flag in scssr is set to 1, a dri interrupt request is generated. when the tsf flag in scssr is set to 1, a tdi interrupt request is generated. the vectors of txi and tdi, eri and bri, and rxi and dri are the same. the dmac activation and interrupts cannot be generated simultaneously by the same source. the following procedure should be used for the dmac activation. 1. set the interrupt enable bits (tie and rie) corresponding to the generated source to 1. 2. mask the corresponding interrupt requests by using the interrupt mask register of the interrupt controller. rev. 1.0, 11/02, page 427 of 690 table 16.4 scif interrupt sources description dmac activation interrupt initiated by receive error flag (er) or break flag (brk) not possible interrupt initiated by receive fifo data full flag (rdf) or receive data ready (dr) possible * 1 interrupt initiated by transmit fifo data empty flag (tdfe) or transmit data stop flag (tsf) possible * 2 notes: * 1 the dmac can be activated only by a receive-fifo-data-full interrupt request. * 2 the dmac can be activated by a transmit-fifo-data-empty (tdfe) or transmit-data- stop (tsf) interrupt request. when the dmac is activated by the tsf interrupt, it is cleared by either of two cases listed below. (1) the tsf flag is read by the cpu. (2) the transmit fifo is full. see section 5, exception handling, for priorities and the relationship with non-scif interrupts. rev. 1.0, 11/02, page 428 of 690 16.6 notes on usage note the following when using the scif. a. scftdr writing and the tdfe flag: the tdfe flag in the serial status register (scssr) is set when the number of transmit data bytes written in the transmit fifo data register (scftdr) has fallen to or below the transmit trigger number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr). after tdfe is set, transmit data up to the number of empty bytes in scftdr can be written, allowing efficient continuous transmission. however, if the number of data bytes written in scftdr is equal to or less than the transmit trigger number, the tdfe flag will be set to 1 again after being read as 1 and cleared to 0. tdfe clearing should therefore be carried out when scftdr contains more than the transmit trigger number of transmit data bytes. the number of transmit data bytes in scftdr can be found from the 14 to 8 bits of the fifo data count register (scfdr). b. scfrdr reading and the rdf flag: the rdf flag in the serial status register (scssr) is set when the number of receive data bytes in the receive fifo data register (scfrdr) has become equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr). after rdf is set, receive data equivalent to the trigger number can be read from scfrdr, allowing efficient continuous reception. however, if the number of data bytes in scfrdr is still equal to or greater than the trigger number after a read, the rdf flag will be set to 1 again if it is cleared to 0. rdf should therefore be cleared to 0 after being read as 1 after all receive data has been read. the number of receive data bytes in scfrdr can be found from the 6 to 0 bits of the fifo data count register (scfdr). c. break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. although the scif stops transferring receive data to scfrdr after receiving a break, the receive operation continues. rev. 1.0, 11/02, page 429 of 690 d. receive data sampling timing and receive margin: as an example, when the sampling rate is 1/16, the scif operates on a base clock with a frequency of 8 times the transfer rate. in reception, the scif synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the fourth base clock pulse. the receive margin can therefore be expressed as shown in equation (1). m = 0.5 ? 1 2n d ? 0.5 n ? (l ? 0.5)f ? (1 + f) 100% .......................... (1) m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.875%, as given by equation (2). when d = 0.5 and f = 0: m = (0.5 ? 1/(2 16)) 100% = 46.875% ........................................... (2) this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%. rev. 1.0, 11/02, page 430 of 690 ifirda0a_000020020100 rev. 1.0, 11/02, page 431 of 690 section 17 infrared data association module (irda) this lsi has an on-chip infrared data association (irda) interface that is based on the irda 1.0 system and can perform infrared communication. the irda is an optional module used for modulation and demodulation of signals for the scif module, and it must always be used together with the scif module. 17.1 features ? conforms to the irda 1.0 system ? asynchronous serial communication ? data length: 8 bits ? stop bit length: 1 bit ? parity bit: none ? on-chip 64-stage fifo buffers for both transmit and receive operations ? on-chip baud rate generator with selectable bit rates ? guard functions to protect the receiver during transmission ? clock supply halted to reduce power consumption when not using the irda interface figure 17.1 shows a block diagram of the irda. scif txd transfer clock rxd switching irda/scif irda irtx irrx modulation unit demodulation unit legend scif: serial communication interface with fifo figure 17.1 block diagram of irda rev. 1.0, 11/02, page 432 of 690 17.2 input/output pins table 17.1 shows the irda pin configuration. table 17.1 pin configuration pin name signal name i/o function receive data pin irrx input receive data input transmit data pin irtx output transmit data output note: clock input from the serial clock pin cannot be set in irda mode. 17.3 register description the irda has the following internal registers. for details on register addresses and register states in each processing state, refer to section 24, list of registers. ? irda mode register (scsmr_ir) 17.3.1 irda mode register (scsmr_ir) scsmr_ir is a 16-bit register that selects irda or scif mode and selects the irda output pulse width. this module operates as irda when the irmod bit is set to 1. when the irmod bit is cleared to 0, this module can also operate as an scif. rev. 1.0, 11/02, page 433 of 690 bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 irmod 0 r/w irda mode selects whether this module operates as an irda serial communication interface or as an scif. 0: operates as an scif 1: operates as an irda 6 to 3 ick3 to ick0 all 0 r/w output pulse division ratio specifies the ratio for dividing the peripheral clock (p ) to generate the irclk clock pulse to be used for irda. irclk is obtained as follows: irclk = 1/(2n + 2) p n = value set by ick3 to ick0 2 psel 0 r/w output pulse width select psel selects an irda output pulse width that is 3/16 of the bit length for 115 kbps or 3/16 of the bit length for the selected baud rate. 0: pulse width is 3/16 of the bit length 1: pulse width is 3/16 of 115 kbps bit length for the baud rate selected by ick3 to ick0 1, 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. example: p clock: 14.7456 mhz irclk: 921.6 khz (fixed) n: setting of ick3 to ick0 (0 n 15) ? 1 7 n p 2 irclk accordingly, n is 7. rev. 1.0, 11/02, page 434 of 690 17.4 operation the irda module can perform infrared communication conforming to irda 1.0 by connecting infrared transmit/receive units. the serial communication interface unit includes a buffer in the transmit unit and the receive unit, allowing cpu overhead to be reduced and continuous high- speed communication to be performed. 17.4.1 overview the irda module modifies irtx/irrx transmit/receive data waveforms to satisfy the irda 1.0 specification for infrared communication. in the irda 1.0 specification, communication is first performed at a speed of 9600 bps, and the communication speed is changed. however, the communication rate cannot be automatically changed in this module, so the communication speed should be confirmed, and the appropriate speed set for this module by software. 17.4.2 transmitting the waveforms of a serial output signal (uart frame) from the scif are modified and the signal is converted into the ir frame serial output signal by the irda module, as shown in figure 17.2. when serial data is 0, a pulse of 3/16 the ir frame bit width is generated and output. when serial data is 1, no pulse is output. rev. 1.0, 11/02, page 435 of 690 17.4.3 receiving received 3/16 ir frame bit-width pulses are demodulated and converted to a uart frame, as shown in figure 17.2. demodulation to 0 is performed for pulse output, and demodulation to 1 is performed for no pulse output. 0101001101 01 01 0 01 1 01 uart frame start bit ir frame start bit bit cycle 3/16-bit cycle pulse width uart frame data ir frame data receive transmit stop bit stop bit figure 17.2 transmit/receive operation 17.4.4 data format specification the data format of uart frames used for irda communication must be specified by the scif0 registers. the uart frame has eight data bits, no parity bit, and one stop bit. irda communication is performed in asynchronous mode, and this mode must also be specified by the scif0 registers. the sampling rate must be set to 1/16. the internal clock must be selected for the scif0 operation clock and the sck0 pin must be specified for the synchronizing clock output pin. the irda communication rate is the same as the scif0 bit rate, which is specified by the scif0 registers. rev. 1.0, 11/02, page 436 of 690 for details on scif0 registers, refer to section 16, serial communication interface with fifo (scif). ifusb40a_000020020100 rev. 1.0, 11/02, page 437 of 690 section 18 usb function module this lsi incorporates a usb function module (usb). 18.1 features ? the udc (usb device controller) conforming to usb1.1 and transceiver process usb protocol automatically. automatic processing of usb standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) ? transfer speed: full-speed ? endpoint configuration: endpoint name abbreviation transfer type maximum packet size fifo buffer capacity (byte) dma transfer endpoint 0 ep0s setup 8 8 ? ep0i control-in 8 8 ? ep0o control-out 8 8 ? endpoint 1 ep1 bulk-out 64 128 possible endpoint 2 ep2 bulk-in 64 128 possible endpoint 3 ep3 interrupt 8 8 ? configuration 1 interface 0 alternate setting 0 endpoint 1 endpoint 2 endpoint 3 ? interrupt requests: generates various interrupt signals necessary for usb transmission/reception ? clock: external input (48 mhz) (refer to section 9.4.1, frequency control register (frqcr), and section 9.4.2, usb clock frequency control register (uclkcr)) ? power-down mode power consumption can be reduced by stopping udc internal clock when usb cable is disconnected automatic transition to/recovery from suspend state ? can be connected to a philips pdiusbp11 series transceiver or compatible product in internal transceiver bypass mode (the xveroff bit in xvercr is set to 1) when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand. ? power mode: self-powered rev. 1.0, 11/02, page 438 of 690 figure 18.1 shows the block diagram of the usb. peripheral bus interrupt requests dma transfer requests status and control registers fifo udc transceiver usb function module d+ d- clock (48 mhz) udc: usb device controller legend: figure 18.1 block diagram of usb rev. 1.0, 11/02, page 439 of 690 18.2 input/output pins table 18.1 shows the usb pin configuration. table 18.1 pin configuration pin name i/o function xveroff condition xvdata input input pin for receive data from differential receiver 1 dpls input input pin to driver for d + signal from receiver 1 dmns input input pin to driver for d? signal from receiver 1 txdpls output d+ transmit output pin to driver 1 txdmns output d- transmit output pin to driver 1 txenl output driver output enable pin 1 vbus input usb cable connection monitor pin 1 or 0 suspnd output transceiver suspend state output pin 1 extal_usb input usb clock input pin (external clock input/crystal resonator connect) xtal_usb output usb clock pin (crystal resonator connect) d+ i/o usb internal transceiver d + d- i/o usb internal transceiver d? vcc-usb input power supply for usb vss-usb input ground for usb note: the usb can be connected to a philips pdiusbp11 series transceiver or compatible product in internal transceiver bypass mode (the xveroff bit in xvercr is set to 1). when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand. rev. 1.0, 11/02, page 440 of 690 18.3 register descriptions the usb has following registers. for the information on the addresses of these registers and the state of the register in each processing condition, see section 24, list of registers. ? interrupt flag register 0 (ifr0) ? interrupt flag register 1 (ifr1) ? interrupt select register 0 (isr0) ? interrupt select register 1 (isr1) ? interrupt enable register 0 (ier0) ? interrupt enable register 1 (ier1) ? ep0i data register (epdr0i) ? ep0o data register (epdr0o) ? ep0s data register (epdr0s) ? ep1 data register (epdr1) ? ep2 data register (epdr2) ? ep3 data register (epdr3) ? ep0o receive data size register (epsz0o) ? ep1 receive data size register (epsz1) ? trigger register (trg) ? data status register (dasts) ? fifo clear register (fclr) ? dma transfer setting register (dmar) ? endpoint stall register (epstl) ? transceiver control register (xvercr) rev. 1.0, 11/02, page 441 of 690 18.3.1 interrupt flag register 0 (ifr0) ifr0, together with interrupt flag register 1 (ifr1), indicates interrupt status information required by the application. when an interrupt source is generated, the corresponding bit is set to 1 and an interrupt request is sent to the cpu according to the combination with interrupt enable register 0 (ier0). clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. however, ep1full and ep2empty are status bits, and cannot be cleared. bit bit name initial value r/w description 7 brst 0 r/w bus reset this bit is set to 1 when a bus reset signal is detected on the usb bus. 6 ep1full 0 r ep1 fifo full this bit is set when endpoint 1 receives one packet of data successfully from the host, and holds a value of 1 as long as there is valid data in the fifo buffer. this is a status bit, and cannot be cleared. 5 ep2tr 0 r/w ep2 transfer request this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 2 is received from the host. a nack handshake is returned to the host until data is written to the fifo buffer and packet transmission is enabled. 4 ep2empty 1 r ep2 fifo empty this bit is set when at least one of the dual endpoint 2 transmit fifo buffers is ready for transmit data to be written. this is a status bit, and cannot be cleared. 3 setupts 0 r/w setup command receive complete this bit is set to 1 when endpoint 0 receives successfully a setup command requiring decoding on the application side, and returns an ack handshake to the host. 2 ep0ots 0 r/w ep0o receive complete this bit is set to 1 when endpoint 0 receives data from the host successfully, stores the data in the fifo buffer, and returns an ack handshake to the host. rev. 1.0, 11/02, page 442 of 690 bit bit name initial value r/w description 1 ep0itr 0 r/w ep0i transfer request this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 0 is received from the host. a nack handshake is returned to the host until data is written to the fifo buffer and packet transmission is enabled. 0 ep0its 0 r/w ep0i transmit complete this bit is set when data is transmitted to the host from endpoint 0 and an ack handshake is returned. 18.3.2 interrupt flag register 1 (ifr1) ifr1, together with interrupt flag register 0 (ifr0), indicates interrupt status information required by the application. when an interrupt source is generated, the corresponding bit is set to 1 and an interrupt request is sent to the cpu according to the combination with interrupt enable register 1 (ier1). clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 vbusmn 0 r this is a status bit which monitors the state of the vbus pin. this bit reflects the state of the vbus pin. 2 ep3tr 0 r/w ep3 transfer request this bit is set if there is no valid transmit data in the fifo buffer when an in token for endpoint 3 is received from the host. a nack handshake is returned to the host until data is written to the fifo buffer and packet transmission is enabled. 1 ep3ts 0 r/w ep3 transmit complete this bit is set when data is transmitted to the host from endpoint 3 and an ack handshake is returned. 0 vbus 0 r/w usb disconnection detection when the function is connected to the usb bus or disconnected from it, this bit is set to 1. the vbus pin of this module is used for detecting connection or disconnection. rev. 1.0, 11/02, page 443 of 690 18.3.3 interrupt select register 0 (isr0) isr0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0 (ifr0). if the usb issues an interrupt request to the intc when a bit in isr0 is cleared to 0, the interrupt corresponding to the bit will be usi0 (usb interrupt 0). if the usb issues an interrupt request to the intc when a bit in isr0 is set to 1, the corresponding interrupt will be usi1 (usb interrupt 1). if interrupts occur simultaneously, usi0 has priority by default. bit bit name initial value r/w description 7 brst 0 r/w bus reset 6 ep1full 0 r/w ep1 fifo full 5 ep2tr 0 r/w ep2 transfer request 4 ep2empty 0 r/w ep2 fifo empty 3 setupts 0 r/w setup command receive complete 2 ep0ots 0 r/w ep0o receive complete 1 ep0itr 0 r/w ep0i transfer request 0 ep0its 0 r/w ep0i transmit complete 18.3.4 interrupt select register 1 (isr1) isr1 selects the vector numbers of the interrupt requests indicated in interrupt flag register 1 (ifr1). if the usb issues an interrupt request to the intc when a bit in isr1 is cleared to 0, the interrupt corresponding to the bit will be usi0 (usb interrupt 0). if the usb issues an interrupt request to the intc when a bit in isr1 is set to 1, the corresponding interrupt will be usi1 (usb interrupt 1). if interrupts occur simultaneously, usi0 has priority by default. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 ep3tr 1 r/w ep3 transfer request 1 ep3ts 1 r/w ep3 transmit complete 0 vbus 1 r/w usb bus connect rev. 1.0, 11/02, page 444 of 690 18.3.5 interrupt enable register 0 (ier0) ier0 enables the interrupt requests of interrupt flag register 0 (ifr0). when an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the cpu. the interrupt vector number is determined by the contents of interrupt select register 0 (isr0). bit bit name initial value r/w description 7 brst 0 r/w bus reset 6 ep1full 0 r/w ep1 fifo full 5 ep2tr 0 r/w ep2 transfer request 4 ep2empty 1 r/w ep2 fifo empty 3 setupts 0 r/w setup command receive complete 2 ep0ots 0 r/w ep0o receive complete 1 ep0itr 0 r/w ep0i transfer request 0 ep0its 0 r/w ep0i transmit complete 18.3.6 interrupt enable register 1 (ier1) ier1 enables the interrupt requests of interrupt flag register 1 (ifr1). when an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the cpu. the interrupt vector number is determined by the contents of interrupt select register 1 (isr1). bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 ep3tr 0 r/w ep3 transfer request 1 ep3ts 0 r/w ep3 transmit complete 0 vbus 0 r/w usb bus connect rev. 1.0, 11/02, page 445 of 690 18.3.7 ep0i data register (epdr0i) epdr0i is an 8-byte transmit fifo buffer for endpoint 0. epdr0i holds one packet of transmit data for control-in. transmit data is fixed by writing one packet of data and setting ep0ipkte in the trigger register. when an ack handshake is returned from the host after the data has been transmitted, ep0its in interrupt flag register 0 is set. this fifo buffer can be initialized by means of ep0iclr in the fclr register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w data register for control-in transfer 18.3.8 ep0o data register (epdr0o) epdr0o is an 8-byte receive fifo buffer for endpoint 0. epdr0o holds endpoint 0 receive data other than setup commands. when data is received successfully, ep0ots in interrupt flag register 0 is set, and the number of receive bytes is indicated in the ep0o receive data size register. after the data has been read, setting ep0ordfn in the trigger register enables the next packet to be received. this fifo buffer can be initialized by means of bp0oclr in the fclr register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined r data register for control-out transfer 18.3.9 ep0s data register (epdr0s) epdr0s is an 8-byte fifo buffer specifically for receiving endpoint 0 setup commands. only the setup command to be processed by the application is received. when command data is received successfully, the setupts bit in interrupt flag register 0 is set. as a latest setup command must be received in high priority, if data is left in this buffer, it will be overwritten with new data. if reception of the next command is started while the current command is being read, command reception has priority, the read by the application is forcibly stopped, and the read data is invalid. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined r data register for storing the setup command at the control-out transfer rev. 1.0, 11/02, page 446 of 690 18.3.10 ep1 data register (epdr1) epdr1 is a 128-byte receive fifo buffer for endpoint 1. epdr1 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. when one packet of data is received successfully, ep1full in interrupt flag register 0 is set, and the number of receive bytes is indicated in the ep1 receive data size register. after the data has been read, the buffer that was read is enabled to receive data again by writing 1 to the ep1rdfn bit in the trigger register. the receive data in this fifo buffer can be transferred by dma. this fifo buffer can be initialized by means of ep1clr in the fclr register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined r data register for endpoint 1 transfer 18.3.11 ep2 data register (epdr2) epdr2 is a 128-byte transmit fifo buffer for endpoint 2. epdr2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. when transmit data is written to this fifo buffer and ep2pkte in the trigger register is set, one packet of transmit data is fixed, and the dual-fifo buffer is switched over. the transmit data for this fifo buffer can be transferred by dma. this fifo buffer can be initialized by means of ep2clr in the fclr register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w data register for endpoint 2 transfer 18.3.12 ep3 data register (epdr3) epdr3 is an 8-byte transmit fifo buffer for endpoint 3. epdr3 holds one packet of transmit data for the interrupt transfer of endpoint 3. transmit data is fixed by writing one packet of data and setting ep3pkte in the trigger register. when an ack handshake is returned from the host after one packet of data has been transmitted successfully, ep3ts in interrupt flag register 0 is set. this fifo buffer can be initialized by means of ep3clr in the fclr register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined r data register for endpoint 3 transfer rev. 1.0, 11/02, page 447 of 690 18.3.13 ep0o receive data size register (epsz0o) epsz0o indicates the number of bytes received at endpoint 0 from the host. bit bit name initial value r/w description 7 to 0 ? all 0 r number of receive data for endpoint 0 18.3.14 ep1 receive data size register (epsz1) epsz1 is a receive data size resister for endpoint 1. epsz1 indicates the number of bytes received from the host. the fifo for endpoint 1 has a dual-buffer configuration. the size of the received data indicated by this register is the size of the currently selected side (can be read by cpu). bit bit name initial value r/w description 7 to 0 ? all 0 r number of received bytes for endpoint 1 rev. 1.0, 11/02, page 448 of 690 18.3.15 trigger register (trg) trg generates one-shot triggers to control the transfer sequence for each endpoint. bit bit name initial value r/w description 7 ? undefined ? reserved the write value should always be 0. 6 ep3pkte undefined w ep3 packet enable after one packet of data has been written to the endpoint 3 transmit fifo buffer, the transmit data is fixed by writing 1 to this bit. 5 ep1rdfn undefined w ep1 read complete write 1 to this bit after one packet of data has been read from the endpoint 1 fifo buffer. the endpoint 1 receive fifo buffer has a dual-buffer configuration. writing 1 to this bit initializes the fifo that was read, enabling the next packet to be received. 4 ep2pkte undefined w ep2 packet enable after one packet of data has been written to the endpoint 2 transmit fifo buffer, the transmit data is fixed by writing 1 to this bit. 3 ? undefined ? reserved the write value should always be 0. 2 ep0srdfn undefined w ep0s read complete write 1 to this bit after data for the ep0s command fifo has been read. writing 1 to this bit enables transfer of data in the following data stage. a nack handshake is returned in response to transfer requests from the host in the data stage until 1 is written to this bit. 1 ep0ordfn undefined w ep0o read complete writing 1 to this bit after one packet of data has been read from the endpoint 0 transmit fifo buffer initializes the fifo buffer, enabling the next packet to be received. 0 ep0ipkte undefined w ep0i packet enable after one packet of data has been written to the endpoint 0 transmit fifo buffer, the transmit data is fixed by writing 1 to this bit. rev. 1.0, 11/02, page 449 of 690 18.3.16 data status register (dasts) dasts indicates whether the transmit fifo buffers contain valid data. a bit is set when data is written to the corresponding fifo buffer and the packet enable state is set, and cleared when all data has been transmitted to the host. bit bit name initial value r/w description 7, 6 ? all 0 r reserved this bit is always read as 0. 5 ep3de 0 r ep3 data present this bit is set when the endpoint 3 fifo buffer contains valid data. 4 ep2de 0 r ep2 data present this bit is set when the endpoint 2 fifo buffer contains valid data. 3 to 1 ? all 0 r reserved this bit is always read as 0. 0 ep0ide 0 r ep0i data present this bit is set when the endpoint 0 fifo buffer contains valid data. 18.3.17 fifo clear register (fclr) fclr is a register to initialize the fifo buffers for each endpoint. writing 1 to a bit clears all the data in the corresponding fifo buffer. note that the corresponding interrupt flag is not cleared. do not clear a fifo buffer during transfer. bit bit name initial value r/w description 7 ? undefined ? reserved the write value should always be 0. 6 ep3clr undefined w ep3 clear writing 1 to this bit initializes the endpoint 3 transmit fifo buffer. 5 ep1clr undefined w ep1 clear writing 1 to this bit initializes both sides of the endpoint 1 receive fifo buffer. rev. 1.0, 11/02, page 450 of 690 bit bit name initial value r/w description 4 ep2clr undefined w ep2 clear writing 1 to this bit initializes both sides of the endpoint 2 transmit fifo buffer. 3, 2 ? undefined ? reserved the write value should always be 0. 1 ep0oclr undefined w ep0o clear writing 1 to this bit initializes the endpoint 0 receive fifo buffer. 0 ep0iclr undefined w ep0i clear writing 1 to this bit initializes the endpoint 0 transmit fifo buffer. 18.3.18 dma transfer setting register (dmar) dma transfer can be carried out between the endpoint 1 and 2 data registers and memory by means of the on-chip direct memory access controller (dma). dual address transfer is performed in bytes. to start dma transfer, dmac settings must be made in addition to the settings in this register. bit bit name initial value r/w description 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 451 of 690 bit bit name initial value r/w description 1 ep2dmae 0 r/w endpoint 2 dma transfer enable when this bit is set, dma transfer is enabled from memory to the endpoint 2 transmit fifo buffer. if there is at least one byte of space in the fifo buffer, a transfer request is asserted for the dmac. in dma transfer, when 64 bytes are written to the fifo buffer the ep2 packet enable bit is set automatically, allowing 64 bytes of data to be transferred, and if there is still space in the other of the two fifos, a transfer request is asserted for the dmac again. however, if the size of the data packet to be transmitted is less than 64 bytes, the ep2 packet enable bit is not set automatically, and so should be set by the cpu with a dma transfer end interrupt. as ep2-related interrupt requests to the cpu are not automatically masked, interrupt requests should be masked as necessary in the interrupt enable register. ? operating procedure 1. write of 1 to the ep2 dmae bit in dmar 2. transfer count setting in the dmac 3. dmac activation 4. dma transfer 5. dma transfer end interrupt generated refer to section 18.7.3, dma transfer for endpoint 2. rev. 1.0, 11/02, page 452 of 690 bit bit name initial value r/w description 0 ep1dmae 0 r/w endpoint 1 dma transfer enable when this bit is set, dma transfer is enabled from the endpoint 1 receive fifo buffer to memory. if there is at least one byte of receive data in the fifo buffer, a transfer request is asserted for the dmac. in dma transfer, when all the received data is read, ep1 is read automatically and the completion trigger operates. ep1-related interrupt requests to the cpu are not automatically masked. ? operating procedure: 1. write of 1 to the ep1 dmae bit in dmar 2. transfer count setting in the dmac 3. dmac activation 4. dma transfer 5. dma transfer end interrupt generated refer to section 18.7.2, dma transfer for endpoint 1. rev. 1.0, 11/02, page 453 of 690 18.3.19 endpoint stall register (epstl) the bits in epstl are used to forcibly stall the endpoints on the application side. while a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. the stall bit for endpoint 0 is cleared automatically on reception of 8-byte command data for which decoding is performed by the function and the ep0 stl bit is cleared. when the setupts flag in the ifr0 register is set to 1, writing 1 to the ep0 stl bit is ignored. for detailed operation, see section 18.6, stall operations. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 ep3stl 0 r/w ep3 stall when this bit is set to 1, endpoint 3 is placed in the stall state. 2 ep2stl 0 r/w ep2 stall when this bit is set to 1, endpoint 2 is placed in the stall state. 1 ep1stl 0 r/w ep1 stall when this bit is set to 1, endpoint 1 is placed in the stall state. 0 ep0stl 0 r/w ep0 stall when this bit is set to 1, endpoint 0 is placed in the stall state. 18.3.20 transceiver control register (xvercr) the transceiver control register sets either the internal transceiver or external transceiver for use. bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 xveroff 0 r/w transceiver control 1: the internal transceiver function is stopped and a digital signal for the external transceiver is output from the port. 0: the internal transceiver is operated. rev. 1.0, 11/02, page 454 of 690 18.4 operation 18.4.1 cable connection cable disconnected vbus pin = 0 v udc core reset usb cable connection ifr1.vbus = 1 usb bus connection interrupt udc core reset release bus reset reception ifr0.brst = 1 bus reset interrupt wait for setup command reception complete interrupt usb function application general output port d+ pull-up enabled? usb module interrupt setting as soon as preparations are completed, enable d+ pull-up in general output port clear vbus flag (ifr1.vbus) firmware preparations for start of usb communication clear bus reset flag (ifr0.brst) clear fifos (ep0, ep1, ep2, ep3) yes no initial settings wait for setup command reception complete interrupt interrupt request interrupt request figure 18.2 cable connection operation the above flowchart shows the operation in the case of in section 18.8, example of usb external circuitry. in applications that do not require usb cable connection to be detected, processing by the usb bus connection interrupt is not necessary. preparations should be made with the bus-reset interrupt. rev. 1.0, 11/02, page 455 of 690 18.4.2 cable disconnection usb function application cable connected vbus pin = 1 usb cable disconnection vbus pin = 0 udc core reset end figure 18.3 cable disconnection operation the above flowchart shows the operation in section 18.8, example of usb external circuitry. 18.4.3 control transfer control transfer consists of three stages: setup, data (not always included), and status (figure 18.4). the data stage comprises a number of bus transactions. operation flowcharts for each stage are shown below. control-in setup stage data stage status stage control-out no data setup(0) data0 setup(0) data0 setup(0) data0 in(1) data1 out(1) data1 in(0) data0 out(0) . . . . . . data0 in(0/1) data0/1 out(0/1) data0/1 out(1) data1 in(1) data1 in(1) data1 figure 18.4 transfer stages in control transfer rev. 1.0, 11/02, page 456 of 690 1. setup stage usb function application setup token reception receive 8-byte command data in ep0s to data stage set setup command reception complete flag (ifr0.setup ts = 1) automatic processing by this module clear setup ts flag (ifr0.setup ts = 0) clear ep0i fifo (clr.ep0iclr = 1) clear ep0o fifo (clr.ep0oclr = 1) read 8-byte data from ep0s decode command data determine data stage direction * 1 write 1 to ep0s read complete bit (trg.ep0s rdfn = 1) to control-in data stage to control-out data stage command to be processed by application? interrupt request yes no notes: 1 in the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.). 2 when the transfer direction is control-out, the ep0i transfer request interrupt required in the status stage should be enabled here. when the transfer direction is control-in, this interrupt is not required and should be disabled. * 2 figure 18.5 setup stage operation rev. 1.0, 11/02, page 457 of 690 2. data stage (control-in) usb function application in token reception data transmission to host set ep0i transmission complete flag (ifr0.ep0i ts = 1) from setup stage write data to ep0i data register (epdr0i) write 1 to ep0i packet enable bit (trg.ep0i pkte = 1) clear ep0i transmission complete flag (ifr0.ep0i ts = 0) write 1 to ep0i packet enable bit (trg.ep0i pkte = 1) write data to ep0i data register (epdr0i) 1 written to trg.ep0s rdfn? valid data in ep0i fifo? nack nack no no yes yes ack interrupt request figure 18.6 data stage (control-in) operation the application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. if the result of command data analysis is that the data stage is in- transfer, one packet of data to be sent to the host is written to the fifo. if there is more data to be sent, this data is written to the fifo after the data written first has been sent to the host (ep0its bit in ifr0 = 1). the end of the data stage is identified when the host transmits an out token and the status stage is entered. note: if the size of the data transmitted by the function is smaller than the data size requested by the host, the function indicates the end of the data stage by returning to the host a packet shorter than the maximum packet size. if the size of the data transmitted by the function is an integral multiple of the maximum packet size, the function indicates the end of the data stage by transmitting a zero-length packet. rev. 1.0, 11/02, page 458 of 690 3. data stage (control-out) usb function application out token reception data reception from host out token reception set ep0o reception complete flag (ifr0.ep0o ts = 1) clear ep0o reception complete flag (ifr0.ep0o ts = 0) read data from ep0o receive data size register (epsz0o) write 1 to ep0o read complete bit (trg.ep0o rdfn = 1) read data from ep0o data register (epdr0o) 1 written to trg.ep0s rdfn? 1 written to trg.ep0o rdfn? nack nack ack no yes no yes interrupt request figure 18.7 data stage (control-out) operation the application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. if the result of command data analysis is that the data stage is out- transfer, the application waits for data from the host, and after data is received (ep0ots bit in ifr0 = 1), reads data from the fifo. next, the application writes 1 to the ep0o read complete bit, empties the receive fifo, and waits for reception of the next data. the end of the data stage is identified when the host transmits an in token and the status stage is entered. rev. 1.0, 11/02, page 459 of 690 4. status stage (control-in) usb function application out token reception 0-byte reception from host end of control transfer set ep0o reception complete flag (ifr0.ep0o ts = 1) clear ep0o reception complete flag (ifr0.ep0o ts = 0) write 1 to ep0o read complete bit (trg.ep0o rdfn = 1) end of control transfer ack interrupt request figure 18.8 status stage (control-in) operation the control-in status stage starts with an out token from the host. the application receives 0-byte data from the host, and ends control transfer. rev. 1.0, 11/02, page 460 of 690 5. status stage (control-out) usb function application in token reception 0-byte transmission to host end of control transfer set ep0i transmission complete flag (ifr0.ep0i ts = 1) clear ep0i transfer request flag (ifr0.ep0i tr = 0) write 1 to ep0i packet enable bit (trg.ep0i pkte = 1) clear ep0i transmission complete flag (ifr0.ep0i ts = 0) end of control transfer valid data in ep0i fifo? ack yes no nack interrupt request interrupt request figure 18.9 status stage (control-out) operation the control-out status stage starts with an in token from the host. when an in-token is received at the start of the status stage, there is not yet any data in the ep0i fifo, and so an ep0i transfer request interrupt is generated. the application recognizes from this interrupt that the status stage has started. next, in order to transmit 0-byte data to the host, 1 is written to the ep0i packet enable bit but no data is written to the ep0i fifo. as a result, the next in token causes 0-byte data to be transmitted to the host, and control transfer ends. after the application has finished all processing relating to the data stage, 1 should be written to the ep0i packet enable bit. rev. 1.0, 11/02, page 461 of 690 18.4.4 ep1 bulk-out transfer (dual fifos) usb function application out token reception data reception from host set ep1 fifo full status (ifr0.ep1 full = 1) clear ep1 fifo full status (ifr0.ep1 full = 0) read ep1 receive data size register (epsz1) read data from ep1 data register (epdr1) write 1 to ep1 read complete bit (trg.ep1 rdfn = 1) space in ep1 fifo? no yes both ep1 fifos empty? no yes nack ack interrupt request interrupt request figure 18.10 ep1 bulk-out transfer operation ep1 has two 64-byte fifos, but the user can receive data and read receive data without being aware of this dual-fifo configuration. when one fifo is full after reception is completed, the ep1full bit in ifr0 is set. after the first receive operation into one of the fifos when both fifos are empty, the other fifo is empty, and so the next packet can be received immediately. when both fifos are full, nack is returned to the host automatically. when reading of the receive data is completed following data reception, 1 is written to the ep1rdfn bit in trg. this operation empties the fifo that has just been read, and makes it ready to receive the next packet. rev. 1.0, 11/02, page 462 of 690 18.4.5 ep2 bulk-in transfer (dual fifos) usb function application in token reception data transmission to host clear ep2 transfer request flag (ifr0.ep2 tr = 0) enable ep2 fifo empty interrupt (ier0.ep2 empty = 1) ier0.ep2 empty interrupt write one packet of data to ep2 data register (epdr2) write 1 to ep2 packet enable bit (trg.ep2 pkte = 1) set ep2 empty status (ifr0.ep2 empty = 1) valid data in ep2 fifo? nack ack interrupt request yes no clear ep2 empty status (ifr0.ep2 empty = 0) space in ep2 fifo? no yes interrupt request figure 18.11 ep2 bulk-in transfer operation ep2 has two 64-byte fifos, but the user can transmit data and write transmit data without being aware of this dual-fifo configuration. however, one data write is performed for one fifo. for example, even if both fifos are empty, it is not possible to perform ep2pkte at one time after consecutively writing 128 bytes of data. ep2pkte must be performed for each 64-byte write. when performing bulk-in transfer, as there is no valid data in the fifos on reception of the first in token, an ep2tr bit interrupt in ifr0 is requested. with this interrupt, 1 is written to the ep2empty bit in ier0, and the ep2 fifo empty interrupt is enabled. at first, both ep2 fifos are empty, and so an ep2 fifo empty interrupt is generated immediately. the data to be transmitted is written to the data register using this interrupt. after the first transmit data write for one fifo, the other fifo is empty, and so the next transmit data can be written to the other fifo immediately. when both fifos are full, ep2 empty is cleared to 0. if at least one fifo is empty, the ep2empty bit in ifr0 is set to 1. when ack is returned from the host after rev. 1.0, 11/02, page 463 of 690 data transmission is completed, the fifo used in the data transmission becomes empty. if the other fifo contains valid transmit data at this time, transmission can be continued. when transmission of all data has been completed, write 0 to the ep2empty bit in ier0 and disable interrupt requests. 18.4.6 ep3 interrupt-in transfer usb function application in token reception data transmission to host set ep3 transmission complete flag (ifr1.ep3 ts = 1) write data to ep3 data register (epdr3) write 1 to ep3 packet enable bit (trg.ep3 pkte = 1) clear ep3 transmission complete flag (ifr1.ep3 ts = 0) write data to ep3 data register (epdr3) write 1 to ep3 packet enable bit (trg.ep3 pkte = 1) valid data in ep3fifo? is there data for transmission to host? is there data for transmission to host? no yes no yes no yes nack ack note: this flowchart shows just one example of interrupt transfer processing. other possibilities include an operation flow in which, if there is data to be transferred, the ep3 de bit in the data status register is referenced to confirm that the fifo is empty, and then data is written to the fifo. interrupt request figure 18.12 operation of ep3 interrupt-in transfer rev. 1.0, 11/02, page 464 of 690 18.5 processing of usb standard commands and class/vendor commands 18.5.1 processing of commands transmitted by control transfer a command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. whether command decoding is required on the application side is indicated in table 18.2 below. table 18.2 command decoding on application side decoding not necessary on application side decoding necessary on application side clear feature get configuration get interface get status set address set configuration set feature set interface get descriptor class/vendor command set descriptor sync frame if decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed automatically. no processing is necessary by the user. an interrupt is not generated in this case. if decoding is necessary on the application side, this module stores the command in the ep0s fifo. after reception is completed successfully, the ifr0/setup ts flag is set and an interrupt request is generated. in the interrupt routine, eight bytes of data must be read from the ep0s data register (epdr0s) and decoded by firmware. the necessary data stage and status stage processing should then be carried out according to the result of the decoding operation. rev. 1.0, 11/02, page 465 of 690 18.6 stall operations 18.6.1 overview this section describes stall operations in this module. there are two cases in which the usb function module stall function is used: ? when the application forcibly stalls an endpoint for some reason ? when a stall is performed automatically within the usb function module due to a usb specification violation the usb function module has internal status bits that hold the status (stall or non-stall) of each endpoint. when a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. these bits cannot be cleared by the application; they must be cleared with a clear feature command from the host. 18.6.2 forcible stall by application the application uses the epstl register to issue a stall request for the usb function module. when the application wishes to stall a specific endpoint, it sets the corresponding bit in epstl (1- 1 in figure 18.13). the internal status bits are not changed at this time. when a transaction is sent from the host for the endpoint for which the epstl bit was set, the usb function module references the internal status bit, and if this is not set, references the corresponding bit in epstl (1-2 in figure 18.13). if the corresponding bit in epstl is set, the usb function module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 18.13). if the corresponding bit in epstl is not set, the internal status bit is not changed and the transaction is accepted. once an internal status bit is set, it remains set until cleared by a clear feature command from the host, without regard to the epstl register. even after a bit is cleared by the clear feature command (3-1 in figure 18.13), the usb function module continues to return a stall handshake while the bit in epstl is set, since the internal status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 18.13). to clear a stall, therefore, it is necessary for the corresponding bit in epstl to be cleared by the application, and also for the internal status bit to be cleared with a clear feature command (2-1, 2-2, and 2-3 in figure 18.13). rev. 1.0, 11/02, page 466 of 690 (1) transition from normal operation to stall (1-1) transaction request usb reference (1-2) stall handshake stall to (2-1) or (3-1) normal status restored (1-3) (2) when clear feature is sent after epstl is cleared (2-1) stall handshake transaction request (2-2) clear feature command clear feature command (2-3) (3) when clear feature is sent before epstl is cleared to 0 (3-1) 1. 1 written to epstl by application 1. in/out token received from host 2. epstl referenced 1. transmission of stall handshake 1. internal status bit cleared to 0 1. internal status bit cleared to 0 2. epstl not changed 1. 1 set in epstl 2. internal status bit set to 1 3. transmission of stall handshake 1. epstl cleared to 0 by application 2. in/out token received from host 3. internal status bit already set to 1 4. epstl not referenced 5. internal status bit not changed to (1-2) internal status bit 0 epstl 0 1 internal status bit 0 epstl 1 internal status bit 0 1 epstl 1 internal status bit 1 epstl 1 0 internal status bit 1 epstl 0 internal status bit 1 0 epstl 0 internal status bit 1 0 epstl 1 figure 18.13 forcible stall by application rev. 1.0, 11/02, page 467 of 690 18.6.3 automatic stall by usb function module when a stall setting is made with the set feature command, or in the event of a usb specification violation, the usb function module automatically sets the internal status bit for the relevant endpoint without regard to the epstl register, and returns a stall handshake (1-1 in figure 18.14). once an internal status bit is set, it remains set until cleared by a clear feature command from the host, without regard to the epstl register. after a bit is cleared by the clear feature command, epstl is referenced (3-1 in figure 18.14). the usb function module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 18.14). to clear a stall, therefore, the internal status bit must be cleared with a clear feature command (3-1 in figure 18.14). if set by the application, epstl should also be cleared (2-1 in figure 18.14). (1) transition from normal operation to stall (1-1) (2) when transaction is performed when internal status bit is set, and clear feature is sent (2-1) stall handshake transaction request stall handshake (2-2) clear feature command (3) when clear feature is sent before transaction is performed (3-1) 1. in case of usb specification violation, etc., usb function module stalls endpoint automatically 1. transmission of stall handshake 1. internal status bit cleared to 0 2. epstl not changed 1. epstl cleared to 0 by application 2. in/out token received from host 3. internal status bit already set to 1 4. epstl not referenced 5. internal status bit not changed normal status restored internal status bit 0 1 epstl 0 internal status bit 1 epstl 0 internal status bit 1 epstl 0 internal status bit 1 0 epstl 0 stall status maintained to (2-1) or (3-1) figure 18.14 automatic stall by usb function module rev. 1.0, 11/02, page 468 of 690 18.7 dma transfer 18.7.1 overview dma transfer can be performed for endpoints 1 and 2 in this module. note that word or longword data cannot be transferred. when endpoint 1 holds at least one byte of valid receive data, a dma request for endpoint 1 is generated. when endpoint 2 holds no valid data, a dma request for endpoint 2 is generated. if the dma transfer is enabled by setting the ep1dmae bit to 1 in the dma transfer setting register, zero-length data reception at endpoint 1 is ignored. when the dma transfer is enabled, the rdfn bit for ep1 and pkte bit for ep2 do not need to be set to 1 in trg (note that the pkte bit must be set to 1 when the transfer data is less than the maximum number of bytes). when all the data received at ep1 is read, the fifo automatically enters the empty state. when the maximum number of bytes (64 bytes) are written to the ep2 fifo, the fifo automatically enters the full state, and the data in the fifo can be transmitted (see figures 18.15 and 18.16). 18.7.2 dma transfer for endpoint 1 when the data received at ep1 is transferred by the dmac, the usb function module automatically performs the same processing as writing 1 to the rdfn bit in trg if the currently selected fifo becomes empty. accordingly, in dma transfer, do not write 1 to the rdfn bit in trg. if the user writes 1 to the rdfn bit in dma transfer, correct operation cannot be guaranteed. figure 18.15 shows an example of receiving 150 bytes of data from the host. in this case, internal processing which is the same as writing 1 to the rdfn bit in trg is automatically performed three times. this internal processing is performed when the currently selected data fifo becomes empty. accordingly, this processing is automatically performed both when 64-byte data is sent and when data less than 64 bytes is sent. rdfn (automatically performed) rdfn (automatically performed) rdfn (automatically performed) 64 bytes 64 bytes 22 bytes figure 18.15 rdfn bit operation for ep1 rev. 1.0, 11/02, page 469 of 690 18.7.3 dma transfer for endpoint 2 when the transmit data at ep2 is transferred by the dmac, the usb function module automatically performs the same processing as writing 1 to the pkte bit in trg if the currently selected fifo (64 bytes) becomes full. accordingly, to transfer data of a multiple of 64 bytes, the user need not write 1 to the pkte bit. to transfer data of less than 64 bytes, the user must write 1 to the pkte bit using the dma transfer end interrupt of the on-chip dmac. if the user writes 1 to the pkte bit when the maximum number of bytes (64 bytes) are transferred, correct operation cannot be guaranteed. figure 18.16 shows an example for transmitting 150 bytes of data to the host. in this case, internal processing which is the same as writing 1 to the pkte bit in trg is automatically performed twice. this internal processing is performed when the currently selected data fifo becomes full. accordingly, this processing is automatically performed only when 64-byte data is sent. when the last 22 bytes are sent, the internal processing for writing 1 to the pkte bit is not performed, and the user must write 1 to the pkte bit by software. in this case, the application has no more data to transfer but the usb function module continues to output dma requests for ep2 as long as the fifo has an empty space. when all data has been transferred, write 0 to the ep2dmae bit in dmar to cancel dma requests for ep2. pkte (automatically performed) pkte (automatically performed) pkte is not performed execute by dma transfer end interrupt (user) 64 bytes 64 bytes 22 bytes figure 18.16 pkte bit operation for ep2 rev. 1.0, 11/02, page 470 of 690 18.8 example of usb external circuitry 1. usb transceiver a usb transceiver ic (such as a pdiusbp11) should be connected externally when no internal transceiver is used. the usb transceiver manufacturer should be consulted concerning the recommended circuit from the usb transceiver to the usb connector, etc. 2. d+ pull-up control in a system where it is wished to disable usb host/hub connection notification (d+ pull-up) (during high-priority processing or initialization processing, for example), d+ pull-up should be controlled using a general output port. however, if a usb cable is already connected to the host/hub and d+ pull-up is prohibited, d+ and d? will both go low (both of d+ and d? pulled down on the host/hub side) and the usb module will mistakenly identify this as reception of a usb bus reset from the host. therefore, the d+ pull-up control signal and vbus pin input signal should be controlled using a general output port and the usb cable vbus (and circuit) as shown in figure 18.17. (the udc core in this lsi maintains the powered state when the vbus pin is low, regardless of the d+/d? state.) 3. detection of usb cable connection/disconnection as usb states, etc., are managed by hardware in this module, a vbus signal that recognizes connection/disconnection is necessary. the power supply signal (vbus) in the usb cable is used for this purpose. however, if the cable is connected to the usb host/hub when the function (system installing this lsi) power is off, a voltage (5 v) will be applied from the usb host/hub. therefore, an ic (such as an hd74lv1g08a or 2g08a) that allows voltage application when the system power is off should be connected externally. rev. 1.0, 11/02, page 471 of 690 vbus extal_usb vbus gnd d+ d+ d- d- 5v 3v general output port, etc. this lsi usb module 48 mhz ic allowing voltage application when system (lsi) power is off ic allowing voltage application when system (lsi) power is off usb connector usb cable note: operation is not guaranteed with this sample circuit. if external surge and esd noise countermeasures are required for the system, a protective diode or the noise canceler should be used for this purpose. figure 18.17 example of usb function module external circuitry (internal transceiver) rev. 1.0, 11/02, page 472 of 690 vbus vbus txenl txdmns txdpls xvdata dpls gnd dmns suspnd + - suspnd pdiusbp11 etc vm vp rcv speed vmo vpo d+ d- 5v 3v general output port, etc. usb module ic allowing voltage application when system (lsi) power is off ic allowing voltage application when system (lsi) power is off usb connector usb cable note: operation is not guaranteed with this sample circuit. if external surge and esd noise countermeasures are required for the system, a protective diode or the noise canceler should be used for this purpose. this lsi extal_usb 48 mhz figure 18.18 example of usb function module external circuitry (external transceiver) rev. 1.0, 11/02, page 473 of 690 18.9 usage notes 18.9.1 receiving setup data note the following for epdr0s that receives 8-byte setup data: 1. as a latest setup command must be received in high priority, the write from the usb bus takes priority over the read from the cpu. if the next setup command reception is started while the cpu is reading data after the data is received, the read from the cpu is forcibly terminated. therefore, the data read after reception is started becomes invalid. 2. epdr0s must always be read in 8-byte units. if the read is terminated at a midpoint, the data received at the next setup cannot be read correctly. 18.9.2 clearing the fifo if a usb cable is disconnected during data transfer, the data being received or transmitted may remain in the fifo. when disconnecting a usb cable, clear the fifo. while a fifo is transferring data, it must not be cleared. 18.9.3 overreading and overwriting the data registers note the following when reading or writing to a data register of this module. (1) receive data registers the receive data registers must not be read exceeding the valid amount of receive data, that is, the number of bytes indicated by the receive data size register. even for epdr1 which has double fifo buffers, the maximum data to be read at one time is 64 bytes. after the data is read from the current valid fifo buffer, be sure to write 1 to ep1rdfn in trg, which switches the valid buffer, updates the receive data size to the new number of bytes, and enables the next data to be received. (2) transmit data registers the transmit data registers must not be written to exceeding the maximum packet size. even for epdr2 which has double fifo buffers, write data within the maximum packet size at one time. after the data is written, write 1 to pkte in trg to switch the valid buffer and enable the next data to be written. data must not be continuously written to the two fifo buffers. rev. 1.0, 11/02, page 474 of 690 18.9.4 assigning interrupt sources to ep0 the ep0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in ifr0 must be assigned to the same interrupt signal with isr0. the other interrupt sources have no limitations. 18.9.5 clearing the fifo when dma transfer is enabled the endpoint 1 data register (epdr1) cannot be cleared when dma transfer for endpoint 1 is enabled (ep1 dmae in dmar = 1). cancel dma transfer before clearing the register. 18.9.6 notes on tr interrupt note the following when using the transfer request interrupt (tr interrupt) for in transfer to ep0i, ep2, or ep3. the tr interrupt flag is set if the fifo for the target ep has no data when the in token is sent from the usb host. however, at the timing shown in figure 18.19, multiple tr interrupts occur successively. take appropriate measures against malfunction in such a case. note: this module determines whether to return nak if the fifo of the target ep has no data when receiving the in token, but the tr interrupt flag is set only after a nak handshake is sent. if the next in token is sent before pkte of trg is written to, the tr interrupt flag is set again. cpu host in token in token in token sets tr flag (sets the flag again) sets tr flag determines whether to return nak transmits data tr interrupt routine clear tr flag writes transmit data trg. pkte tr interrupt routine usb nak determines whether to return nak nak ack figure 18.19 tr interrupt flag set timing rev. 1.0, 11/02, page 475 of 690 section 19 pin function controller 19.1 overview the pin function controller (pfc) consists of registers to select the pin functions and i/o directions of multiplex pins. pin functions and i/o directions can be individually selected for every pin regardless of the lsi operating mode. table 19.1 lists the multiplex pins of this lsi. table 19.1 multiplex pins port port function (related module) other functions (related module) a pta7 input/output (port)/pint7 input (intc) d23 input/output (bsc) a pta6 input/output (port)/pint6 input (intc) d22 input/output (bsc) a pta5 input/output (port)/pint5 input (intc) d21 input/output (bsc) a pta4 input/output (port)/pint4 input (intc) d20 input/output (bsc) a pta3 input/output (port)/pint3 input (intc) d19 input/output (bsc) a pta2 input/output (port)/pint2 input (intc) d18 input/output (bsc) a pta1 input/output (port)/pint1 input (intc) d17 input/output (bsc) a pta0 input/output (port)/pint0 input (intc) d16 input/output (bsc) b ptb7 input/output (port)/pint15 input (intc) d31 input/output (bsc) b ptb6 input/output (port)/pint14 input (intc) d30 input/output (bsc) b ptb5 input/output (port)/pint13 input (intc) d29 input/output (bsc) b ptb4 input/output (port)/pint12 input (intc) d28 input/output (bsc) b ptb3 input/output (port)/pint11 input (intc) d27 input/output (bsc) b ptb2 input/output (port)/pint10 input (intc) d26 input/output (bsc) b ptb1 input/output (port)/pint9 input (intc) d25 input/output (bsc) b ptb0 input/output (port)/pint8 input (intc) d24 input/output (bsc) c ptc7 input/output (port) cs6a output (bsc) c ptc6 input/output (port) cs5a output (bsc) c ptc5 input/output (port) cs4 output (bsc) c ptc4 input/output (port) cs3 output (bsc) c ptc3 input/output (port) cs2 output (bsc) c ptc2 input/output (port) we3 output (bsc)/dqmuu output (bsc)/ ah output (bsc) c ptc1 input/output (port) we2 output (bsc)/dqmul output (bsc) c ptc0 input/output (port) bs output (bsc) rev. 1.0, 11/02, page 476 of 690 port port function (related module) other functions (related module) d ptd7 input/output (port) cs6b output (bsc) d ptd6 input/output (port) cs5b output (bsc) d ptd5 input (port) nf * 1 d ptd4 input/output (port) cke output (bsc) d ptd3 input/output (port) casu output (bsc) d ptd2 input/output (port) casl output (bsc) d ptd1 input/output (port) rasu output (bsc) d ptd0 input/output (port) rasl output (bsc) e pte7 input/output (port) ? e pte6 input/output (port) tclk input (tmu) e pte5 input/output (port) status1 output (cpg) / cts0 input (scif0) e pte4 input/output (port) status0 output (cpg) / rts0 output (scif0) e pte3 input/output (port) tend0 output (dmac) e pte2 input/output (port) irq5 input (intc) e pte1 input/output (port) dack1 output (dmac) e pte0 input/output (port) dack0 output (dmac) f ptf7 input/output (port) asemd0 input f ptf6 input/output (port) asebrkak output f ptf5 input/output (port) tdo output (h-udi) f ptf4 input/output (port) audsync output (aud) f ptf3 input/output (port) audata3 output (aud) /to3 output (tpu) f ptf2 input/output (port) audata2 output (aud) /to2 output (tpu) f ptf1 input/output (port) audata1 output (aud) /to1 output (tpu) f ptf0 input/output (port) audata0 output (aud) /to0 output (tpu) g ptg7 input/output (port) wait input (bsc) g ptg6 input/output (port) breq input (bsc) g ptg5 input/output (port) back output (bsc) g ptg4 input/output (port) audck output (aud) g ptg3 input/output (port) trst input (h-udi) g ptg2 input/output (port) tms input (h-udi) g ptg1 input/output (port) tck input (h-udi) g ptg0 input/output (port) tdi input (h-udi) rev. 1.0, 11/02, page 477 of 690 port port function (related module) other functions (related module) h pth6 input/output (port) dreq1 input (dmac) h pth5 input/output (port) dreq0 input (dmac) h pth4 input/output (port) irq4 input (intc) h pth3 input/output (port) irq3 input (intc)/ irl3 input (intc) h pth2 input/output (port) irq2 input (intc)/ irl2 input (intc) h pth1 input/output (port) irq1 input (intc)/ irl1 input (intc) h pth0 input/output (port) irq0 input (intc)/ irl0 input (intc) j ptj7 output (port) nf * 1 j ptj6 output (port) nf * 1 j ptj5 output (port) nf * 1 j ptj4 output (port) nf * 1 j ptj3 output (port) nf * 1 j ptj2 output (port) nf * 1 j ptj1 output (port) nf * 1 j ptj0 output (port) nf * 1 k ptk7 input/output (port) a25 output (bsc) k ptk6 input/output (port) a24 output (bsc) k ptk5 input/output (port) a23 output (bsc) k ptk4 input/output (port) a22 output (bsc) k ptk3 input/output (port) a21 output (bsc) k ptk2 input/output (port) a20 output (bsc) k ptk1 input/output (port) a19 output (bsc) k ptk0 input/output (port) a0 output (bsc) l ptl3 input (port) an3 input (adc) l ptl2 input (port) an2 input (adc) l ptl1 input (port) an1 input (adc) l ptl0 input (port) an0 input (adc) m ptm6 input/output (port) vbus input (usb) m ptm4 input (port) nf * 1 m ptm3 input/output (port) ? m ptm2 input/output (port) ? m ptm1 input/output (port) ? m ptm0 input/output (port) ? rev. 1.0, 11/02, page 478 of 690 port port function (related module) other functions (related module) n ptn7 input/output (port) ? n ptn6 input/output (port) dpls input (usb) n ptn5 input/output (port) dmns input (usb) n ptn4 input/output (port) txdpls output (usb) n ptn3 input/output (port) txdmns output (usb) n ptn2 input/output (port) xvdata input (usb) n ptn1 input/output (port) txenl output (usb) n ptn0 input/output (port) suspnd output (usb) scpt scpt5 input/output (port) cts2 input (scif2) scpt scpt4 input/output (port) rts2 output (scif2) scpt scpt3 input/output (port) sck2 input/output (scif2) scpt scpt2 input (port) * 2 rxd2 input (scif2) scpt scpt2 output (port) * 2 txd2 output (scif2) scpt scpt1 input/output (port) sck0 input/output (scif0) scpt scpt0 input (port) * 2 rxd0 input (scif0)/irrx input (irda) scpt scpt0 output (port) * 2 txd0 output (scif0)/irtx output (irda) notes: * 1 the initial functions of nf (no function) pins are not assigned after power-on reset. specifies the functions with pin function controller (pfc). ptd5 and ptm4 must be pulled up. ptj[7:0] must be open except for the pins specified as port output pins. * 2 scpt0 and scpt2 each have two separate pins for input and output, however, a common data register is accessed. in table 19.1, pin functions in the shaded column can be used immediately after a power-on reset. rev. 1.0, 11/02, page 479 of 690 19.2 register descriptions the pfc has the following registers. for details on register addresses and access sizes, see section 24, list of registers. ? port a control register (pacr) ? port b control register (pbcr) ? port c control register (pccr) ? port d control register (pdcr) ? port e control register (pecr) ? port e control register 2 (pecr2) ? port f control register (pfcr) ? port f control register 2 (pfcr2) ? port g control register (pgcr) ? port h control register (phcr) ? port j control register (pjcr) ? port k control register (pkcr) ? port l control register (plcr) ? port m control register (pmcr) ? port n control register (pncr) ? port n control register 2 (pncr2) ? port sc control register (scpcr) rev. 1.0, 11/02, page 480 of 690 19.2.1 port a control register (pacr) pacr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pa7md1 pa7md0 0 0 r/w r/w pta7 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pa6md1 pa6md0 0 0 r/w r/w pta6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pa5md1 pa5md0 0 0 r/w r/w pta5 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pa4md1 pa4md0 0 0 r/w r/w pta4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pa3md1 pa3md0 0 0 r/w r/w pta3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 481 of 690 bit bit name initial value r/w description 5 4 pa2md1 pa2md0 0 0 r/w r/w pta2 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pa1md1 pa1md0 0 0 r/w r/w pta1 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pa0md1 pa0md0 0 0 r/w r/w pta0 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 19.2.2 port b control register (pbcr) pbcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pb7md1 pb7md0 0 0 r/w r/w ptb7 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pb6md1 pb6md0 0 0 r/w r/w ptb6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 482 of 690 bit bit name initial value r/w description 11 10 pb5md1 pb5md0 0 0 r/w r/w ptb5 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pb4md1 pb4md0 0 0 r/w r/w ptb4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pb3md1 pb3md0 0 0 r/w r/w ptb3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pb2md1 pb2md0 0 0 r/w r/w ptb2 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pb1md1 pb1md0 0 0 r/w r/w ptb1 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pb0md1 pb0md0 0 0 r/w r/w ptb0 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 483 of 690 19.2.3 port c control register (pccr) pccr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pc7md1 pc7md0 1 1 r/w r/w ptc7 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pc6md1 pc6md0 1 1 r/w r/w ptc6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pc5md1 pc5md0 0 0 r/w r/w ptc5 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pc4md1 pc4md0 0 0 r/w r/w ptc4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pc3md1 pc3md0 0 0 r/w r/w ptc3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 484 of 690 bit bit name initial value r/w description 5 4 pc2md1 pc2md0 0 0 r/w r/w ptc2 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pc1md1 pc1md0 0 0 r/w r/w ptc1 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pc0md1 pc0md0 0 0 r/w r/w ptc0 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 485 of 690 19.2.4 port d control register (pdcr) pdcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pd7md1 pd7md0 1 1 r/w r/w ptd7 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pd6md1 pd6md0 1 1 r/w r/w ptd6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pd5md1 pd5md0 0 0 r/w r/w ptd5 mode 00: nf 01: setting prohibited 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pd4md1 pd4md0 0 0 r/w r/w ptd4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pd3md1 pd3md0 1 1 r/w r/w ptd3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 486 of 690 bit bit name initial value r/w description 5 4 pd2md1 pd2md0 0 0 r/w r/w ptd2 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pd1md1 pd1md0 1 1 r/w r/w ptd1 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pd0md1 pd0md0 0 0 r/w r/w ptd0 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 487 of 690 19.2.5 port e control register (pecr) pecr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pe7md1 pe7md0 1 0 r/w r/w pte7 mode 00: setting prohibited 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pe6md1 pe6md0 1 0 r/w r/w pte6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pe5md1 pe5md0 0 0 r/w r/w pte5 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pe4md1 pe4md0 0 0 r/w r/w pte4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pe3md1 pe3md0 1 0 r/w r/w pte3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pe2md1 pe2md0 1 1 r/w r/w pte2 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 488 of 690 bit bit name initial value r/w description 3 2 pe1md1 pe1md0 1 0 r/w r/w pte1 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pe0md1 pe0md0 1 0 r/w r/w pte0 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 19.2.6 port e control register 2 (pecr2) pecr2 is an 8-bit readable/writable register that selects the pin function. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 pe5md2 0 r/w pe5 mode 2 this bit is valid when the pe5md[1:0] bits in pecr are set to b?00 (other functions). 0: status1 (cpg) 1: cts0 (scif0) 4 pe4md2 0 r/w pe4 mode 2 this bit is valid when the pe4md[1:0] bits in pecr are set to b?00 (other functions). 0: status0 (cpg) 1: rts0 (scif0) 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 489 of 690 19.2.7 port f control register (pfcr) pfcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pf7md1 pf7md0 0 0 r/w r/w ptf7 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pf6md1 pf6md0 1 * 0 r/w r/w ptf6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pf5md1 pf5md0 0 0 r/w r/w ptf5 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pf4md1 pf4md0 1 * 0 r/w r/w ptf4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pf3md1 pf3md0 1 * 0 r/w r/w ptf3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pf2md1 pf2md0 1 * 0 r/w r/w ptf2 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 490 of 690 bit bit name initial value r/w description 3 2 pf1md1 pf1md0 1 * 0 r/w r/w ptf1 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pf0md1 pf0md0 1 * 0 r/w r/w ptf0 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) note: * indicates the initial value when asemd0 = 1. when asemd0 = 0, the relevant bit becomes 0, and other functions is selected. 19.2.8 port f control register 2 (pfcr2) pfcr2 is an 8-bit readable/writable register that selects the pin function. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 pf3md2 0 r/w ptf3 mode 2 this bit is valid when the pf3md[1:0] bits in pfcr are set to b'00 (other functions). 0: audata3 (aud) 1: to3 (tpu) 2 pf2md2 0 r/w ptf2 mode 2 this bit is valid when the pf2md[1:0] bits in pfcr are set to b'00 (other functions). 0: audata2 (aud) 1: to2 (tpu) rev. 1.0, 11/02, page 491 of 690 bit bit name initial value r/w description 1 pf1md2 0 r/w ptf1 mode 2 this bit is valid when the pf1md[1:0] bits in pfcr are set to b'00 (other functions). 0: audata1 (aud) 1: to1 (tpu) 0 pf0md2 0 r/w ptf0 mode 2 this bit is valid when the pf0md[1:0] bits in pfcr are set to b'00 (other functions). 0: audata0 (aud) 1: to0 (tpu) 19.2.9 port g control register (pgcr) pgcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pg7md1 pg7md0 0 0 r/w r/w ptg7 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pg6md1 pg6md0 0 0 r/w r/w ptg6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pg5md1 pg5md0 0 0 r/w r/w ptg5 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 492 of 690 bit bit name initial value r/w description 9 8 pg4md1 pg4md0 1 * 0 r/w r/w ptg4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pg3md1 pg3md0 0 0 r/w r/w ptg3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pg2md1 pg2md0 0 0 r/w r/w ptg2 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pg1md1 pg1md0 0 0 r/w r/w ptg1 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pg0md1 pg0md0 0 0 r/w r/w ptg0 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) note: * indicates the initial value when asemd0 = 1. when asemd0 = 0, the relevant bit becomes 0, and other functions is selected. rev. 1.0, 11/02, page 493 of 690 19.2.10 port h control register (phcr) phcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 ph6md1 ph6md0 1 1 r/w r/w pth6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 ph5md1 ph5md0 1 1 r/w r/w pth5 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 ph4md1 ph4md0 0 0 r/w r/w pth4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 ph3md1 ph3md0 0 0 r/w r/w pth3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 ph2md1 ph2md0 0 0 r/w r/w pth2 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 494 of 690 bit bit name initial value r/w description 3 2 ph1md1 ph1md0 0 0 r/w r/w pth1 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 ph0md1 ph0md0 0 0 r/w r/w pth0 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 19.2.11 port j control register (pjcr) pjcr is a 16-bit readable/writable register that selects the pin function. bit bit name initial value r/w description 15 14 pj7md1 pj7md0 0 0 r/w r/w ptj7 mode 00: nf 01: port output 10: setting prohibited 11: setting prohibited 13 12 pj6md1 pj6md0 0 0 r/w r/w ptj6 mode 00: nf 01: port output 10: setting prohibited 11: setting prohibited 11 10 pj5md1 pj5md0 0 0 r/w r/w ptj5 mode 00: nf 01: port output 10: setting prohibited 11: setting prohibited rev. 1.0, 11/02, page 495 of 690 bit bit name initial value r/w description 9 8 pj4md1 pj4md0 0 0 r/w r/w ptj4 mode 00: nf 01: port output 10: setting prohibited 11: setting prohibited 7 6 pj3md1 pj3md0 0 0 r/w r/w ptj3 mode 00: nf 01: port output 10: setting prohibited 11: setting prohibited 5 4 pj2md1 pj2md0 0 0 r/w r/w ptj2 mode 00: nf 01: port output 10: setting prohibited 11: setting prohibited 3 2 pj1md1 pj1md0 0 0 r/w r/w ptj1 mode 00: nf 01: port output 10: setting prohibited 11: setting prohibited 1 0 pj0md1 pj0md0 0 0 r/w r/w ptj0 mode 00: nf 01: port output 10: setting prohibited 11: setting prohibited rev. 1.0, 11/02, page 496 of 690 19.2.12 port k control register (pkcr) pkcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pk7md1 pk7md0 0 0 r/w r/w ptk7 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pk6md1 pk6md0 0 0 r/w r/w ptk6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pk5md1 pk5md0 0 0 r/w r/w ptk5 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pk4md1 pk4md0 0 0 r/w r/w ptk4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pk3md1 pk3md0 0 0 r/w r/w ptk3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pk2md1 pk2md0 0 0 r/w r/w ptk2 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 497 of 690 bit bit name initial value r/w description 3 2 pk1md1 pk1md0 0 0 r/w r/w ptk1 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pk0md1 pk0md0 0 0 r/w r/w ptk0 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 498 of 690 19.2.13 port l control register (plcr) plcr is a 16-bit readable/writable register that selects the pin function. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 pl3md1 pl3md0 0 0 r/w r/w ptl3 mode 00: other functions (see table 19.1) 01: setting prohibited 10: setting prohibited 11: port input (pull-up mos: off) 5 4 pl2md1 pl2md0 0 0 r/w r/w ptl2 mode 00: other functions (see table 19.1) 01: setting prohibited 10: setting prohibited 11: port input (pull-up mos: off) 3 2 pl1md1 pl1md0 0 0 r/w r/w ptl1 mode 00: other functions (see table 19.1) 01: setting prohibited 10: setting prohibited 11: port input (pull-up mos: off) 1 0 pl0md1 pl0md0 0 0 r/w r/w ptl0 mode 00: other functions (see table 19.1) 01: setting prohibited 10: setting prohibited 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 499 of 690 19.2.14 port m control register (pmcr) pmcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 pm6md1 pm6md0 1 0 r/w r/w ptm6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11, 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 pm4md1 pm4md0 0 0 r/w r/w ptm4 mode 00: nf 01: setting prohibited 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pm3md1 pm3md0 1 0 r/w r/w ptm3 mode 00: setting prohibited 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pm2md1 pm2md0 1 0 r/w r/w ptm2 mode 00: setting prohibited 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 500 of 690 bit bit name initial value r/w description 3 2 pm1md1 pm1md0 1 0 r/w r/w ptm1 mode 00: setting prohibited 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pm0md1 pm0md0 1 0 r/w r/w ptm0 mode 00: setting prohibited 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 19.2.15 port n control register (pncr) pncr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pn7md1 pn7md0 1 0 r/w r/w ptn7 mode 00: setting prohibited 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pn6md1 pn6md0 1 0 r/w r/w ptn6 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pn5md1 pn5md0 1 0 r/w r/w ptn5 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 501 of 690 bit bit name initial value r/w description 9 8 pn4md1 pn4md0 1 0 r/w r/w ptn4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pn3md1 pn3md0 1 0 r/w r/w ptn3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pn2md1 pn2md0 1 0 r/w r/w ptn2 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pn1md1 pn1md0 1 0 r/w r/w ptn1 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pn0md1 pn0md0 1 0 r/w r/w ptn0 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 502 of 690 19.2.16 port n control register 2 (pncr2) pncr2 is an 8-bit readable/writable register that selects the pin function. bit bit name initial value r/w description 7? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 pn6md2 0 r/w ptn6 mode 2 this bit is valid when the pn6md[1:0] bits in pncr are set to b'00 (other functions). 0: setting prohibited 1: dpls (usb) 5 pn5md2 0 r/w ptn5 mode 2 this bit is valid when the pn5md[1:0] bits in pncr are set to b'00 (other functions). 0: setting prohibited 1: dmns (usb) 4 pn4md2 0 r/w ptn4 mode 2 this bit is valid when the pn4md[1:0] bits in pncr are set to b'00 (other functions). 0: setting prohibited 1: txdpls (usb) 3 pn3md2 0 r/w ptn3 mode 2 this bit is valid when the pn3md[1:0] bits in pncr are set to b'00 (other functions). 0: setting prohibited 1: txdmns (usb) 2 pn2md2 0 r/w ptn2 mode 2 this bit is valid when the pn2md[1:0] bits in pncr are set to b'00 (other functions). 0: setting prohibited 1: xvdata (usb) rev. 1.0, 11/02, page 503 of 690 bit bit name initial value r/w description 1 pn1md2 0 r/w ptn1 mode 2 this bit is valid when the pn1md[1:0] bits in pncr are set to b'00 (other functions). 0: setting prohibited 1: txenl (usb) 0 pn0md2 0 r/w ptn0 mode 2 this bit is valid when the pn0md[1:0] bits in pncr are set to b'00 (other functions). 0: setting prohibited 1: suspnd (usb) 19.2.17 port sc control register (scpcr) scpcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. the settings of scpcr become valid only when transmission/reception operation is disabled by the settings of scscr in the on-chip serial communication interface (scif). when the te bit in scscr_0 or scscr_2 of the scif is set to 1, the output status of ?other functions: txd0 or txd2? has priority for the setting of scpcr. similarly, when the re bit in scscr_0 or scscr_2 is set to 1, the input status of ?other functions: rxd0 or rxd2? has priority for the setting of scpcr. bit bit name initial value r/w description 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 10 scp5md1 scp5md0 0 0 r/w r/w scpt5 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) rev. 1.0, 11/02, page 504 of 690 bit bit name initial value r/w description 9 8 scp4md1 scp4md0 0 0 r/w r/w scpt4 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 scp3md1 scp3md0 0 0 r/w r/w scpt3 mode 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 scp2md1 scp2md0 0 0 r/w r/w scpt2 mode these bits select pin function and input pull-up mos control. when te = 0 and re = 0 in scscr_2, operation is as follows: 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) when te = 1 in scscr_2, the scpt2/txd2 pin functions as txd2. when re = 1 in scscr_2, the scpt2/rxd2 pin functions as rxd2. note: since two pins (txd2 and rxd2) are used to access one bit (scpt2), there is no combination of simultaneous input/output of scpt2. when port input is set (when bit scp2md1 is set to 1), the txd2 pin enters an output state when the te bit in scscr_2 is set to 1, whereas it enters high-impedance state when the te bit is cleared to 0. rev. 1.0, 11/02, page 505 of 690 bit bit name initial value r/w description 3 2 scp1md1 scp1md0 0 0 r/w r/w scpt1 mode these bits select pin function and input pull-up mos control. 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 scp0md1 scp0md0 0 0 r/w r/w scpt0 mode these bits select pin function and input pull-up mos control. when te = 0 and re = 0 in scscr_0, operation is as follows: 00: other functions (see table 19.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) when te = 1 in scscr_0, the scpt0/txd0 pin functions as txd0. when re = 1 in scscr_0, the scpt0/rxd0 pin functions as rxd0. note: since two pins (txd0 and rxd0) are used to access one bit (scpt0), there is no combination of simultaneous input/output of scpt0. when port input is set (when bit scp0md1 is set to 1), the txd0 pin enters an output state when the te bit in scscr_0 is set to 1, whereas it enters high-impedance state when the te bit is cleared to 0. rev. 1.0, 11/02, page 506 of 690 rev. 1.0, 11/02, page 507 of 690 section 20 i/o ports this lsi has fourteen i/o ports (ports a to h, j to n, and sc). all port pins are multiplexed with other pin functions (the pin function controller (pfc) handles the selection of pin functions and pull-up mos control). each port has a data register which stores data for the pins. 20.1 port a port a is an 8-bit input/output port with the pin configuration shown in figure 20.1. each pin has an input pull-up mos, which is controlled by the port a control register (pacr) in the pfc. port a pta7 (input/output)/d23 (input/output)/pint7 (input) pta6 (input/output)/d22 (input/output)/pint6 (input) pta5 (input/output)/d21 (input/output)/pint5 (input) pta4 (input/output)/d20 (input/output)/pint4 (input) pta3 (input/output)/d19 (input/output)/pint3 (input) pta2 (input/output)/d18 (input/output)/pint2 (input) pta1 (input/output)/d17 (input/output)/pint1 (input) pta0 (input/output)/d16 (input/output)/pint0 (input) figure 20.1 port a 20.1.1 register description port a has the following register. for details on the register address and access size, see section 24, list of registers. ? port a data register (padr) rev. 1.0, 11/02, page 508 of 690 20.1.2 port a data register (padr) padr is an 8-bit readable/writable register that stores data for pins pta7 to pta0. bits pa7dt to pa0dt correspond to pins pta7 to pta0. when the pin function is general output port, if the port is read, the value of the corresponding padr bit is returned directly. when the function is general input port, if the port is read the corresponding pin level is read. bit bit name initial value r/w description 7 to 0 pa7dt to pa0dt all 0 r/w table 20.1 shows the function of padr. table 20.1 port a data register (padr) read/write operations pacr state panmd1 panmd0 pin state read write 0 0 other function padr value data can be written to padr but no effect on pin state. 1 output padr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to padr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to padr but no effect on pin state. note: n = 0 to 7 20.2 port b port b is an 8-bit input/output port with the pin configuration shown in figure 20.2. each pin has an input pull-up mos, which is controlled by the port b control register (p bcr) in the pfc. port b ptb7 (input/output)/d31 (input/output)/pint15 (input) ptb6 (input/output)/d30 (input/output)/pint14 (input) ptb5 (input/output)/d29 (input/output)/pint13 (input) ptb4 (input/output)/d28 (input/output)/pint12 (input) ptb3 (input/output)/d27 (input/output)/pint11 (input) ptb2 (input/output)/d26 (input/output)/pint10 (input) ptb1 (input/output)/d25 (input/output)/pint9 (input) ptb0 (input/output)/d24 (input/output)/pint8 (input) figure 20.2 port b rev. 1.0, 11/02, page 509 of 690 20.2.1 register description port b has the following register. for details on the register address and access size, see section 24, list of registers. ? port b data register (pbdr) 20.2.2 port b data register (pbdr) pbdr is an 8-bit readable/writable register that stores data for pins ptb7 to ptb0. bits pb7dt to pb0dt correspond to pins ptb7 to ptb0. when the pin function is general output port, if the port is read the value of the corresponding pbdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 to 0 pb7dt to pb0dt all 0 r/w table 20.2 shows the function of pbdr. table 20.2 port b data register (pbdr) read/write operations pbcr state pbnmd1 pbnmd0 pin state read write 0 0 other function pbdr value data can be written to pbdr but no effect on pin state. 1 output pbdr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to pbdr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pbdr but no effect on pin state. note: n = 0 to 7 rev. 1.0, 11/02, page 510 of 690 20.3 port c port c is an 8-bit input/output port with the pin configuration shown in figure 20.3. each pin has an input pull-up mos, which is controlled by the port c control register (p ccr) in the pfc. port c ptc7 (input/output)/ (output) ptc6 (input/output)/ (output) ptc5 (input/output)/ (output) ptc4 (input/output)/ (output) ptc3 (input/output)/ (output) ptc2 (input/output)/ (output)/dqmuu (output)/ (output) ptc1 (input/output)/ (output)/dqmul (output) ptc0 (input/output)/ (output) figure 20.3 port c 20.3.1 register description port c has the following register. for details on the register address and access size, see section 24, list of registers. ? port c data register (pcdr) 20.3.2 port c data register (pcdr) pcdr is an 8-bit readable/writable register that stores data for pins ptc7 to ptc0. bits pc7dt to pc0dt correspond to pins ptc7 to ptc0. when the pin function is general output port, if the port is read, the value of the corresponding pcdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 to 0 pc7dt to pc0dt all 0 r/w table 20.3 shows the function of pcdr. rev. 1.0, 11/02, page 511 of 690 table 20.3 port c data register (pcdr) read/write operations pccr state pcnmd1 pcnmd0 pin state read write 0 0 other function pcdr value data can be written to pcdr but no effect on pin state. 1 output pcdr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to pcdr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pcdr but no effect on pin state. note: n = 0 to 7 20.4 port d port d is an 8-bit input/output port with the pin configuration shown in figure 20.4. each pin has an input pull-up mos, which is controlled by the port d control register (pdcr) in the pfc. port d ptd7 (input/output)/ (output) ptd6 (input/output)/ (output) ptd5 (input) /nf (input) ptd4 (input/output)/cke (output) ptd3 (input/output)/ (output) ptd2 (input/output)/ (output) ptd1 (input/output)/ (output) ptd0 (input/output)/ (output) figure 20.4 port d 20.4.1 register description port d has the following register. for details on the register address and access size, see section 24, list of registers. ? port d data register (pddr) 20.4.2 port d data register (pddr) pddr is an 8-bit readable/writable register that stores data for pins ptd7 to ptd0. bits pd7dt to pd0dt correspond to pins ptd7 to ptd0. when the pin function is general output port, if the port is read, the value of the corresponding pddr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. rev. 1.0, 11/02, page 512 of 690 bit bit name initial value r/w description 7 to 0 pd7dt to pd0dt all 0 r/w table 20.4 shows the function of pddr. table 20.4 port d data register (pddr) read/write operations pdcr state pdnmd1 pdnmd0 pin state read write 0 0 other function pddr value data can be written to pddr but no effect on pin state. 1 output pddr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to pddr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pddr but no effect on pin state. note: n = 0 to 4, 6, and 7 pdcr state pd5md1 pd5md0 pin state read write 0 0 nf pddr value data can be written to pddr but no effect on pin state. 1 setting prohibited ?? 1 0 input (pull-up mos on) pin state data can be written to pddr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pddr but no effect on pin state. rev. 1.0, 11/02, page 513 of 690 20.5 port e port e is an 8-bit input/output port with the pin configuration shown in figure 20.5. each pin has an input pull-up mos, which is controlled by the port e control register (pecr) in the pfc. port e pte7 (input/output) pte6 (input/output)/tclk (input) pte5 (input/output)/status1 (output)/ (input) pte4 (input/output)/status0 (output)/ (output) pte3 (input/output)/tend0 (output) pte2 (input/output)/irq5 (input) pte1 (input/output)/dack1 (output) pte0 (input/output)/dack0 (output) figure 20.5 port e 20.5.1 register description port e has the following register. for details on the register address and access size, see section 24, list of registers. ? port e data register (pedr) 20.5.2 port e data register (pedr) pedr is an 8-bit readable/writable register that stores data for pins pte7 to pte0. bits pe7dt to pe0dt correspond to pins pte7 to pte0. when the pin function is general output port, if the port is read, the value of the corresponding pedr bit is returned directly. when the function is general input port, if the port is read the corresponding pin level is read. bit bit name initial value r/w description 7 to 0 pe7dt to pe0dt all 0 r/w table 20.5 shows the function of pedr. rev. 1.0, 11/02, page 514 of 690 table 20.5 port e data register (pedr) read/write operations pecr state penmd1 penmd0 pin state read write 0 0 other function pedr value data can be written to pedr but no effect on pin state. 1 output pedr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to pedr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pedr but no effect on pin state. note: n = 0 to 7 20.6 port f port f is an 8-bit input port with the pin configuration shown in figure 20.6. each pin has an input pull-up mos, which is controlled by the port f control register (pfcr) in the pfc. port f ptf7 (input/output)/ (input) ptf6 (input/output)/ (output) ptf5 (input/output)/tdo (output) ptf4 (input/output)/audsync (output) ptf3 (input/output)/audata3 (output)/to3 (output) ptf2 (input/output)/audata2 (output)/to2 (output) ptf1 (input/output)/audata1 (output)/to1 (output) ptf0 (input/output)/audata0 (output)/to0 (output) figure 20.6 port f 20.6.1 register description port f has the following register. for details on the register address and access size, see section 24, list of registers. ? port f data register (pfdr) 20.6.2 port f data register (pfdr) pfdr is an 8-bit readable/writable register that stores data for pins ptf7 to ptf0. bits pf7dt to pf0dt correspond to pins ptf7 to ptf0. when the pin function is general output port, if the port is read, the value of the corresponding pfdr bit is returned directly. when the function is general input port, if the port is read the corresponding pin level is read. rev. 1.0, 11/02, page 515 of 690 bit bit name initial value r/w description 7 to 0 pf7dt to pf0dt all 0 r/w table 20.6 shows the function of pfdr. table 20.6 port f data register (pfdr) read/write operations pfcr state pfnmd1 pfnmd0 pin state read write 0 0 other function pfdr value data can be written to pfdr but no effect on pin state. 1 output pfdr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to pfdr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pfdr but no effect on pin state. note: n = 0 to 7 20.7 port g port g is an 8-bit input port with the pin configuration shown in figure 20.7. each pin has an input pull-up mos, which is controlled by the port g control register (pgcr) in the pfc. port g ptg5 (input/output)/ (output) ptg4 (input/output)/audck (output) ptg3 (input/output)/ (input) ptg2 (input/output)/tms (input) ptg1 (input/output)/tck (input) ptg0 (input/output)/tdi (input) ptg7 (input/output)/ (input) ptg6 (input/output)/ (input) figure 20.7 port g 20.7.1 register description port g has the following register. for details on the register address and access size, see section 24, list of registers. ? port g data register (pgdr) rev. 1.0, 11/02, page 516 of 690 20.7.2 port g data register (pgdr) pgdr is an 8-bit readable/writable register that stores data for pins ptg7 to ptg0. bits pg7dt to pg0dt correspond to pins ptg7 to ptg0. when the pin function is general output port, if the port is read, the value of the corresponding pgdr bit is returned directly. when the function is general input port, if the port is read the corresponding pin level is read. bit bit name initial value r/w description 7 to 0 pg7dt to pg0dt all 0 r/w table 20.7 shows the function of pgdr. table 20.7 port g data register (pgdr) read/write operations pgcr state pgnmd1 pgnmd0 pin state read write 0 0 other function pgdr value data can be written to pgdr but no effect on pin state. 1 output pgdr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to pgdr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pgdr but no effect on pin state. note: n = 0 to 7 20.8 port h port h is a 7-bit input/output port with the pin configuration shown in figure 20.8. each pin has an input pull-up mos, which is controlled by the port h control register (phcr) in the pfc. port h pth6 (input/output)/dreq1 (input) pth5 (input/output)/dreq0 (input) pth4 (input/output)/irq4 (input) pth3 (input/output)/irq3 (input)/ (input) pth2 (input/output)/irq2 (input)/ (input) pth1 (input/output)/irq1 (input)/ (input) pth0 (input/output)/irq0 (input)/ (input) figure 20.8 port h rev. 1.0, 11/02, page 517 of 690 20.8.1 register description port h has the following register. for details on the register address and access size, see section 24, list of registers. ? port h data register (phdr) 20.8.2 port h data register (phdr) phdr is an 8-bit readable/writable register that stores data for pins pth6 to pth0. bits ph6dt to ph0dt correspond to pins pth6 to pth0. when the pin function is general output port, if the port is read, the value of the corresponding phdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 to 0 ph6dt to ph0dt all 0 r/w table 20.8 shows the function of phdr. table 20.8 port h data register (phdr) read/write operations phcr state phnmd1 phnmd0 pin state read write 0 0 other function phdr value data can be written to phdr but no effect on pin state. 1 output phdr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to phdr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to phdr but no effect on pin state. note: n = 0 to 6 rev. 1.0, 11/02, page 518 of 690 20.9 port j port j is an 8-bit output port with the pin configuration shown in figure 20.9. port j ptj7 (output)/nf (output) ptj6 (output)/nf (output) ptj5 (output)/nf (output) ptj4 (output)/nf (output) ptj3 (output)/nf (output) ptj2 (output)/nf (output) ptj1 (output)/nf (output) ptj0 (output)/nf (output) figure 20.9 port j 20.9.1 register description port j has the following register. for details on the register address and access size, see section 24, list of registers. ? port j data register (pjdr) 20.9.2 port j data register (pjdr) pjdr is an 8-bit readable/writable register that stores data for pins ptj7 to ptj0. bits pj7dt to pj0dt correspond to pins ptj7 to ptj0. when the pin function is general output port, if the port is read, the value of the corresponding pjdr bit is returned directly. bit bit name initial value r/w description 7 to 0 pj7dt to pj0dt all 0 r/w table 20.9 shows the function of pjdr. rev. 1.0, 11/02, page 519 of 690 table 20.9 port j data register (pjdr) read/write operations pjcr state pjnmd1 pjnmd0 pin state read write 0 0 nf pjdr value data can be written to pjdr but no effect on pin state. 1 output pjdr value written data is output from the pin. 10setting prohibited ?? 1 setting prohibited ?? note: n = 0 to 7 20.10 port k port k is an 8-bit input/output port with the pin configuration shown in figure 20.10. each pin has an input pull-up mos, which is controlled by the port k control register (pkcr) in the pfc. port k ptk7 (input/output)/a25 (output) ptk6 (input/output)/a24 (output) ptk5 (input/output)/a23 (output) ptk4 (input/output)/a22 (output) ptk3 (input/output)/a21 (output) ptk2 (input/output)/a20 (output) ptk1 (input/output)/a19 (output) ptk0 (input/output)/a0 (output) figure 20.10 port k 20.10.1 register description port k has the following register. for details on the register address and access size, see section 24, list of registers. ? port k data register (pkdr) 20.10.2 port k data register (pkdr) pkdr is an 8-bit readable/writable register that stores data for pins ptk7 to ptk0. bits pk7dt to pk0dt correspond to pins ptk7 to ptk0. when the pin function is general output port, if the port is read, the value of the corresponding pkdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. rev. 1.0, 11/02, page 520 of 690 bit bit name initial value r/w description 7 to 0 pk7dt to pk0dt all 0 r/w table 20.10 shows the function of pkdr. table 20.10 port k data register (pkdr) read/write operations pkcr state pknmd1 pknmd0 pin state read write 0 0 other function pkdr value data can be written to pkdr but no effect on pin state. 1 output pkdr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to pkdr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pkdr but no effect on pin state. note: n = 0 to 7 20.11 port l port l is a 4-bit input port with the pin configuration shown in figure 20.11. port l ptl3 (input)/an3 (input) ptl2 (input)/an2 (input) ptl1 (input)/an1 (input) ptl0 (input)/an0 (input) figure 20.11 port l 20.11.1 register description port l has the following register. for details on the register address and access size, see section 24, list of registers. ? port l data register (pldr) rev. 1.0, 11/02, page 521 of 690 20.11.2 port l data register (pldr) pldr is an 8-bit read-only register that stores data for pins ptl3 to ptl0. bits pl3dt to pl0dt correspond to pins ptl3 to ptl0. if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. 3 to 0 pl3dt to pl0dt all 0 r table 20.11 shows the function of pldr. table 20.11 port l data register (pldr) read/write operation plcr state plnmd1 plnmd0 pin state read write 0 0 other function read as 0 invalid (no effect on pin state) 1 setting prohibited ?? 0 setting prohibited ?? 1 1 input (pull-up mos off) pin state invalid (no effect on pin state) note: n = 0 to 3 20.12 port m port m is a 6-bit input/output port with the pin configuration shown in figure 20.12. each pin has an input pull-up mos, which is controlled by the port m control register (pmcr) in the pfc. port m ptm6 (input/output)/vbus (input) ptm4 (input)/nf (input) ptm3 (input/output) ptm2 (input/output) ptm1 (input/output) ptm0 (input/output) figure 20.12 port m rev. 1.0, 11/02, page 522 of 690 20.12.1 register description port m has the following register. for details on the register address and access size, see section 24, list of registers. ? port m data register (pmdr) 20.12.2 port m data register (pmdr) pmdr is an 8-bit readable/writable register that stores data for pins ptm6 and ptm4 to ptm0. bits pm6dt and pm4dt to pm0dt correspond to pins ptm6 and ptm4 to ptm0. when the pin function is general output port, if the port is read, the value of the corresponding pmdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7? 0rreserved this bit is always read as 0. the write value should always be 0. 6 pm6dt 0 r/w table 20.12 shows the function of pmdr. 5? 0rreserved this bit is always read as 0. the write value should always be 0. 4 to 0 pm4dt to pm0dt all 0 r/w table 20.12 shows the function of pmdr. table 20.12 port m data register (pmdr) read/write operations pmcr state pmnmd1 pmnmd0 pin state read write 0 0 other function pmdr value data can be written to pmdr but no effect on pin state. 1 output pmdr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to pmdr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pmdr but no effect on pin state. note: n = 0 to 3 and 6 rev. 1.0, 11/02, page 523 of 690 pmcr state pm4md1 pm4md0 pin state read write 0 0 nf pmdr value data can be written to pmdr but no effect on pin state. 1 setting prohibited pmdr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to pmdr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pmdr but no effect on pin state. 20.13 port n port n is an 8-bit input/output port with the pin configuration shown in figure 20.13. each pin has an input pull-up mos, which is controlled by the port n control register (pncr) in the pfc. port n ptn7 (input/output) ptn6 (input/output)/dpls (input) ptn5 (input/output)/dmns (input) ptn4 (input/output)/txdpls (output) ptn3 (input/output)/txdmns (output) ptn2 (input/output)/xvdata (input) ptn1 (input/output)/txenl (output) ptn0 (input/output)/suspnd (output) figure 20.13 port n 20.13.1 register description port n has the following register. for details on the register address and access size, see section 24, list of registers. ? port n data register (pndr) 20.13.2 port n data register (pndr) pndr is an 8-bit readable/writable register that stores data for pins ptn7 to ptn0. bits pn7dt to pn0dt correspond to pins ptn7 to ptn0. when the pin function is general output port, if the port is read, the value of the corresponding pndr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. rev. 1.0, 11/02, page 524 of 690 bit bit name initial value r/w description 7 to 0 pn7dt to pn0dt all 0 r/w table 20.13 shows the function of pndr. table 20.13 port n data register (pndr) read/write operations pncr state pnnmd1 pnnmd0 pin state read write 0 0 other function pndr value data can be written to pndr but no effect on pin state. 1 output pndr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to pndr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to pndr but no effect on pin state. note: n = 0 to 7 20.14 sc port the sc port is an 8-bit input/output port with the pin configuration shown in figure 20.14. each pin has an input pull-up mos, which is controlled by the sc port control register (scpcr) in the pfc. sc port scpt5 (input/output)/ (input) scpt4 (input/output)/ (output) scpt3 (input/output)/sck2 (input/output) scpt2 (input) * /rxd2 (input) scpt2 (output) * /txd2 (output) scpt1 (input/output)/sck0 (input/output) scpt0 (input) * /rxd0 (input)/irrx (input) scpt0 (output) * /txd0 (output)/irtx (output) note: * scpt0 and scpt2 each have two separate pins for input and output, however, a common data register is accessed. figure 20.14 sc port rev. 1.0, 11/02, page 525 of 690 20.14.1 register description port sc has the following register. for details on the register address and access size, see section 24, list of registers. ? sc port data register (scpdr) 20.14.2 port sc data register (scpdr) scpdr is an 8-bit readable/writable that stores data for pins scpt5 to scpt0. bits scp5dt to scp0dt correspond to pins scpt5 to scpt0. when the pin function is general output port, if the port is read, the value of the corresponding scpdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. when the re bit of scscr_2 or scscr_0 in the serial communication interface with fifo (scif) is set to 1, the rxd2 and rxd0 pins become input pins, and their states can be read regardless of the setting of scpcr. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 to 0 scp5dt to scp0dt all 0 r/w table 20.14 shows the function of scpdr. table 20.14 sc port data register (scpdr) read/write operations ? scp1dr and scp3dr to scp5dr scpcr state scpnmd1 scpnmd0 pin state read write 0 0 other function scpdr value data can be written to scpdr but no effect on pin state. 1 output scpdr value written data is output from the pin. 1 0 input (pull-up mos on) pin state data can be written to scpdr but no effect on pin state. 1 input (pull-up mos off) pin state data can be written to scpdr but no effect on pin state. note: n= 1 and 3 to 5 rev. 1.0, 11/02, page 526 of 690 ? scp0dr and scp2dr scpcr state scpnmd1 scpnmd0 pin state read write 0 0 other function prohibited prohibited 1 txd: output rxd: input (cannot be read) scpdr value written data is output on txd pin. 1 0 txd: output high impedance rxd: input (pull-up mos on) rxd pin state data can be written to scpdr but no effect on pin state. 1 txd: output high impedance rxd: input (pull-up mos off) rxd pin state data can be written to scpdr but no effect on pin state. note: n= 0 and 2 the operations are not guaranteed when read and write operations are prohibited. adcms60a_000020020100 rev. 1.0, 11/02, page 527 of 690 section 21 a/d converter this lsi includes a 10-bit successive-approximation a/d converter allowing selection of up to four analog input channels. 21.1 features ? 10-bit resolution ? four input channels ? minimum conversion time: 8.5 s per channel (p = 33 mhz operation) ? three conversion modes ? single mode: a/d conversion on one channel ? multi mode: a/d conversion on one to four channels ? scan mode: continuous a/d conversion on one to four channels ? four 16-bit data registers ? a/d conversion results are transferred for storage into 16-bit data registers corresponding to the channels. ? sample-and-hold function ? interrupt source ? at the end of a/d conversion, an a/d conversion end interrupt (adi) can be requested. ? module standby mode can be set rev. 1.0, 11/02, page 528 of 690 figure 21.1 shows a block diagram of the a/d converter. 10-bit d/a addra addrb addrd bus interface peripheral data bus analog multi- plexer control circuit successive approxi- mation register + ? comparator sample-and- hold circuit adi interrupt signal av ss an0 an1 an2 an3 p /8 p /16 adcsr p /4 av cc adcsr: a/d control/status register addra: a/d data register a addrb: a/d data register b addrc: a/d data register c addrd: a/d data register d legend internal data bus addrc figure 21.1 block diagram of a/d converter rev. 1.0, 11/02, page 529 of 690 21.2 input/output pins table 21.1 summarizes the a/d converter?s pins. the av cc and av ss pins are the power supply for the analog circuits in the a/d converter. the av cc pin also functions as the a/d conversion reference voltage pin. table 21.1 pin configuration pin name abbreviation input/ output function analog power supply avcc input analog power supply and reference voltage for a/d conversion analog ground avss input analog ground and reference voltage for a/d conversion analog input 0 an0 input analog input 0 analog input 1 an1 input analog input 1 analog input 2 an2 input analog input 2 analog input 3 an3 input analog input 3 21.3 register descriptions the a/d converter has the following registers. for more information on addresses of registers and register states in the processing, see section 24, list of registers. ? a/d data register a (addra) ? a/d data register b (addrb) ? a/d data register c (addrc) ? a/d data register d (addrd) ? a/d control/status register (adcsr) rev. 1.0, 11/02, page 530 of 690 21.3.1 a/d data registers a to d (addra to addrd) the four a/d data registers (addra to addrd) are 16-bit read-only registers that store the results of a/d conversion. table 21.2 indicates the pairings of analog input channels and a/d data registers that store the results of a/d conversion. an a/d conversion produces 10-bit data, which is transferred for storage into bits 15 to 6 in the a/d data register corresponding to the selected channel. bits 5 to 0 of an a/d data register are reserved bits that are always read as 0. the a/d data registers are initialized to h'0000. table 21.2 analog input channels and a/d data registers analog input channel a/d data register that store results of a/d conversion an0 addra an1 addrb an2 addrc an3 addrd 21.3.2 a/d control/status registers (adcsr) adcsr is a 16-bit readable/writable register that selects the mode and controls the a/d converter. bit bit name initial value r/w description 15 adf 0 r/(w) * a/d end flag indicates the end of a/d conversion. [setting conditions] single mode: a/d conversion ends multi mode: a/d conversion ends cycling through the selected channels scan mode: a/d conversion ends cycling through the selected channels [clearing conditions] (1) reading adf while adf = 1, then writing 0 to adf (2) dmac is activated by adi interrupt and addr is read note: * clear this bit by writing 0. writing 1 is ignored. rev. 1.0, 11/02, page 531 of 690 bit bit name initial value r/w description 14 adie 0 r/w a/d interrupt enable enables or disables the interrupt (adi) requested by adf. set the adie bit while the adst bit is 0. 0: interrupt (adi) requested by adf is disabled 1: interrupt (adi) requested by adf is enabled 13 adst 0 r/w a/d start starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. 0: a/d conversion is stopped. 1: single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends on selected channels. multi mode: a/d conversion starts; when conversion is completed cycling through the selected channels, adst is automatically cleared. scan mode: a/d conversion starts and continues, a/d conversion is continuously performed until adst is cleared to 0 by software, by a reset, or by a transition to standby mode. 12 dmasl 0 r/w dmac select selects an interrupt due to adf or activation of the dmac. set the dmasl bit while the adst bit is 0. 0: an interrupt by adf is selected. 1: activation of the dmac by adf is selected. 11 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 532 of 690 bit bit name initial value r/w description 7 6 cks1 cks0 0 1 r/w r/w clock select selects the a/d conversion time. clear the adst bit to 0 before changing the conversion time. 00: conversion time = 151 states (maximum) at p /4 01: conversion time = 285 states (maximum) at p /8 10: conversion time = 545 states (maximum) at p /16 11: setting prohibited note: if the minimum conversion time is not satisfied, lack of accuracy or abnormal operation may occur. 5 4 multi1 multi0 0 0 r/w r/w mode select selects single mode, multi mode, or scan mode. 00: single mode 01: setting prohibited 10: multi mode 11: scan mode 3 2 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 1 0 ch1 ch0 0 0 r/w r/w channel select these bits and the multi bit select the analog input channels. clear the adst bit to 0 before changing the channel selection. single mode multi mode or scan mode 00: an0 an0 01: an1 an0, an1 10: an2 an0 to an2 11: an3 an0 to an3 rev. 1.0, 11/02, page 533 of 690 21.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has three operating modes: single mode, multi mode, and scan mode. to avoid malfunction, switch operating modes while the adst bit of adcsr is 0. changing operating modes and channels and setting the adst bit can be performed simultaneously. 21.4.1 single mode single mode should be selected when only one a/d conversion on one channel is required. 1. a/d conversion of the selected channel starts when the adst bit of adcsr is set to 1 by software. 2. when conversion ends, the conversion results are transmitted to the a/d data register that corresponds to the channel. 3. when conversion ends, the adf bit of adcsr is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. 4. the adst bit holds 1 during a/d conversion. when a/d conversion is completed, the adst bit is cleared to 0 and the a/d converter becomes idle. when the adst bit is cleared to 0 during a/d conversion, the conversion is halted and the a/d converter becomes idle. to clear the adf flag to 0, first read adf, then write 0 to adf. 21.4.2 multi mode multi mode should be selected when performing a/d conversions on one or more channels. 1. when the adst bit is set to 1 by software, a/d conversion starts with the smaller number of the analog input channel in the group (for instance, an0, and an1 to an3). 2. when conversion of each channel ends, the conversion results are transmitted to the a/d data register that corresponds to the channel. 3. when conversion of all selected channels ends, the adf bit of adcsr is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. 4. when a/d conversion is completed, the adst bit is cleared to 0 and the a/d converter becomes idle. when the adst bit is cleared to 0 during a/d conversion, the conversion is halted and the a/d converter becomes idle. to clear the adf flag to 0, first read adf, then write 0 to adf. rev. 1.0, 11/02, page 534 of 690 21.4.3 scan mode scan mode should be selected when performing a/d conversions of analog inputs on one or more specified channels. scan mode is useful for monitoring analog inputs. 1. when the adst bit is set to 1 by software, a/d conversion starts with the smaller number of the analog input channel in the group (for instance, an0, and an1 to an3). 2. when conversion of each channel ends, the conversion results are transmitted to the a/d data register that corresponds to the channel. 3. when conversion of all selected channels ends, the adf bit of adcsr is set to 1. if the adie bit is also set to 1, an adi interrupt is requested at this time. a/d conversion then starts with the smaller number of the analog input channel. 4. the adst bit is not automatically cleared to 0. when the adst bit is set to 1, steps 2 and 3 above are repeated. when the adst bit is cleared to 0, the conversion is halted and the a/d converter becomes idle. to clear the adf flag to 0, first read adf, then write 0 to adf. 21.4.4 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at an a/d conversion start delay time t d after the adst bit is set to 1, then starts conversion. figure 21.2 shows the a/d conversion timing. table 21.3 indicates the a/d conversion time. as indicated in figure 21.2, the a/d conversion time (t conv ) includes t d and the input sampling time (t spl ). the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 21.3. in multi mode and scan mode, the values given in table 21.3 apply to the first conversion. in the second and subsequent conversions, the values given in table 21.4 apply to the first conversion. rev. 1.0, 11/02, page 535 of 690 p adf a/d conversion time (t conv ) a/d conversion start delay time (t d ) analog input sampling time (t spl ) write cycle a/d synchronization time address internal write signal write timing of adst analog input sampling signal a/d converter idle time sample and hold a/d conversion executed a/d conversion ended figure 21.2 a/d conversion timing table 21.3 a/d conversion time (single mode) cks1 = 1, cks0 = 0 cks1 = 0, cks0 = 1 cks1 = 0, cks0 = 0 symbol min typ max min typ max min typ max a/d conversion start delay t d 18? 2110? 136 ? 9 input sampling time t spl ?129??65??33? a/d conversion time t conv 535 ? 545 275 ? 285 141 ? 151 note: values in the table are numbers of states for p . table 21.4 a/d conversion time (multi mode and scan mode) cks1 cks0 conversion time (cycles) 0 0 128 (fixed) 0 1 256 (fixed) 1 0 512 (fixed) 1 1 unused rev. 1.0, 11/02, page 536 of 690 21.5 interrupts and dmac transfer request the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request is enabled when adf in adcsr is set to 1and the adie bit in adcsr is set to 1 after a/d conversion. the adi interrupt can activate the direct memory access controller (dmac) by setting the adie and dmasl bits to 1. continuous conversion without loads of software is enabled by reading data that has been converted by the adi interrupt with dmac. when activating dmac by adi, the adf bit in adcsr is automatically cleared to 0 at dmac data transfer. table 21.5 a/d converter interrupt source name interrupt source interrupt flag dmac activation adi a/d conversion end adf yes 21.6 definitions of a/d conversion accuracy the following shows the definitions of a/d conversion accuracy. in the figure, the 10 bits of the a/d converter have been simplified to 3 bits. ? resolution digital output code number of the a/d converter ? quantization error intrinsic error of the a/d converter and is expressed as 1/2 lsb (figure 21.3) ? offset error deviation between analog input voltage and ideal a/d conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (h?00; 000 in figure 21.3) to 0000000001 (h?01; 001 in figure 21.3) (figure 21.4) ? full-scale error deviation between analog input voltage and ideal a/d conversion characteristics when the digital output value changes from the 1111111110 (h?3ef; 110 in figure 21.3) to the maximum 1111111111 (h?3ff; 111 in figure 21.3) (figure 21.4). ? nonlinearity error deviation between analog input voltage and ideal a/d conversion characteristics between zero voltage and full-scale voltage (figure 21.4). note that it does not include offset, full-scale, or quantization error. ? absolute accuracy deviation between analog and digital input values. note that it includes offset, full-scale, quantization, or nonlinearity error. rev. 1.0, 11/02, page 537 of 690 111 110 101 100 011 010 001 000 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs analog input voltage quantization error ideal a/d conversion characteristic digital output figure 21.3 definitions of a/d conversion accuracy nonlinearity error ideal a/d conversion characteristic actual a/d conversion characteristic full-scale error digital output analog input voltage offset error fs figure 21.4 definitions of a/d conversion accuracy rev. 1.0, 11/02, page 538 of 690 21.7 usage notes 21.7.1 allowable signal-source impedance for the analog input design of this lsi, conversion accuracy is guaranteed for an input signal with signal-source impedance of 5 k ? or less. the specification is for charging input capacitance of the sample and hold circuit of the a/d converter within sampling time. when the output impedance of the sensor exceeds 5 k ? , conversion accuracy is not guaranteed due to insufficient charging. if large external capacitance is set at conversion in single mode, signal-source impedance is ignored since input load is only internal input resistance of 3 k ? . however, an analog signal with large differential coefficient (5 mv/ s or greater) cannot be followed up because of a low-pass filter (figure 21.5). when converting high-speed analog signals or converting in scan mode, insert a low-impedance buffer. 21.7.2 influence to absolute accuracy by adding capacitance, absolute accuracy may be degraded if noise is on gnd because there is coupling with gnd. therefore, connect electrically stable gnd such as avcc to prevent absolute accuracy from being degraded. a filter circuit must not interfere with digital signals, or must not be an antenna on a mounting board. 20 pf c in = 15 pf 3 k ? to 5 k ? output impedance of sensor sensor input this lsi lowpass filter (c = 0.1 f) equivalent circuit of a/d converter figure 21.5 analog input circuit example 21.7.3 setting analog input voltage operating the chip in excess of the following voltage range may result in damage to chip reliability. ? analog input voltage range: during a/d conversion, the voltages (vann) input to the analog input pins ann should be in the range av ss vann av cc (n = 0 to 3). rev. 1.0, 11/02, page 539 of 690 ? relationships of av cc , av ss and v cc q, v ss q: av cc = v cc q 0.2 v and av ss = v ss q. even when the a/d converter is not used, do not open av cc and av ss . 21.7.4 notes on board design in designing a board, separate digital circuits and analog circuits. do not intersect or locate closely signal lines of a digital circuit and an analog circuit. an analog circuit may malfunction due to induction, thus affecting a/d conversion values. separate analog input pins (an0 to an3) and the analog power voltage (avcc) from digital circuits with analog ground (avss). connect analog ground (avss) to one point of stable ground (vss) on the board. 21.7.5 notes on countermeasures to noise connect a protective circuit between avcc and avss, as shown in figure 21.6, to prevent damage of analog input pins (an0 to an3) due to abnormal voltage such as excessive serge. connect a bypass capacitor that is connected to avcc and a capacitor for a filter that is connected to an0 to an3 to avss. when a capacitor for a filter is connected, input currents of an0 to an3 are averaged, may causing errors. if a/d conversion is frequently performed in scan mode, voltages of analog input pins cause errors when a current that is charged/discharged for capacitance of a sample & hold circuit in the a/d converter is higher than a current that is input through input impedance (rin). therefore, determine a circuit constant carefully. 0.01 f 10 f av cc an0 to an3 av ss this lsi * 1 100 ? 0.1 f notes: * 1 values are for reference. r in * 2 * 2 r in is input impedance. figure 21.6 example of analog input protection circuit rev. 1.0, 11/02, page 540 of 690 table 21.6 analog input pin ratings item min max unit analog input capacitance ? 20 pf allowable signal-source impedance ? 5 k ? 20 pf an0 to an3 3 k ? to a/d converter note: values are for reference. figure 21.7 analog input pin equivalent circuit ubcs311a_000020020100 rev. 1.0, 11/02, page 541 of 690 section 22 user break controller the user break controller (ubc) provides functions that simplify program debugging. these functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. break conditions that can be set in the ubc are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch. 22.1 features the ubc has the following features: ? the following break comparison conditions can be set. number of break channels: two channels (channels a and b) user break can be requested as either the independent or sequential condition on channels a and b (sequential break setting: channel a and then channel b match with break conditions, but not in the same bus cycle). ? address (compares 40 bits configured of the asid and addresses 32 bits: the asid can be selected either all-bit comparison or all-bit mask. comparison bits for the address are maskable in 1-bit units; user can mask addresses at lower 12 bits (4 k page), lower 10 bits (1 k page), or any size of page, etc.) one of the two address buses (l bus address (lab) and i bus address (iab)) can be selected. ? data (only on channel b, 32-bit maskable) one of the two data buses (l bus data (ldb) and i bus data (idb)) can be selected. ? bus cycle: instruction fetch or data access ? read/write ? operand size: byte, word, or longword ? user break is generated upon satisfying break conditions. a user-designed user-break condition exception processing routine can be run. ? in an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. ? maximum repeat times for the break condition (only for channel b): 2 12 ? 1 times. ? eight pairs of branch source/destination buffers. rev. 1.0, 11/02, page 542 of 690 figure 22.1 shows a block diagram of the ubc. bbra bara bamra cpu state signals iab lab mdb access comparator address comparator channel a access comparator address comparator data comparator pc trace control channel b bbrb betr basra basrb barb bamrb bbrb bdmrb brsr brdr brcr user break request ubc location ccn location ldb/idb [legend] bbra: break bus cycle register a bara: break address register a bamra: break address mask register a basra: break asid register a bbrb: break bus cycle register b barb: break address register b bamrb: break address mask register b basrb: break asid register b bdrb: break data register b bdmrb: break data mask register b betr: break execution times register brsr: branch source register brdr: branch destination register brcr: break control register access control asid comparator asid comparator asid figure 22.1 block diagram of user break controller rev. 1.0, 11/02, page 543 of 690 22.2 register descriptions the user break controller has the following registers. for details on register addresses and access sizes, refer to section 24, list of registers. ? break address register a (bara) ? break address mask register a (bamra) ? break bus cycle register a (bbra) ? break address register b (barb) ? break address mask register b (bamrb) ? break bus cycle register b (bbrb) ? break data register b (bdrb) ? break data mask register b (bdmrb) ? break control register (brcr) ? execution times break register (betr) ? branch source register (brsr) ? branch destination register (brdr) ? break asid register a (basra) ? break asid register b (basrb) 22.2.1 break address register a (bara) bara is a 32-bit readable/writable register. bara specifies the address used as a break condition in channel a. bit bit name initial value r/w description 31 to 0 baa31 to baa0 all 0 r/w break address a store the address on the lab or iab specifying break conditions of channel a. rev. 1.0, 11/02, page 544 of 690 22.2.2 break address mask register a (bamra) bamra is a 32-bit readable/writable register. bamra specifies bits masked in the break address specified by bara. bit bit name initial value r/w description 31 to 0 bama31 to bama0 all 0 r/w break address mask a specify bits masked in the channel a break address bits specified by bara (baa31 to baa0). 0: break address bit baan of channel a is included in the break condition 1: break address bit baan of channel a is masked and is not included in the break condition note: n = 31 to 0 22.2.3 break bus cycle register a (bbra) bbra is a 16-bit readable/writable register, which specifies (1) l bus cycle or i bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel a. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 cda1 cda0 0 0 r/w r/w l bus cycle/i bus cycle select a select the l bus cycle or i bus cycle as the bus cycle of the channel a break condition. 00: condition comparison is not performed 01: the break condition is the l bus cycle 10: the break condition is the i bus cycle 11: the break condition is the l bus cycle rev. 1.0, 11/02, page 545 of 690 bit bit name initial value r/w description 5 4 ida1 ida0 0 0 r/w r/w instruction fetch/data access select a select the instruction fetch cycle or data access cycle as the bus cycle of the channel a break condition. 00: condition comparison is not performed 01: the break condition is the instruction fetch cycle 10: the break condition is the data access cycle 11: the break condition is the instruction fetch cycle or data access cycle 3 2 rwa1 rwa0 0 0 r/w r/w read/write select a select the read cycle or write cycle as the bus cycle of the channel a break condition. 00: condition comparison is not performed 01: the break condition is the read cycle 10: the break condition is the write cycle 11: the break condition is the read cycle or write cycle 1 0 sza1 sza0 0 0 r/w r/w operand size select a select the operand size of the bus cycle for the channel a break condition. 00: the break condition does not include operand size 01: the break condition is byte access 10: the break condition is word access 11: the break condition is longword access 22.2.4 break address register b (barb) barb is a 32-bit readable/writable register. barb specifies the address used as a break condition in channel b. bit bit name initial value r/w description 31 to 0 bab31 to bab0 all 0 r/w break address b stores an address which specifies a break condition in channel b. barb specifies the break address on lab or iab. rev. 1.0, 11/02, page 546 of 690 22.2.5 break address mask register b (bamrb) bamrb is a 32-bit readable/writable register. bamrb specifies bits masked in the break address specified by barb. bit bit name initial value r/w description 31 to 0 bamb31 to bamb0 all 0 r/w break address mask b specifies bits masked in the break address of channel b specified by barb (bab31 to bab0). 0: break address babn of channel b is included in the break condition 1: break address babn of channel b is masked and is not included in the break condition note: n = 31 to 0 22.2.6 break data register b (bdrb) bdrb is a 32-bit readable/writable register. bit bit name initial value r/w description 31 to 0 bdb31 to bdb0 all 0 r/w break data bit b stores data which specifies a break condition in channel b. bdrb specifies the break data on ldb or idb. notes: 1. specify an operand size when including the value of the data bus in the break condition. 2. when the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in bdrb as the break data. rev. 1.0, 11/02, page 547 of 690 22.2.7 break data mask register b (bdmrb) bdmrb is a 32-bit readable/writable register. bdmrb specifies bits masked in the break data specified by bdrb. bit bit name initial value r/w description 31 to 0 bdmb31 to bdmb0 all 0 r/w break data mask b specifies bits masked in the break data of channel b specified by bdrb (bdb31 to bdb0). 0: break data bdbn of channel b is included in the break condition 1: break data bdbn of channel b is masked and is not included in the break condition note: n = 31 to 0 notes: 1. specify an operand size when including the value of the data bus in the break condition. 2. when the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in bdrb as the break mask data in bdmrb. 22.2.8 break bus cycle register b (bbrb) bbrb is a 16-bit readable/writable register, which specifies (1) l bus cycle or i bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel b. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 548 of 690 bit bit name initial value r/w description 7 6 cdb1 cdb0 0 0 r/w r/w l bus cycle/i bus cycle select b select the l bus cycle or i bus cycle as the bus cycle of the channel b break condition. 00: condition comparison is not performed 01: the break condition is the l bus cycle 10: the break condition is the i bus cycle 11: the break condition is the l bus cycle 5 4 idb1 idb0 0 0 r/w r/w instruction fetch/data access select b select the instruction fetch cycle or data access cycle as the bus cycle of the channel b break condition. 00: condition comparison is not performed 01: the break condition is the instruction fetch cycle 10: the break condition is the data access cycle 11: the break condition is the instruction fetch cycle or data access cycle 3 2 rwb1 rwb0 0 0 r/w r/w read/write select b select the read cycle or write cycle as the bus cycle of the channel b break condition. 00: condition comparison is not performed 01: the break condition is the read cycle 10: the break condition is the write cycle 11: the break condition is the read cycle or write cycle 1 0 szb1 szb0 0 0 r/w r/w operand size select b select the operand size of the bus cycle for the channel b break condition. 00: the break condition does not include operand size 01: the break condition is byte access 10: the break condition is word access 11: the break condition is longword access rev. 1.0, 11/02, page 549 of 690 22.2.9 break control register (brcr) brcr sets the following conditions: 1. specifies whether channels a and b are used in two independent channel conditions or under the sequential condition. 2. specifies whether a break is set before or after instruction execution. 3. specifies whether to include the number of execution times on channel b in comparison conditions. 4. specifies whether to include data bus on channel b in comparison conditions. 5. enables pc trace. 6. enables asid check. brcr is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions. bit bit name initial value r/w description 31 to 22 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 21 basma 0 r/w break asid mask a specifies whether bits in channel a break asid7 to asid0 (basa7 to basa0) which are set in basra are masked or not. 0: all basra bits are included in the break conditions and the asid is checked 1: all basra bits are not included in the break conditions and the asid is not checked 20 basmb 0 r/w break asid mask b specifies whether bits in channel b break asid7 to asid0 (basb7 to basb0) which are set in basrb are masked or not. 0: all basrb bits are included in the break conditions and the asid is checked 1: all basrb bits are not included in the break conditions and the asid is not checked 19 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. rev. 1.0, 11/02, page 550 of 690 bit bit name initial value r/w description 15 scmfca 0 r/w l bus cycle condition match flag a when the l bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1. in order to clear this flag, write 0 into this bit. 0: the l bus cycle condition for channel a does not match 1: the l bus cycle condition for channel a matches 14 scmfcb 0 r/w l bus cycle condition match flag b when the l bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1. in order to clear this flag, write 0 into this bit. 0: the l bus cycle condition for channel b does not match 1: the l bus cycle condition for channel b matches 13 scmfda 0 r/w i bus cycle condition match flag a when the i bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1. in order to clear this flag, write 0 into this bit. 0: the i bus cycle condition for channel a does not match 1: the i bus cycle condition for channel a matches 12 scmfdb 0 r/w i bus cycle condition match flag b when the i bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1. in order to clear this flag, write 0 into this bit. 0: the i bus cycle condition for channel b does not match 1: the i bus cycle condition for channel b matches 11 pcte 0 r/w pc trace enable 0: disables pc trace 1: enables pc trace 10 pcba 0 r/w pc break select a selects the break timing of the instruction fetch cycle for channel a as before or after instruction execution. 0: pc break of channel a is set before instruction execution 1: pc break of channel a is set after instruction execution rev. 1.0, 11/02, page 551 of 690 bit bit name initial value r/w description 9, 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 dbeb 0 r/w data break enable b selects whether or not the data bus condition is included in the break condition of channel b. 0: no data bus condition is included in the condition of channel b 1: the data bus condition is included in the condition of channel b 6 pcbb 0 r/w pc break select b selects the break timing of the instruction fetch cycle for channel b as before or after instruction execution. 0: pc break of channel b is set before instruction execution 1: pc break of channel b is set after instruction execution 5, 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 seq 0 r/w sequence condition select selects two conditions of channels a and b as independent or sequential conditions. 0: channels a and b are compared under independent conditions 1: channels a and b are compared under sequential conditions (channel a, then channel b) 2, 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 etbe 0 r/w number of execution times break enable enables the execution-times break condition only on channel b. if this bit is 1 (break enable), a user break is issued when the number of satisfied break conditions matches with the number of execution times that is specified by betr. 0: the execution-times break condition is disabled on channel b 1: the execution-times break condition is enabled on channel b rev. 1.0, 11/02, page 552 of 690 22.2.10 execution times break register (betr) betr is a 16-bit readable/writable register. when the execution-times break condition of channel b is enabled, this register specifies the number of execution times to make the break. the maximum number is 2 12 ? 1 times. when a break condition is satisfied, it decrements the betr value. a break is issued when the break condition is satisfied after betr becomes h'0001. bit bit name initial value r/w description 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 bet11 to bet0 all 0 r/w number of execution times 22.2.11 branch source register (brsr) brsr is a 32-bit read-only register. brsr stores bits 27 to 0 in the address of the branch source instruction. brsr has the flag bit that is set to 1 when a branch occurs. this flag bit is cleared to 0 when brsr is read, the setting to enable pc trace is made, or brsr is initialized by a power-on reset. other bits are not initialized by a power-on reset. the eight brsr registers have a queue structure and a stored register is shifted at every branch. bit bit name initial value r/w description 31 svf 0 r brsr valid flag indicates whether the branch source address is stored. when a branch source address is fetched, this flag is set to 1. this flag is cleared to 0 by reading from brsr. 0: the value of brsr register is invalid 1: the value of brsr register is valid 30 to 28 ? all 0 r reserved these bits are always read as 0. 27 to 0 bsa27 to bsa0 undefined r branch source address store bits 27 to 0 of the branch source address. rev. 1.0, 11/02, page 553 of 690 22.2.12 branch destination register (brdr) brdr is a 32-bit read-only register. brdr stores bits 27 to 0 in the address of the branch destination instruction. brdr has the flag bit that is set to 1 when a branch occurs. this flag bit is cleared to 0 when brdr is read, the setting to enable pc trace is made, or brdr is initialized by a power-on reset. other bits are not initialized by a power-on reset. the eight brdr registers have a queue structure and a stored register is shifted at every branch. bit bit name initial value r/w description 31 dvf 0 r brdr valid flag indicates whether a branch destination address is stored. when a branch destination address is fetched, this flag is set to 1. this flag is cleared to 0 by reading brdr. 0: the value of brdr register is invalid 1: the value of brdr register is valid 30 to 28 ? all 0 r reserved these bits are always read as 0. 27 to 0 bda27 to bda0 undefined r branch destination address store bits 27 to 0 of the branch destination address. 22.2.13 break asid register a (basra) basra is an 8-bit readable/writable register that specifies asid which becomes the break condition for channel a. basra is in ccn. bit bit name initial value r/w description 7 to 0 basa7 to basa0 ? r/w break asid a store asid (bits 7 to 0) which is the break condition for channel a. rev. 1.0, 11/02, page 554 of 690 22.2.14 break asid register b (basrb) basrb is an 8-bit readable/writable register that specifies asid which becomes the break condition for channel b. basrb is in ccn. bit bit name initial value r/w description 7 to 0 basb7 to basb0 ? r/w break asid b store asid (bits 7 to 0) which is the break condition for channel b. 22.3 operation 22.3.1 flow of the user break operation the flow from setting of break conditions to user break exception processing is described below: 1. the break addresses and corresponding asid are set in the break address registers (bara and barb) and break asid registers (basra and basrb in cnn). the masked addresses are set in the break address mask registers (bamra and bamrb). the break data is set in the break data register (bdrb). the masked data is set in the break data mask register (bdmrb). the bus break conditions are set in the break bus cycle registers (bbra and bbrb). three gr oups of bbra and bbrb (l bus cycle/i bus cycle select, instruction fetch/data access select, and read/write select) are each set. no user break will be generated if even one of these groups is set with 00. the respective conditions are set in the bits of the break control register (brcr). make sure to set all registers related to breaks before setting bbra/bbrb. 2. when the break conditions are satisfied, the ubc sends a user break request to the cpu and sets the l bus condition match flag (scmfca or scmfcb) and the i bus condition match flag (scmfda or scmfdb) for the appropriate channel. 3. the appropriate condition match flags (scmfca, scmfda, scmfcb, and scmfdb) can be used to check if the set conditions match or not. the matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. there is a chance that the data access break and its following instruction fetch break occur around the same time. there will be only one break request to the cpu, but these two break channel match flags could be both set. rev. 1.0, 11/02, page 555 of 690 5. when selecting the i bus as the break condition, note the following: ? several bus masters, including the cpu and dmac, are connected to the i bus. the ubc monitors bus cycles generated by all bus masters, and determines the condition match. ? physical addresses are used for the i bus. set a physical address in break address registers (bara and barb). the bus cycles for logical addresses issued on the l bus by the cpu are converted to physical addresses before being output to the i bus. (if the address translation function is enabled, address translation by the mmu is carried out.) ? for data access cycles issued on the l bus by the cpu, if their logical addresses are not to be cached, they are issued with the data size specified on the l bus and their addresses are not rounded. ? for instruction fetch cycles issued on the l bus by the cpu, even though their logical addresses are not to be cached, they are issued in longwords and their addresses are rounded to match longword boundaries. ? if a logical address issued on the l bus by the cpu is an address to be cached and a cache miss occurs, its bus cycle is issued as a cache fill cycle on the i bus. in this case, it is issued in longwords and its address is rounded to match longword boundaries. however note that cache fill is not performed for a write miss in write through mode. in this case, the bus cycle is issued with the data size specified on the l bus and its address is not rounded. in write back mode, a write back cycle may be issued in addition to a read fill cycle. it is a longword bus cycle whose address is rounded to match longword boundaries. ? i bus cycles (including read fill cycles) resulting from instruction fetches on the l bus by the cpu are defined as instruction fetch cycles on the i bus, while other bus cycles are defined as data access cycles. ? the dmac only issues data access cycles for i bus cycles. ? if a break condition is specified for the i bus, even when the condition matches in an i bus cycle resulting from an instruction executed by the cpu, at which instruction the break is to be accepted cannot be clearly defined. 6. while the block bit (bl) in the cpu status register (sr) is set to 1, no breaks can be accepted. however, condition determination will be carried out, and if the condition matches, the corresponding condition match flag is set to 1. rev. 1.0, 11/02, page 556 of 690 22.3.2 break on instruction fetch cycle 1. when l bus/instruction fetch/read/word or longword is set in the break bus cycle register (bbra or bbrb), the break c ondition becomes the l bus instruction fetch cycle. whether it breaks before or after the execution of the instruction can then be selected with the pcba or pcbb bit of the break control register (brcr) for the appropriate channel. if an instruction fetch cycle is set as a break condition, clear lsb in the break address register (bara or barb) to 0. a break cannot be generated as long as this bit is set to 1. 2. an instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. this means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). when this kind of break is set for the delay slot of a delayed branch instruction, the break is generated prior to execution of the delayed branch instruction. note: if a branch does not occur at a delayed conditional branch instruction, the subsequent instruction is not recognized as a delay slot. 3. when the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. as with pre-execution breaks, this cannot be used with overrun fetch instructions. when this kind of break is set for a delayed branch instruction and its delay slot, a break is not generated until the first instruction at the branch destination. 4. when an instruction fetch cycle is set for channel b, the break data register b (bdrb) is ignored. therefore, break data cannot be set for the break of the instruction fetch cycle. 5. if the i bus is set for a break of an instruction fetch cycle, the condition is determined for the instruction fetch cycles on the i bus. for details, see 5 in section 22.3.1, flow of the user break operation. rev. 1.0, 11/02, page 557 of 690 22.3.3 break on data access cycle 1. if the l bus is specified as a break condition for data access break, condition comparison is performed for the logical addresses (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. if the i bus is specified as a break condition, condition comparison is performed for the physical addresses (and data) of the data access cycles that are issued on the i bus by all bus masters including the cpu, and a break occurs if the condition is satisfied. for details on the cpu bus cycles issued on the i bus, see 5 in section 22.3.1, flow of the user break operation. 2. the relationship between the data access cycle address and the comparison condition for each operand size is listed in table 22.1. table 22.1 data access cycle addresses and operand size comparison conditions access size address compared longword compares break address register bits 31 to 2 to address bus bits 31 to 2 word compares break address register bits 31 to 1 to address bus bits 31 to 1 byte compares break address register bits 31 to 0 to address bus bits 31 to 0 this means that when address h'00001003 is set in the break address register (bara or barb), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). longword access at h'00001000 word access at h'00001002 byte access at h'00001003 3. when the data value is included in the break conditions on channel b: when the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle register b (bbrb). when data values are included in break conditions, a break is generated when the address conditions and data conditions both match. to specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register b (bdrb) and break data mask register b (bdmrb). when word or byte is set, bits 31 to 16 of bdrb and bdmrb are ignored. 4. access by a pref instruction is handled as read access in longword units without access data. therefore, if including the value of the data bus when a pref instruction is specified as a break condition, a break will not occur. 5. if the l bus is selected, a break occurs on ending execution of the instruction that matches the break condition, and immediately before the next instruction is executed. however, when data is also specified as the break condition, the break may occur on ending execution of the instruction following the instruction that matches the break condition. if the i bus is selected, the instruction at which the break will occur cannot be determined. when this kind of break rev. 1.0, 11/02, page 558 of 690 occurs at a delayed branch instruction or its delay slot, the break may not actually take place until the first instruction at the branch destination. 22.3.4 sequential break 1. by setting the seq bit in brcr to 1, the sequential break is issued when a channel b break condition matches after a channel a break condition matches. a user break is not generated even if a channel b break condition matches before a channel a break condition matches. when channels a and b conditions match at the same time, the sequential break is not issued. to clear the channel a condition match when a channel a condition match has occurred but a channel b condition match has not yet occurred in a sequential break specification, clear the seq bit in brcr to 0. 2. in sequential break specification, the l or i bus can be selected and the execution times break condition can be also specified. for example, when the execution times break condition is specified, the break condition is satisfied when a channel b condition matches with betr = h'0001 after a channel a condition has matched. 22.3.5 value of saved program counter when a break occurs, the address of the instruction from where execution is to be resumed is saved in the spc, and the exception handling state is entered. if the l bus is specified as a break condition, the instruction at which the break should occur can be clearly determined (except for when data is included in the break condition). if the i bus is specified as a break condition, the instruction at which the break should occur cannot be clearly determined. rev. 1.0, 11/02, page 559 of 690 1. when instruction fetch (before instruction execution) is specified as a break condition: the address of the instruction that matched the break condition is saved in the spc. the instruction that matched the condition is not executed, and the break occurs before it. however when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the spc. 2. when instruction fetch (after instruction execution) is specified as a break condition: the address of the instruction following the instruction that matched the break condition is saved in the spc. the instruction that matches the condition is executed, and the break occurs before the next instruction is executed. however when a delayed branch instruction or delay slot matches the condition, these instructions are executed, and the branch destination address is saved in the spc. 3. when data access (address only) is specified as a break condition: the address of the instruction immediately after the instruction that matched the break condition is saved in the spc. the instruction that matches the condition is executed, and the break occurs before the next instruction is executed. however when a delay slot instruction matches the condition, the branch destination address is saved in the spc. 4. when data access (address + data) is specified as a break condition: when a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the spc. at which instruction the break occurs cannot be determined accurately. when a delay slot instruction matches the condition, the branch destination address is saved in the spc. if the instruction following the instruction that matches the break condition is a branch instruction, the break may occur after the branch instruction or delay slot has finished. in this case, the branch destination address is saved in the spc. rev. 1.0, 11/02, page 560 of 690 22.3.6 pc trace 1. setting pcte in brcr to 1 enables pc traces. when branch (branch instruction, and interrupt exception) is generated, the branch source address and branch destination address are stored in brsr and brdr, respectively. 2. the values stored in brsr and brdr are as given below due to the kind of branch. ? if a branch occurs due to a branch instruction, the address of the branch instruction is saved in brsr and the address of the branch destination instruction is saved in brdr. ? if a branch occurs due to an interrupt or exception, the value saved in spc due to exception occurrence is saved in brsr and the start address of the exception handling routine is saved in brdr. 3. brsr and brdr have eight pairs of queue structures. the top of queues is read first when the address stored in the pc trace register is read. brsr and brdr share the read pointer. read brsr and brdr in order, the queue only shifts after brdr is read. after switching the pcte bit (in brcr) off and on, the values in the queues are invalid. rev. 1.0, 11/02, page 561 of 690 22.3.7 usage examples break condition specified for an l bus instruction fetch cycle 1. register specifications bara = h'00000404, bamra = h'00000000, bbra = h' 0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00300400 specified conditions: channel a/channel b independent mode ? channel a address: h'00000404, address mask: h'00000000 bus cycle: l bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) the asid check is not included. ? channel b address: h'00008010, address mask: h'00000006 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) the asid check is not included. a user break occurs after an instruction of address h'00000404 is executed or before instructions of addresses h'00008010 to h'00008016 are executed. 2. register specifications bara = h'00037226, bamra = h'00000000, bbra = h' 0056, barb = h'0003722e, bamrb = h'00000000, bbrb = h'0056, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00000008, basra = h'80, basrb = h'70 specified conditions: channel a/channel b sequential mode ? channel a address: h'00037226, address mask: h'00000000, asid = h'80 bus cycle: l bus/instruction fetch (before instruction execution)/read/word ? channel b address: h'0003722e, address mask: h'00000000, asid = h'70 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fetch (before instruction execution)/read/word after an instruction with asid = h?80 and address h'00037226 is executed, a user break occurs before an instruction with asid = h?70 and address h'0003722e is executed. rev. 1.0, 11/02, page 562 of 690 3. register specifications bara = h'00027128, bamra = h'00000000, bbra = h'005a, barb = h'00031415, bamrb = h'00000000, b brb = h' 0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00300000 specified conditions: channel a/channel b independent mode ? channel a address: h'00027128, address mask: h'00000000 bus cycle: l bus/instruction fetch (before instruction execution)/write/word the asid check is not included. ? channel b address: h'00031415, address mask: h'00000000 data: h'00000000, data mask: h'00000000 the asid check is not included. bus cycle: l bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) on channel a, no user break occurs since instruction fetch is not a write cycle. on channel b, no user break occurs since instruction fetch is performed for an even address. 4. register specifications bara = h'00037226, bamra = h'00000000, bbra = h'005a, barb = h'0003722e, bamrb = h'00000000, b brb = h' 0056, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00000008, basra = h'80, basrb = h'70 specified conditions: channel a/channel b sequential mode ? channel a address: h'00037226, address mask: h'00000000, asid = h'80 bus cycle: l bus/instruction fetch (before instruction execution)/write/word ? channel b address: h'0003722e, address mask: h'00000000, asid = h'70 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fetch (before instruction execution)/read/word since instruction fetch is not a write cycle on channel a, a sequential condition does not match. therefore, no user break occurs. rev. 1.0, 11/02, page 563 of 690 5. register specifications bara = h'00000500, bamra = h'00000000, bbra = h' 0057, barb = h'00001000, bamrb = h'00000000, bbrb = h'0057, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00300001, betr = h'0005 specified conditions: channel a/channel b independent mode ? channel a address: h'00000500, address mask: h'00000000 bus cycle: l bus/instruction fetch (before instruction execution)/read/longword the asid check is not included. ? channel b address: h'00001000, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fetch (before instruction execution)/read/longword the number of execution-times break enable (5 times) the asid check is not included. on channel a, a user break occurs before an instruction of address h'00000500 is executed. on channel b, a user break occurs after the instruction of address h'00001000 are executed four times and before the fifth time. 6. register specifications bara = h'00008404, bamra = h'00000fff, bbra = h' 0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h' 00000400, basra = h'80, basrb = h'70 specified conditions: channel a/channel b independent mode ? channel a address: h'00008404, address mask: h'00000fff, asid = h'80 bus cycle: l bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) ? channel b address: h'00008010, address mask: h'00000006, asid = h'70 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) a user break occurs after an instruction with asid = h?80 and addresses h'00008000 to h'00008ffe is executed or before an instruction with asid = h?70 and addresses h'00008010 to h'00008016 are executed. rev. 1.0, 11/02, page 564 of 690 break condition specified for an l bus data access cycle register specifications: bara = h'00123456, bamra = h'00000000, bbra = h'0064, barb = h'000abcde, bamrb = h'000000ff, bbrb = h'006a, bdrb = h'0000a512, bdmrb = h'00000000, brcr = h' 00000080, basra = h'80, basrb = h'70 specified conditions: channel a/channel b independent mode ? channel a address: h'00123456, address mask: h'00000000, asid = h?80 bus cycle: l bus/data access/read (operand size is not included in the condition) ? channel b address: h'000abcde, address mask: h'000000ff, asid = h?70 data: h'0000a512, data mask: h'00000000 bus cycle: l bus/data access/write/word on channel a, a user break occurs with longword read from asid = h?80 and address h'00123454, word read from address h'00123456, or byte read from address h'00123456. on channel b, a user break occurs when word h'a512 is written in asid = h?70 and addresses h'000abc00 to h'000abcfe. rev. 1.0, 11/02, page 565 of 690 break condition specified for an i bus data access cycle register specifications: bara = h'00314156, bamra = h'00000000, bbra = h' 0094, barb = h'00055555, bamrb = h'00000000, bbrb = h'00a9, bdrb = h'00007878, bdmrb = h'00000f0f, brcr = h' 00000080, basra = h'80, basrb = h'70 specified conditions: channel a/channel b independent mode ? channel a address: h'00314156, address mask: h'00000000, asid = h'80 bus cycle: i bus/instruction fetch/read (operand size is not included in the condition) ? channel b address: h'00055555, address mask: h'00000000, asid = h'70 data: h'00000078, data mask: h'0000000f bus cycle: i bus/data access/write/byte on channel a, a user break occurs when instruction fetch is performed for asid = h?80 and address h'00314156 in the memory space. on channel b, a user break occurs when byte data h'7* is written in address h'00055555 with asid = h?70 on the i bus. rev. 1.0, 11/02, page 566 of 690 22.3.8 notes 1. the cpu can read from or write to the ubc registers via the i bus. accordingly, during the period from executing an instruction to rewrite the ubc register till the new value is actually rewritten, the desired break may not occur. in order to know the timing when the ubc register is changed, read from the last written register. instructions after then are valid for the newly written register value. 2. ubc cannot monitor access to the l bus and i bus in the same channel. 3. note on specification of sequential break: a condition match occurs when a b-channel match occurs in a bus cycle after an a-channel match occurs in another bus cycle in sequential break setting. therefore, no break occurs even if a bus cycle, in which an a-channel match and a channel b match occur simultaneously, is set. 4. when a user break and another exception occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 5.1 in section 5, exception handling. if an exception with higher priority occurs, the user break is not generated. ? pre-execution break has the highest priority. ? when a post-execution break or data access break occurs simultaneously with a re- execution-type exception (including pre-execution break) that has higher priority, the re- execution-type exception is accepted, and the condition match flag is not set (see the exception in the following note). the break will occur and the condition match flag will be set only after the exception source of the re-execution-type exception has been cleared by the exception handling routine and re-execution of the same instruction has ended. ? when a post-execution break or data access break occurs simultaneously with a completion-type exception (trapa) that has higher priority, though a break does not occur, the condition match flag is set. 5. note the following exception for the above note. if a post-execution break or data access break is satisfied by an instruction that generates a cpu address error (or tlb related exception) by data access, the cpu address error (or tlb related exception) is given priority to the break. note that the ubc condition match flag is set in this case. 6. note the following when a break occurs in a delay slot. if a pre-execution break is set at the delay slot instruction of the rte instruction, the break does not occur until the branch destination of the rte instruction. 7. user breaks are disabled during usb module standby mode. do not read from or write to the ubc registers during usb module standby mode; the values are not guaranteed. rev. 1.0, 11/02, page 567 of 690 section 23 hitachi user debugging interface (h-udi) this lsi incorporates a hitachi user debugging interface (h-udi) and advanced user debugger (aud) for a boundary scan function and emulator support. this section describes the h-udi. the aud is a function exclusively for use by an emulator. refer to the user?s manual for the relevant emulator for details of the aud. 23.1 features the h-udi (hitachi user debugging interface) is a serial i/o interface which supports with jtag (joint test action group, ieee standard 1149.1 and ieee standard test access port and boundary-scan architecture) specifications. the h-udi in this lsi supports a boundary scan mode, and is also used for emulator connection. when using an emulator, h-udi functions should not be used. refer to the emulator manual for the method of connecting the emulator. figure 23.1 shows a block diagram of the h-udi. sdir sdid tck tdo tdi tms sdbpr mux sdbsr shift register tap controller decoder local bus figure 23.1 block diagram of h-udi rev. 1.0, 11/02, page 568 of 690 23.2 input/output pins table 23.1 shows the pin configuration of the h-udi. table 23.1 pin configuration pin name input/output description tck input serial data input/output clock pin data is serially supplied to the h-udi from the data input pin (tdi), and output from the data output pin (tdo), in synchronization with this clock. tms input mode select input pin the state of the tap control circuit is determined by changing this signal in synchronization with tck. the protocol is supported to the jtag standard (ieee std.1149.1). trst input reset input pin input is accepted asynchronously with respect to tck, and when low, the h-udi is reset. trst must be held low for a constant period when power is turned on regardless of using the h-udi function. as the same as the resetp pin, the trst pin should be driven low at the power-on reset state and driven high after the power-on reset state is released. this is different from the jtag standard. see section 23.4.2, reset configuration, for more information. tdi input serial data input pin data transfer to the h-udi is executed by changing this signal in synchronization with tck. tdo output serial data output pin data read from the h-udi is executed by reading this pin in synchronization with tck. the data output timing depends on the command type set in the sdir. see section 23.3.2, instruction register (sdir), for more information. asemd0 input ase mode select pin if a low level is input at the asemd0 pin while the resetp pin is asserted, ase mode is entered; if a high level is input, normal mode is entered. in ase mode, dedicated emulator function can be used. the input level at the asemd0 pin should be held for at least one cycle after resetp negation. see section 23.4.2, reset configuration, for more information. rev. 1.0, 11/02, page 569 of 690 pin name input/output description asebrkak audsync audata3 to 0 audck output dedicated emulator pin 23.3 register descriptions the h-udi has the following registers. for details on register addresses and register states in each processing state, see section 24, list of registers. ? bypass register (sdbpr) ? instruction register (sdir) ? boundary scan register (sdbsr) ? id register (sdid) 23.3.1 bypass register (sdbpr) sdbpr is a 1-bit register that cannot be accessed by the cpu. when sdir is set to the bypass mode, sdbpr is connected between h-udi pins tdi and tdo. the initial value is undefined but sdbpr is initialized when the tap enters the capture-dr state. 23.3.2 instruction register (sdir) sdir is a 16-bit read-only register. the register is in jtag idcode in its initial state. it is initialized by trst assertion or in the tap test-logic-reset state, and can be written to by the h- udi irrespective of the cpu mode. operation is not guaranteed if a reserved command is set in this register. bit bit name initial value r/w description 15 to 13 ti7 to ti5 all 1 r 12 ti4 0 r 11 to 8 ti3 to ti0 all 1 r test instruction 7 to 0 the h-udi instruction is transferred to sdir by a serial input from tdi. for commands, see table 23.2. 7 to 2 ? all 1 r reserved these bits are always read as 1. 1 ? 0rreserved this bit is always read as 0. 0 ? 1rreserved this bit is always read as 1. rev. 1.0, 11/02, page 570 of 690 table 23.2 h-udi commands bits 15 to 8 ti7 ti6 ti5 ti4 ti3 ti2 ti1 ti0 description 0000????jtag extest 0010????jtag clamp 0011????jtag highz 0100????jtag sample/preload 0110????h-udi reset negate 0111????h-udi reset assert 1 0 1 ?????h-udi interrupt 1110????jtag idcode (initial value) 1111????jtag bypass other than the above reserved 23.3.3 boundary scan register (sdbsr) sdbsr is a 384-bit shift register, located on the pad, for controlling the input/output pins of this lsi. the initial value is undefined. sdbsr cannot be accessed by the cpu. using the extest, sample/preload, clamp, and highz commands, a boundary scan test which supports the jtag standard can be carried out. table 23.3 shows the correspondence between this lsi?s pins and boundary scan register bits. rev. 1.0, 11/02, page 571 of 690 table 23.3 sh7705 pins and boundary scan register bits bit pin name i/o bit pin name i/o from tdi 353 d2 in 384 vbus/ptm6 in 352 d1 in 383 md6 in 351 d0 in 382 d31/ptb7/pint15 in 350 vbus/ptm6 out 381 d30/ptb6/pint14 in 349 d31/ptb7/pint15 out 380 d29/ptb5/pint13 in 348 d30/ptb6/pint14 out 379 d28/ptb4/pint12 in 347 d29/ptb5/pint13 out 378 d27/ptb3/pint11 in 346 d28/ptb4/pint12 out 377 d26/ptb2/pint10 in 345 d27/ptb3/pint11 out 376 d25/ptb1/pint9 in 344 d26/ptb2/pint10 out 375 d24/ptb0/pint8 in 343 d25/ptb1/pint9 out 374 d23/pta7/pint7 in 342 d24/ptb0/pint8 out 373 d22/pta6/pint6 in 341 d23/pta7/pint7 out 372 d21/pta5/pint5 in 340 d22/pta6/pint6 out 371 d20/pta4/pint4 in 339 d21/pta5/pint5 out 370 d19/pta3/pint3 in 338 d20/pta4/pint4 out 369 d18/pta2/pint2 in 337 d19/pta3/pint3 out 368 d17/pta1/pint1 in 336 d18/pta2/pint2 out 367 d16/pta0/pint0 in 335 d17/pta1/pint1 out 366 d15 in 334 d16/pta0/pint0 out 365 d14 in 333 d15 out 364 d13 in 332 d14 out 363 d12 in 331 d13 out 362 d11 in 330 d12 out 361 d10 in 329 d11 out 360 d9 in 328 d10 out 359 d8 in 327 d9 out 358 d7 in 326 d8 out 357 d6 in 325 d7 out 356 d5 in 324 d6 out 355 d4 in 323 d5 out 354 d3 in 322 d4 out rev. 1.0, 11/02, page 572 of 690 bit pin name i/o bit pin name i/o 321 d3 out 288 d3 control 320 d2 out 287 d2 control 319 d1 out 286 d1 control 318 d0 out 285 d0 control 317 vbus/ptm6 control 284 a0/ptk0 in 316 d31/ptb7/pint15 control 283 a19/ptk1 in 315 d30/ptb6/pint14 control 282 a20/ptk2 in 314 d29/ptb5/pint13 control 281 a21/ptk3 in 313 d28/ptb4/pint12 control 280 a22/ptk4 in 312 d27/ptb3/pint11 control 279 a23/ptk5 in 311 d26/ptb2/pint10 control 278 a24/ptk6 in 310 d25/ptb1/pint9 control 277 a25/ptk7 in 309 d24/ptb0/pint8 control 276 bs /ptc0 in 308 d23/pta7/pint7 control 275 we2 /dqmul/ptc1 in 307 d22/pta6/pint6 control 274 we3 /dqmuu/ ah /ptc2 in 306 d21/pta5/pint5 control 273 cs2 /ptc3 in 305 d20/pta4/pint4 control 272 cs3 /ptc4 in 304 d19/pta3/pint3 control 271 cs4 /ptc5 in 303 d18/pta2/pint2 control 270 cs5a /ptc6 in 302 d17/pta1/pint1 control 269 cs5b /ptd6 in 301 d16/pta0/pint0 control 268 cs6a /ptc7 in 300 d15 control 267 cs6b /ptd7 in 299 d14 control 266 rasl /ptd0 in 298 d13 control 265 rasu /ptd1 in 297 d12 control 264 casl /ptd2 in 296 d11 control 263 a0/ptk0 out 295 d10 control 262 a1 out 294 d9 control 261 a2 out 293 d8 control 260 a3 out 292 d7 control 259 a4 out 291 d6 control 258 a5 out 290 d5 control 257 a6 out 289 d4 control 256 a7 out rev. 1.0, 11/02, page 573 of 690 bit pin name i/o bit pin name i/o 255 a8 out 222 rasl /ptd0 out 254 a9 out 221 rasu /ptd1 out 253 a10 out 220 casl /ptd2 out 252 a11 out 219 a0/ptk0 control 251 a12 out 218 a1 control 250 a13 out 217 a2 control 249 a14 out 216 a3 control 248 a15 out 215 a4 control 247 a16 out 214 a5 control 246 a17 out 213 a6 control 245 a18 out 212 a7 control 244 a19/ptk1 out 211 a8 control 243 a20/ptk2 out 210 a9 control 242 a21/ptk3 out 209 a10 control 241 a22/ptk4 out 208 a11 control 240 a23/ptk5 out 207 a12 control 239 a24/ptk6 out 206 a13 control 238 a25/ptk7 out 205 a14 control 237 bs /ptc0 out 204 a15 control 236 rd out 203 a16 control 235 we0 /dqmll out 202 a17 control 234 we1 /dqmlu out 201 a18 control 233 we2 /dqmul/ptc1 out 200 a19/ptk1 control 232 we3 /dqmuu/ ah /ptc2 out 199 a20/ptk2 control 231 rd/ wr out 198 a21/ptk3 control 230 cs0 out 197 a22/ptk4 control 229 cs2 /ptc3 out 196 a23/ptk5 control 228 cs3 /ptc4 out 195 a24/ptk6 control 227 cs4 /ptc5 out 194 a25/ptk7 control 226 cs5a /ptc6 out 193 bs /ptc0 control 225 cs5b /ptd6 out 192 rd control 224 cs6a /ptc7 out 191 we0 /dqmll control 223 cs6b /ptd7 out 190 we1 /dqmlu control rev. 1.0, 11/02, page 574 of 690 bit pin name i/o bit pin name i/o 189 we2 /dqmul/ptc1 control 156 nf/ptj5 in 188 we3 /dqmuu/ ah /ptc2 control 155 nf/ptj6 in 187 rd/ wr control 154 nf/ptj7 in 186 cs0 control 153 nf/ptm4 in 185 cs2 /ptc3 control 152 ptm0 in 184 cs3 /ptc4 control 151 ptm1 in 183 cs4 /ptc5 control 150 ptm2 in 182 cs5a /ptc6 control 149 ptm3 in 181 cs5b /ptd6 control 148 asebrkak /ptf6 in 180 cs6a /ptc7 control 147 md0 in 179 cs6b /ptd7 control 146 md1 in 178 rasl /ptd0 control 145 md2 in 177 rasu /ptd1 control 144 md5 in 176 casl /ptd2 control 143 casu /ptd3 out 175 casu /ptd3 in 142 cke/ptd4 out 174 cke/ptd4 in 141 ptd5/nf out 173 ptd5/nf in 140 back /ptg5 out 172 back /ptg5 in 139 breq /ptg6 out 171 breq /ptg6 in 138 wait /ptg7 out 170 wait /ptg7 in 137 dack0/pte0 out 169 dack0/pte0 in 136 dack1/pte1 out 168 dack1/pte1 in 135 tend0/pte3 out 167 tend0/pte3 in 134 audsync/ptf4 out 166 audsync/ptf4 in 133 audata0/ptf0/to0 out 165 audata0/ptf0/to0 in 132 audata1/ptf1/to1 out 164 audata1/ptf1/to1 in 131 audata2/ptf2/to2 out 163 audata2/ptf2/to2 in 130 audata3/ptf3/to3 out 162 audata3/ptf3/to3 in 129 nf/ptj0 out 161 nf/ptj0 in 128 nf/ptj1 out 160 nf/ptj1 in 127 nf/ptj2 out 159 nf/ptj2 in 126 nf/ptj3 out 158 nf/ptj3 in 125 nf/ptj4 out 157 nf/ptj4 in 124 nf/ptj5 out rev. 1.0, 11/02, page 575 of 690 bit pin name i/o bit pin name i/o 123 nf/ptj6 out 90 ptm2 control 122 nf/ptj7 out 89 ptm3 control 121 nf/ptm4 out 88 asebrkak /ptf6 control 120 ptm0 out 87 status0/pte4/ rts0 in 119 ptm1 out 86 status1/pte5/ cts0 in 118 ptm2 out 85 ptn0/suspnd in 117 ptm3 out 84 ptn1/txenl in 116 asebrkak /ptf6 out 83 ptn2/xvdata in 115 casu /ptd3 control 82 ptn3/txdmns in 114 cke/ptd4 control 81 ptn4/txdpls in 113 ptd5/nf control 80 ptn5/dmns in 112 back /ptg5 control 79 ptn6/dpls in 111 breq /ptg6 control 78 ptn7 in 110 wait /ptg7 control 77 tclk/pte6 in 109 dack0/pte0 control 76 pte7 in 108 dack1/pte1 control 75 sck0/scpt1 in 107 tend0/pte3 control 74 sck2/scpt3 in 106 audsync/ptf4 control 73 rts2 /scpt4 in 105 audata0/ptf0/to0 control 72 rxd0/scpt0/irrx in 104 audata1/ptf1/to1 control 71 rxd2/scpt2 in 103 audata2/ptf2/to2 control 70 cts2 /scpt5 in 102 audata3/ptf3/to3 control 69 irq0/ irl0 /pth0 in 101 nf/ptj0 control 68 irq1/ irl1 /pth1 in 100 naf/ptj1 control 67 irq2/ irl2 /pth2 in 99 nf/ptj2 control 66 irq3/ irl3 /pth3 in 98 nf/ptj3 control 65 irq4/pth4 in 97 nf/ptj4 control 64 irq5/pte2 in 96 nf/ptj5 control 63 audck/ptg4 in 95 nf/ptj6 control 62 nmi in 94 nf/ptj7 control 61 dreq0/pth5 in 93 nf/ptm4 control 60 dreq1/pth6 in 92 ptm0 control 59 md3 in 91 ptm1 control 58 md4 in rev. 1.0, 11/02, page 576 of 690 bit pin name i/o bit pin name i/o 57 an0/ptl0 in 27 dreq1/pth6 out 56 an1/ptl1 in 26 status0/pte4/ rts0 control 55 an2/ptl2 in 25 status1/pte5/ cts0 control 54 an3/ptl3 in 24 ptn0/suspnd control 53 status0/pte4/ rts0 out 23 ptn1/txenl control 52 status1/pte5/ cts0 out 22 ptn2/xvdata control 51 ptn0/suspnd out 21 ptn3/txdmns control 50 ptn1/txenl out 20 ptn4/txdpls control 49 ptn2/xvdata out 19 ptn5/dmns control 48 ptn3/txdmns out 18 ptn6/dpls control 47 ptn4/txdpls out 17 ptn7 control 46 ptn5/dmns out 16 tclk/pte6 control 45 ptn6/dpls out 15 pte7 control 44 ptn7 out 14 txd0/scpt0/irtx control 43 tclk/pte6 out 13 sck0/scpt1 control 42 pte7 out 12 txd2/scpt2 control 41 txd0/scpt0/irtx out 11 sck2/scpt3 control 40 sck0/scpt1 out 10 rts2 /scpt4 control 39 txd2/scpt2 out 9 cts2 /scpt5 control 38 sck2/scpt3 out 8 irq0/ irl0 /pth0 control 37 rts2 /scpt4 out 7 irq1/ irl1 /pth1 control 36 cts2 /scpt5 out 6 irq2/ irl2 /pth2 control 35 irq0/ irl0 /pth0 out 5 irq3/ irl3 /pth3 control 34 irq1/ irl1 /pth1 out 4 irq4/pth4 control 33 irq2/ irl2 /pth2 out 3 irq5/pte2 control 32 irq3/ irl3 /pth3 out 2 audck/ptg4 control 31 irq4/pth4 out 1 dreq0/pth5 control 30 irq5/pte2 out 0 dreq1/pth6 control 29 audck/ptg4 out 28 dreq0/pth5 out to tdo note: control is an active-low signal. when control is driven low, the corresponding pin is driven by the value of out. rev. 1.0, 11/02, page 577 of 690 23.3.4 id register (sdid) sdid is a 32-bit read-only register that consists of connected 16-bit registers sdidh and sdidl, each of which can be read by the cpu. the idcode command is set from the h-udi pin. this register can be read from the tdo when the tap state is shift-dr. writing is disabled. bit bit name initial value r/w description 31 to 0 did31 to did0 refer to description r device id31 to 0 device id register that is stipulated by jtag. h'001a200f (initial value) for this lsi. upper four bits may be changed by the chip version. sdidh corresponds to bits 31 to 16. sdidl corresponds to bits 15 to 0. rev. 1.0, 11/02, page 578 of 690 23.4 operation 23.4.1 tap controller figure 23.2 shows the internal states of the tap controller. state transitions basically conform to the jtag standard. test-logic-reset capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-dr-scan run-test/idle 1 0 0 0 0 11 1 1 0 0 1 0 1 1 10 capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-ir-scan 0 0 1 0 0 1 1 0 1 1 10 0 figure 23.2 tap controller state transitions note: the transition condition is the tms value at the rising edge of tck. the tdi value is sampled at the rising edge of tck; shifting occurs at the falling edge of tck. for details on change timing of the tdo value, see section 23.4.3, tdo output timing. the tdo is at high impedance, except with shift-dr and shift-ir states. during the change to trst = 0, there is a transition to test-logic-reset asynchronously with tck. rev. 1.0, 11/02, page 579 of 690 23.4.2 reset configuration table 23.4 reset configuration asemd0 asemd0 asemd0 asemd0 * 1 resetp resetp resetp resetp trst trst trst trst chip state h l l normal reset and h-udi reset * 4 hnormal reset * 4 h l h-udi reset only h normal operation l l l reset hold * 2 h in ase user mode * 3 : normal reset in ase break mode * 3 : resetp assert is masked h l h-udi reset only h normal operation notes: * 1 performs normal mode and ase mode settings asemd0 = h, normal mode asemd0 = l, ase mode * 2 in ase mode, reset hold is enabled by driving the resetp and trst pins low for a constant cycle. in this state, the cpu does not start up, even if resetp is driven high. when trst is driven high, h-udi operation is enabled, but the cpu does not start up. the reset hold state is canceled by the following: another resetp assert (power-on reset) trst reassert * 3 ase mode is classified into two modes; ase break mode to execute the firm program of an emulator and ase user mode to execute the user program. * 4 make sure the trst pin is low when the power is turned on. 23.4.3 tdo output timing the timing of data output from the tdo is switched by the command type set in the sdir. the timing changes at the tck falling edge when jtag commands (extest, clamp, highz, sample/preload, idcode, and bypass) are set. this is a timing of the jtag standard. when the h-udi commands (h-udi reset negate, h-udi reset assert, and h-udi interrupt) are set, tdo is output at the tck rising edge earlier than the jtag standard by a half cycle. rev. 1.0, 11/02, page 580 of 690 tdo (when the h-udi command is set) tck tdo (when the boundary scan command is set) t tdo t tdo figure 23.3 h-udi data transfer timing 23.4.4 h-udi reset an h-udi reset is executed by setting an h-udi reset assert command in sdir. an h-udi reset is of the same kind as a power-on reset. an h-udi reset is released by inputting an h-udi reset negate command. the required time between the h-udi reset assert command and h-udi reset negate command is the same as time for keeping the resetp pin low to apply a power-on reset. h-udi reset assert h-udi reset negate sdir chip internal reset cpu state branch to h'a0000000 figure 23.4 h-udi reset 23.4.5 h-udi interrupt the h-udi interrupt function generates an interrupt by setting a command from the h-udi in the sdir. an h-udi interrupt is a general exception/interrupt operation, resulting in a branch to an address based on the vbr value plus offset, and with return by the rte instruction. this interrupt request has a fixed priority level of 15. h-udi interrupts are accepted in sleep mode, but not in standby mode. rev. 1.0, 11/02, page 581 of 690 23.5 boundary scan a command can be set in sdir by the h-udi to place the h-udi pins in boundary scan mode stipulated by jtag. 23.5.1 supported instructions this lsi supports the three essential instructions defined in the jtag standard (bypass, sample/preload, and extest) and three option instructions (idcode, clamp, and highz). 1. bypass: the bypass instruction is an essential standard instruction that operates the bypass register. this instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. while this instruction is executing, the test circuit has no effect on the system circuits. the upper four bits of the instruction code are 1111. 2. sample/preload: the sample/preload instruction inputs values from this lsi's internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. when this instruction is executing, this lsi's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. this lsi's system circuits are not affected by execution of this instruction. the upper four bits of the instruction code are 0100. in a sample operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. snapshot latching is performed in synchronization with the rise of tck in the capture-dr state. snapshot latching does not affect normal operation of this lsi. in a preload operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the extest instruction. without a preload operation, when the extest instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the extest instruction, the parallel output latch value is constantly output to the output pin). rev. 1.0, 11/02, page 582 of 690 3. extest: this instruction is provided to test external circuitry when this lsi is mounted on a printed circuit board. when this instruction is executed, output pins are used to output test data (previously set by the sample/preload instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. if testing is carried out by using the extest instruction n times, the nth test data is scanned-in when test data (n-1) is scanned out. data loaded into the output pin boundary scan register in the capture-dr state is not used for external circuit testing (it is replaced by a shift operation). the upper four bits of the instruction code are 0000. 4. idcode: a command can be set in sdir by the h-udi pins to place the h-udi pins in the idcode mode stipulated by jtag. when the h-udi is initialized ( trst is asserted or tap is in the test-logic-reset state), the idcode mode is entered. 5. clamp, highz: a command can be set in sdir by the h-udi pins to place the h-udi pins in the clamp or highz mode stipulated by jtag. 23.5.2 points for attention 1. boundary scan mode does not cover clock-related signals (extal, extal2, xtal, xtal2, extal_usb, xtal_usb, and ckio). 2. boundary scan mode does not cover reset-related signals ( resetp , resetm , and ca). 3. boundary scan mode does not cover h-udi-related signals (tck, tdi, tdo, tms, and trst ). 4. fix the resetp pin low during boundary scan. 5. fix the ca pin high during boundary scan. 6. fix the asemd0 pin high during boundary scan. rev. 1.0, 11/02, page 583 of 690 23.6 usage notes 1. an h-udi command, once set, will not be modified as long as another command is not re- issued from the h-udi. if the same command is given continuously, the command must be set after a command (bypass, etc.) that does not affect chip operations is once set. 2. because chip operations are suspended in standby mode, h-udi commands are not accepted. to keep the tap state constant before and after standby mode, tck must be high during standby mode transition. 3. the h-udi is used for emulator connection. therefore, h-udi functions cannot be used when using an emulator. 23.7 advanced user debugger (aud) the aud is a function only for an emulator. for details on the aud, refer to each emulator?s user?s manual. rev. 1.0, 11/02, page 584 of 690 rev. 1.0, 11/02, page 585 of 690 section 24 list of registers this section gives information on the on-chip i/o registers and is configured as described below. 1. register addresses (by functional module, in order of the corresponding section numbers) ? descriptions by functional module, in order of the corresponding section numbers entries that consist of ? lines are for separation of the functional modules. ? access to reserved addresses which are not described in this list is prohibited. ? when registers consist of 16 or 32 bits, the addresses of the msbs are given, on the presumption of a big-endian system. 2. register bits ? bit configurations of the registers are described in the same order as the register addresses (by functional module, in order of the corresponding section numbers). ? reserved bits are indicated by ? in the bit name. ? no entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. ? when registers consist of 16 or 32 bits, bits are described from the msb side. the order in which bytes are described is on the presumption of a big-endian system. 3. register states in each operating mode ? register states are described in the same order as the register addresses (by functional module, in order of the corresponding section numbers). ? for the initial state of each bit, refer to the description of the register in the corresponding section. ? the register states described are for the basic operating modes. if there is a specific reset for an on-chip module, refer to the section on that on-chip module. rev. 1.0, 11/02, page 586 of 690 24.1 register addresses (by functional module, in order of the corresponding section numbers) entries under access size indicates numbers of bits. note: access to undefined or reserved addresses is prohibited. since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access. register name abbreviation number of bits address module access size mmu control register mmucr 32 h'ffff ffe0 mmu 32 page table entry register high pteh 32 h'ffff fff0 32 page table entry register low ptel 32 h'ffff fff4 32 translation table base register ttb 32 h'ffff fff8 32 ?????? cache control register 1 ccr1 32 h'ffff ffec cache 32 cache control register 2 ccr2 32 h'a400 00b0 32 cache control register 3 ccr3 32 h'a400 00b4 32 ?????? interrupt event register 2 intevt2 32 h'a400 0000 32 trapa exception register tra 32 h'ffff ffd0 exception handling 32 exception event register expevt 32 h'ffff ffd4 32 interrupt event register intevt 32 h'ffff ffd8 32 tlb exception address register tea 32 h'ffff fffc 32 ?????? interrupt priority level setting register a ipra 16 h'ffff fee2 intc 16 interrupt priority level setting register b iprb 16 h'ffff fee4 16 interrupt priority level setting register c iprc 16 h'a400 0016 16 interrupt priority level setting register d iprd 16 h'a400 0018 16 interrupt priority level setting register e ipre 16 h'a400 001a 16 interrupt priority level setting register f iprf 16 h'a408 0000 16 interrupt priority level setting register g iprg 16 h'a408 0002 16 interrupt priority level setting register h iprh 16 h'a408 0004 16 rev. 1.0, 11/02, page 587 of 690 register name abbreviation number of bits address module access size interrupt control register 0 icr0 16 h'ffff fee0 intc 16 interrupt control register 1 icr1 16 h'a400 0010 16 interrupt control register 2 icr2 16 h'a400 0012 16 interrupt request register 0 irr0 8 h'a400 0004 8 interrupt request register 1 irr1 8 h'a400 0006 8 interrupt request register 2 irr2 8 h'a400 0008 8 pint interrupt enable register pinter 16 h'a400 0014 16 ?????? common control register cmncr 32 h'a4fd 0000 bsc 32 bus control register for cs0 space cs0bcr 32 h'a4fd 0004 32 bus control register for cs2 space cs2bcr 32 h'a4fd 0008 32 bus control register for cs3 space cs3bcr 32 h'a4fd 000c 32 bus control register for cs4 space cs4bcr 32 h'a4fd 0010 32 bus control register for cs5a space cs5abcr 32 h'a4fd 0014 32 bus control register for cs5b space cs5bbcr 32 h'a4fd 0018 32 bus control register for cs6a space cs6abcr 32 h'a4fd 001c 32 bus control register for cs6b space cs6bbcr 32 h'a4fd 0020 32 wait control register for cs0 space cs0wcr 32 h'a4fd 0024 32 wait control register for cs2 space cs2 wcr 32 h'a4fd 0028 32 wait control register for cs3 space cs3 wcr 32 h'a4fd 002c 32 wait control register for cs4 space cs4 wcr 32 h'a4fd 0030 32 wait control register for cs5a space cs5a wcr 32 h'a4fd 0034 32 wait control register for cs5b space cs5b wcr 32 h'a4fd 0038 32 wait control register for cs6a space cs6a wcr 32 h'a4fd 003c 32 wait control register for cs6b space cs6b wcr 32 h'a4fd 0040 32 sdram control register sdcr 32 h'a4fd 0044 32 refresh timer control/status register rtcsr 32 h'a4fd 0048 32 refresh timer counter rtcnt 32 h'a4fd 004c 32 refresh time constant register rtcor 32 h'a4fd 0050 32 sdram mode register for cs2 space sdmr2 ? h'a4fd 4xxx * 2 16 sdram mode register for cs3 space sdmr3 ? h'a4fd 5xxx * 2 16 ?????? rev. 1.0, 11/02, page 588 of 690 register name abbreviation number of bits address module access size dma source address register_0 sar_0 32 h'a400 0020 dmac 16/32 dma destination address register_0 dar_0 32 h'a400 0024 16/32 dma transfer count register_0 dmatcr_0 32 h'a400 0028 16/32 dma channel control register_0 chcr_0 32 h'a400 002c 8/16/32 dma source address register_1 sar_1 32 h'a400 0030 16/32 dma destination address register_1 dar_1 32 h'a400 0034 16/32 dma transfer count register_1 dmatcr_1 32 h'a400 0038 16/32 dma channel control register_1 chcr_1 32 h'a400 003c 8/16/32 dma source address register_2 sar_2 32 h'a400 0040 16/32 dma destination address register_2 dar_2 32 h'a400 0044 16/32 dma transfer count register_2 dmatcr_2 32 h'a400 0048 16/32 dma channel control register_2 chcr_2 32 h'a400 004c 8/16/32 dma source address register_3 sar_3 32 h'a400 0050 16/32 dma destination address register_3 dar_3 32 h'a400 0054 16/32 dma transfer count register_3 dmatcr_3 32 h'a400 0058 16/32 dma channel control register_3 chcr_3 32 h'a400 005c 8/16/32 dma operation register dmaor 16 h'a400 0060 8/16 dma extended resource selector 0 dmars0 16 h'a409 0000 16 dma extended resource selector 1 dmars1 16 h'a409 0004 16 ?????? usb clock control register uclkcr 8 h'a40a 0008 cpg 8/16 * 1 frequency control register frqcr 16 h'ffff ff80 16 ?????? watchdog timer counter wtcnt 8 h'ffff ff84 wdt 8/16 * 1 watchdog timer control/status register wtcsr 8 h'ffff ff86 8/16 * 1 ?????? standby control register stbcr 8 h'ffff ff82 8 standby control register 2 stbcr2 8 h'ffff ff88 8 standby control register 3 stbcr3 8 h'a40a 0000 power-down modes 8 ?????? rev. 1.0, 11/02, page 589 of 690 register name abbreviation number of bits address module access size timer start register tstr 8 h'ffff fe92 tmu 8 timer constant register_0 tcor_0 32 h'ffff fe94 32 timer counter_0 tcnt_0 32 h'ffff fe98 32 timer control register_0 tcr_0 16 h'ffff fe9c 16 timer constant register_1 tcor_1 32 h'ffff fea0 32 timer counter_1 tcnt_1 32 h'ffff fea4 32 timer control register_1 tcr_1 16 h'ffff fea8 16 timer constant register_2 tcor_2 32 h'ffff feac 32 timer counter_2 tcnt_2 32 h'ffff feb0 32 timer control register_2 tcr_2 16 h'ffff feb4 16 input capture register_2 tcpr_2 32 h'ffff feb8 32 ?????? compare match timer start register cmstr 16 h'a400 0070 cmt 16 compare match timer control/status register cmcsr 16 h'a400 0074 16 compare match timer counter cmcnt 16 h'a400 0078 16 compare match timer constant register cmcor 16 h'a400 007c 16 ?????? timer start register tstr 16 h'a449 0000 tpu 16 timer control register_0 tcr_0 16 h'a449 0010 16 timer mode register_0 tmdr_0 16 h'a449 0014 16 timer i/o control register_0 tior_0 16 h'a449 0018 16 timer interrupt enable register_0 tier_0 16 h'a449 001c 16 timer status register_0 tsr_0 16 h'a449 0020 16 timer counter_0 tcnt_0 16 h'a449 0024 16 timer general register a_0 tgra_0 16 h'a449 0028 16 timer general register b_0 tgrb_0 16 h'a449 002c 16 timer general register c_0 tgrc_0 16 h'a449 0030 16 timer general register d_0 tgrd_0 16 h'a449 0034 16 timer control register_1 tcr_1 16 h'a449 0050 16 timer mode register_1 tmdr_1 16 h'a449 0054 16 timer i/o control register_1 tior_1 16 h'a449 0058 16 rev. 1.0, 11/02, page 590 of 690 register name abbreviation number of bits address module access size timer interrupt enable register_1 tier_1 16 h'a449 005c tpu 16 timer status register_1 tsr_1 16 h'a449 0060 16 timer counter_1 tcnt_1 16 h'a449 0064 16 timer general register a_1 tgra_1 16 h'a449 0068 16 timer general register b_1 tgrb_1 16 h'a449 006c 16 timer general register c_1 tgrc_1 16 h'a449 0070 16 timer general register d_1 tgrd_1 16 h'a449 0074 16 timer control register_2 tcr_2 16 h'a449 0090 16 timer mode register_2 tmdr_2 16 h'a449 0094 16 timer i/o control register_2 tior_2 16 h'a449 0098 16 timer interrupt enable register_2 tier_2 16 h'a449 009c 16 timer status register_2 tsr_2 16 h'a449 00a0 16 timer counter_2 tcnt_2 16 h'a449 00a4 16 timer general register a_2 tgra_2 16 h'a449 00a8 16 timer general register b_2 tgrb_2 16 h'a449 00ac 16 timer general register c_2 tgrc_2 16 h'a449 00b0 16 timer general register d_2 tgrd_2 16 h'a449 00b4 16 timer control register_3 tcr_3 16 h'a449 00d0 16 timer mode register_3 tmdr_3 16 h'a449 00d4 16 timer i/o control register_3 tior_3 16 h'a449 00d8 16 timer interrupt enable register_3 tier_3 16 h'a449 00dc 16 timer status register_3 tsr_3 16 h'a449 00e0 16 timer counter_3 tcnt_3 16 h'a449 00e4 16 timer general register a_3 tgra_3 16 h'a449 00e8 16 timer general register b_3 tgrb_3 16 h'a449 00ec 16 timer general register c_3 tgrc_3 16 h'a449 00f0 16 timer general register d_3 tgrd_3 16 h'a449 00f4 16 ?????? rev. 1.0, 11/02, page 591 of 690 register name abbreviation number of bits address module access size 64-hz counter r64cnt 8 h'ffff fec0 rtc 8 second counter rseccnt 8 h'ffff fec2 8 minute counter rmincnt 8 h'ffff fec4 8 hour counter rhrcnt 8 h'ffff fec6 8 day of week counter rwkcnt 8 h'ffff fec8 8 date counter rdaycnt 8 h'ffff feca 8 month counter rmoncnt 8 h'ffff fecc 8 year counter ryrcnt 16 h'ffff fece 16 second alarm register rsecar 8 h'ffff fed0 8 minute alarm register rminar 8 h'ffff fed2 8 hour alarm register rhrar 8 h'ffff fed4 8 day of week alarm register rwkar 8 h'ffff fed6 8 date alarm register rdayar 8 h'ffff fed8 8 month alarm register rmonar 8 h'ffff feda 8 rtc control register 1 rcr1 8 h'ffff fedc 8 rtc control register 2 rcr2 8 h'ffff fede 8 year alarm register ryrar 16 h'a413 fee0 16 rtc control register 3 rcr3 8 h'a413 fee4 8 ?????? serial mode register_0 scsmr_0 16 h'a440 0000 scif_0 16 bit rate register_0 scbrr_0 8 h'a440 0004 (channel 0) 8 serial control register_0 scscr_0 16 h'a440 0008 16 transmit data stop register_0 sctdsr_0 8 h'a440 000c 8 fifo error count register_0 scfer_0 16 h'a440 0010 16 serial status register_0 scssr_0 16 h'a440 0014 16 fifo control register_0 scfcr_0 16 h'a440 0018 16 fifo data count register_0 scfdr_0 16 h'a440 001c 16 transmit fifo data register_0 scftdr_0 8 h'a440 0020 8 receive fifo data register_0 scfrdr_0 8 h'a440 0024 8 ?????? rev. 1.0, 11/02, page 592 of 690 register name abbreviation number of bits address module access size serial mode register_2 scsmr_2 16 h'a441 0000 scif_2 16 bit rate register_2 scbrr_2 8 h'a441 0004 (channel 2) 8 serial control register_2 scscr_2 16 h'a441 0008 16 transmit data stop register_2 sctdsr_2 8 h'a441 000c 8 fifo error count register_2 scfer_2 16 h'a441 0010 16 serial status register_2 scssr_2 16 h'a441 0014 16 fifo control register_2 scfcr_2 16 h'a441 0018 16 fifo data count register_2 scfdr_2 16 h'a441 001c 16 transmit fifo data register_2 scftdr_2 8 h'a441 0020 8 receive fifo data register_2 scfrdr_2 8 h'a441 0024 8 ?????? irda mode register scsmr_ir 16 h'a44a 0000 irda 16 ?????? ep0i data register epdr0i 8b h'a448 0000 usb 8 ep0o data register epdr0o 8b h'a448 0004 8 ep0s data register epdr0s 8b h'a448 0008 8 ep1 data register epdr1 128b h'a448 000c 8 ep2 data register epdr2 128b h'a448 0010 8 ep3 data register epdr3 8b h'a448 0014 8 interrupt flag register 0 ifr0 8 h'a448 0018 8 interrupt flag register 1 ifr1 8 h'a448 001c 8 trigger register trg 8 h'a448 0020 8 fifo clear register fclr 8 h'a448 0024 8 ep0o receive data size register epsz0o 8 h'a448 0028 8 data status register dasts 8 h'a448 002c 8 endpoint stall register epstl 8 h'a448 0030 8 interrupt enable register 0 ier0 8 h'a448 0034 8 interrupt enable register 1 ier1 8 h'a448 0038 8 ep1 receive data size register epsz1 8 h'a448 003c 8 dma transfer setting register dmar 8 h'a448 0040 8 interrupt select register 0 isr0 8 h'a448 0044 8 interrupt select register 1 isr1 8 h'a448 0048 8 transceiver control register xvercr 8 h'a448 0060 8 rev. 1.0, 11/02, page 593 of 690 register name abbreviation number of bits address module access size ?????? port a control register pacr 16 h'a400 0100 pfc 16 port b control register pbcr 16 h'a400 0102 16 port c control register pccr 16 h'a400 0104 16 port d control register pdcr 16 h'a400 0106 16 port e control register pecr 16 h'a400 0108 16 port e control register 2 pecr2 8 h'a405 0148 8 port f control register pfcr 16 h'a400 010a 16 port f control register 2 pfcr2 8 h'a405 014a 8 port g control register pgcr 16 h'a400 010c 16 port h control register phcr 16 h'a400 010e 16 port j control register pjcr 16 h'a400 0110 16 port k control register pkcr 16 h'a400 0112 16 port l control register plcr 16 h'a400 0114 16 port sc control register scpcr 16 h'a400 0116 16 port m control register pmcr 16 h'a400 0118 16 port n control register pncr 16 h'a400 011a 16 port n control register 2 pncr2 8 h'a405 015a 8 ?????? port a data register padr 8 h'a400 0120 port 8 port b data register pbdr 8 h'a400 0122 8 port c data register pcdr 8 h'a400 0124 8 port d data register pddr 8 h'a400 0126 8 port e data register pedr 8 h'a400 0128 8 port f data register pfdr 8 h'a400 012a 8 port g data register pgdr 8 h'a400 012c 8 port h data register phdr 8 h'a400 012e 8 port j data register pjdr 8 h'a400 0130 8 port k data register pkdr 8 h'a405 0132 8 port l data register pldr 8 h'a400 0134 8 sc port data register scpdr 8 h'a400 0136 8 port m data register pmdr 8 h'a400 0138 8 port n data register pndr 8 h'a400 013a 8 rev. 1.0, 11/02, page 594 of 690 register name abbreviation number of bits address module access size ?????? a/d data register a addra 16 h'a400 0080 adc 16 a/d data register b addrb 16 h'a400 0082 16 a/d data register c addrc 16 h'a400 0084 16 a/d data register d addrd 16 h'a400 0086 16 a/d control/status register adcsr 16 h'a400 0088 16 ?????? break data register b bdrb 32 h'ffff ff90 ubc 32 break data mask register b bdmrb 32 h'ffff ff94 32 break control register brcr 32 h'ffff ff98 32 execution count break register betr 16 h'ffff ff9c 16 break address register b barb 32 h'ffff ffa0 32 break address mask register b bamrb 32 h'ffff ffa4 32 break bus cycle register b bbrb 16 h'ffff ffa8 16 branch source register brsr 32 h'ffff ffac 32 break address register a bara 32 h'ffff ffb0 32 break address mask register a bamra 32 h'ffff ffb4 32 break bus cycle register a bbra 16 h'ffff ffb8 16 branch destination register brdr 32 h'ffff ffbc 32 break asid register a basra 8 h'ffff ffe4 8 break asid register b basrb 8 h'ffff ffe8 8 ?????? instruction register sdir 16 h'a400 0200 h-udi 16 id register sdid/sdidh 16 h'a400 0214 16 id register sdidl 16 h'a400 0216 16 note: * 1 8 bits when reading and 16 bits when writing. * 2 the value of xxx depends on the setting value because of access control for the sdram mode register. rev. 1.0, 11/02, page 595 of 690 24.2 register bits register addresses and bit names of the on-chip peripheral modules are described below. each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module mmucr ?? ??? ? ?? mmu ?? ??? ? ?? ?? ??? ? ? sv ?? rc1 rc0 ? tf ix at pteh vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn ?? asid7 asid6 asid5 asid4 asid3 asid2 asid1 asid0 ptel ?? ? ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ? v ? pr1 pr0 sz c d sh ? ttb rev. 1.0, 11/02, page 596 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ccr1 ?? ??? ? ?? cache ?? ??? ? ?? ?? ??? ? ?? ?? ?? cf cb wt ce ccr2 ?? ??? ? ?? ?? ??? ? ? le ?? ??? ? w3load w3lock ?? ??? ? w2load w2lock ccr3 ?? ??? ? ?? csize7 csize6 csize5 csize4 csize3 csize2 csize1 csize0 ?? ??? ? ?? ?? ??? ? ?? intevt2 ?? ??? ? ?? ?? ??? ? ?? ?? ?? exception handing tra ?? ??? ? ?? ?? ??? ? ?? ?? ??? ? imm imm imm imm imm imm imm imm ?? expevt ?? ??? ? ?? ?? ??? ? ?? ?? ?? intevt ?? ??? ? ?? ?? ??? ? ?? ?? ?? rev. 1.0, 11/02, page 597 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module tea exception handing ipra ipr15 ipr14 ipr13 ipr12 ipr11 ipr10 ipr9 ipr8 intc ipr7 ipr6 ipr5 ipr4 ipr3 ipr2 ipr1 ipr0 iprb ipr15 ipr14 ipr13 ipr12 ipr11 ipr10 ipr9 ipr8 ipr7 ipr6 ipr5 ipr4 ipr3 ipr2 ipr1 ipr0 iprc ipr15 ipr14 ipr13 ipr12 ipr11 ipr10 ipr9 ipr8 ipr7 ipr6 ipr5 ipr4 ipr3 ipr2 ipr1 ipr0 iprd ipr15 ipr14 ipr13 ipr12 ipr11 ipr10 ipr9 ipr8 ipr7 ipr6 ipr5 ipr4 ipr3 ipr2 ipr1 ipr0 ipre ipr15 ipr14 ipr13 ipr12 ipr11 ipr10 ipr9 ipr8 ipr7 ipr6 ipr5 ipr4 ipr3 ipr2 ipr1 ipr0 iprf ipr15 ipr14 ipr13 ipr12 ipr11 ipr10 ipr9 ipr8 ipr7 ipr6 ipr5 ipr4 ipr3 ipr2 ipr1 ipr0 iprg ipr15 ipr14 ipr13 ipr12 ipr11 ipr10 ipr9 ipr8 ipr7 ipr6 ipr5 ipr4 ipr3 ipr2 ipr1 ipr0 iprh ipr15 ipr14 ipr13 ipr12 ipr11 ipr10 ipr9 ipr8 ipr7 ipr6 ipr5 ipr4 ipr3 ipr2 ipr1 ipr0 icr0 nmil ? ??? ? ? nmie ?? ??? ? ?? icr1 mai irqlvl blmsk ? irq51s irq50s irq41s irq40s irq31s irq30s irq21s irq20s irq11s irq10s irq01s irq00s icr2 pint15s pint14s pint13s pint12s pint11s pint10s pint9s pint8s pint7s pint6s pint5s pint4s pint3s pint2s pint1s pint0s irr0 pint0r pint1r irq5r irq4r irq3r irq2r irq1r irq0r irr1 txi0r ? rxi0r eri0r dei3r dei2r dei1r dei0r irr2 ?? ? adir txi2r ? rxi2r eri2r pinter pint15e pint14e pint13e pint12e pint11e pint10e pint9e pint8e pint7e pint6e pint5e pint4e pint3e pint2e pint1e pint0e rev. 1.0, 11/02, page 598 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module cmncr ?? ??? ? ?? bsc ?? ??? ? ?? ?? ??? ? ?? dmaiw1 dmaiw0 dmaiwa ? endian ? hizmem hizcnt cs0bcr ?? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 ? type2 type1 type0 ? bsz1 bsz0 ? ?? ??? ? ?? cs2bcr ?? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 ? type2 type1 type0 ? bsz1 bsz0 ? ?? ??? ? ?? cs3bcr ?? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 ? type2 type1 type0 ? bsz1 bsz0 ? ?? ??? ? ?? cs4bcr ?? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 ? type2 type1 type0 ? bsz1 bsz0 ? ?? ??? ? ?? cs5abcr ?? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 ? type2 type1 type0 ? bsz1 bsz0 ? ?? ??? ? ?? cs5bbcr ?? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 ? type2 type1 type0 ? bsz1 bsz0 ? ?? ??? ? ?? cs6abcr ?? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 ? type2 type1 type0 ? bsz1 bsz0 ? ?? ??? ? ?? rev. 1.0, 11/02, page 599 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module cs6bbcr ?? iww1 iww0 ? iwrwd1 iwrwd0 ? bsc iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 ? type2 type1 type0 ? bsz1 bsz0 ? ?? ??? ? ?? ?? ??? ? ?? ?? ??? ? ?? ?? ? sw1 sw0 wr3 wr2 wr1 cs0wcr (except burst rom) wr0 wm ??? ? hw1 hw0 ?? ??? ? ?? ?? ??? ? bw1 bw0 ?? ??? w3 w2 w1 cs0wcr (burst rom) w0 wm ??? ? ?? ?? ??? ? ?? ?? ??? ? ?? ?? ??? wr3 wr2 wr1 cs2 wcr (except sdram) wr0 wm ??? ? ?? ?? ??? ? ?? ?? ??? ? ?? ?? ??? ? ? a2cl1 cs2 wcr (sdram) a2cl0 ? ??? ? ?? ?? ??? ? ?? ?? ??? ? ?? ?? ??? wr3 wr2 wr1 cs3 wcr (except sdram) wr0 wm ??? ? ?? ?? ??? ? ?? ?? ??? ? ?? ? trp1 trp0 ? trcd1 trcd0 ? a3cl1 cs3 wcr (sdram) a3cl0 ??? trwl1 trwl0 trc1 trc0 ?? ??? ? ?? ?? ??? ww2 ww1 ww0 ?? ? sw1 sw0 wr3 wr2 wr1 cs4 wcr (except burst rom) wr0 wm ??? ? hw1 hw0 rev. 1.0, 11/02, page 600 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ?? ??? ? ?? bsc ?? ??? ? bw1 bw0 ?? ? sw1 sw0 w3 w2 w1 cs4 wcr (burst rom) w0 wm ??? ? hw1 hw0 cs5a wcr ?? ??? ? ?? ?? ??? ww2 ww1 ww0 ?? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ??? ? hw1 hw0 cs5b wcr ?? ??? ? ?? ?? ? mpxw ? ww2 ww1 ww0 ?? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ??? ? hw1 hw0 cs6a wcr ?? ??? ? ?? ?? ??? ? ?? ?? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ??? ? hw1 hw0 cs6b wcr ?? ??? ? ?? ?? ??? ? ?? ?? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ??? ? hw1 hw0 sdcr ?? ??? ? ?? ?? ? a2row1 a2row0 ? a2col1 a2col0 ?? ? slow rfsh rmode ? bactv ?? ? a3row1 a3row0 ? a3col1 a3col0 rtcsr ?? ??? ? ?? ?? ??? ? ?? ?? ??? ? ?? cmf cmie cks2 cks1 cks0 rrc2 rrc1 rrc0 rtcnt ?? ??? ? ?? rtcor ?? ??? ? ?? rev. 1.0, 11/02, page 601 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module sdmr2 bsc sdmr3 sar_0 dmac dar_0 dmatcr_0 ?? ??? ? ?? chcr_0 ?? ??? ? ?? do tl ??? ? am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 dl ds tb ts1 ts0 ie te de sar_1 dar_1 dmatcr_1 ?? ??? ? ?? rev. 1.0, 11/02, page 602 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module chcr_1 ?? ??? ? ?? dmac do ? ??? ? am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 dl ds tb ts1 ts0 ie te de sar_2 dar_2 dmatcr_2 ?? ??? ? ?? chcr_2 ?? ??? ? ?? ?? ??? ? ?? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 ?? tb ts1 ts0 ie te de sar_3 dar_3 ?? ??? ? ?? dmatcr_3 rev. 1.0, 11/02, page 603 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module chcr_3 ?? ??? ? ?? dmac ?? ??? ? ?? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 ?? tb ts1 ts0 ie te de dmaor ?? cms1 cms0 ?? pr1 pr0 ?? ??? ae nmif dme dmars0 c1mid5 c1mid4 c1mid3 c1mid2 c1mid1 c1mid0 c1rid1 c1rid0 c0mid5 c0mid4 c0mid3 c0mid2 c0mid1 c0mid0 c0rid1 c0rid0 dmars1 c3mid5 c3mid4 c3mid3 c3mid2 c3mid1 c3mid0 c3rid1 c3rid0 c2mid5 c2mid4 c2mid3 c2mid2 c2mid1 c2mid0 c2rid1 c2rid0 uclkcr usscs1 usscs0 usben ?? ? ?? cpg frqcr ?? ? ckoen ?? stc1 stc0 ?? ifc1 ifc0 ?? pfc1 pfc0 wtcnt wtcsr tme wt/it rsts wovf iovf cks2 cks1 cks0 wdt stbcr stby ?? stbxtl ? mstp2 mstp1 ? stbcr2 mstp10 mstp9 mstp8 ? mstp6 mstp5 ?? stbcr3 mstp37 ? mstp35 mstp34 mstp33 mstp32 mstp31 mstp30 power- down modes tstr ?? ??? str2 str1 str0 tmu tcor_0 tcnt_0 ?? ??? ? ? unf tcr_0 ?? unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 rev. 1.0, 11/02, page 604 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module tcor_1 tmu tcnt_1 tcr_1 ?? ??? ? ? unf ?? unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tcor_2 tcnt_2 tcr_2 ?? ??? ? icpf unf icpe1 icpe0 unie ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tcpr_2 cmstr ?? ??? ? ?? cmt ?? ??? ? ? str cmcsr ?? ??? ? ?? cmf ?? cmr ?? cks1 cks0 cmcnt cmcor rev. 1.0, 11/02, page 605 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module tstr ?? ??? ? ?? tpu ?? ? ? cst3 cst2 cst1 cst0 tcr_0 ?? ??? ? ?? cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_0 ?? ??? ? ?? ? bfwt bfb bfa ? md2 md1 md0 tior_0 ?? ??? ? ?? ?? ??? ioa2 ioa1 ioa0 tier_0 ?? ??? ? ?? ?? ? tciev tgied tgiec tgieb tgiea tsr_0 ?? ??? ? ?? ?? ? tcfv tgfd tgfc tgfb tgfa tcnt_0 tgra_0 tgrb_0 tgrc_0 tgrd_0 tcr_1 ?? ??? ? ?? cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_1 ?? ??? ? ?? ? bfwt bfb bfa ? md2 md1 md0 tior_1 ?? ??? ? ?? ?? ??? ioa2 ioa1 ioa0 tier_1 ?? ??? ? ?? ?? ? tciev tgied tgiec tgieb tgiea tsr_1 ?? ??? ? ?? ?? ? tcfv tgfd tgfc tgfb tgfa rev. 1.0, 11/02, page 606 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module tcnt_1 tpu tgra_1 tgrb_1 tgrc_1 tgrd_1 tcr_2 ?? ??? ? ?? cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_2 ?? ??? ? ?? ? bfwt bfb bfa ? md2 md1 md0 tior_2 ?? ??? ? ?? ?? ??? ioa2 ioa1 ioa0 tier_2 ?? ??? ? ?? ?? ? tciev tgied tgiec tgieb tgiea tsr_2 ?? ??? ? ?? ?? ? tcfv tgfd tgfc tgfb tgfa tcnt_2 tgra_2 tgrb_2 tgrc_2 tgrd_2 tcr_3 ?? ??? ? ?? cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 rev. 1.0, 11/02, page 607 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module tmdr_3 ?? ??? ? ?? tpu ? bfwt bfb bfa ? md2 md1 md0 tior_3 ?? ??? ? ?? ?? ??? ioa2 ioa1 ioa0 tier_3 ?? ??? ? ?? ?? ? tciev tgied tgiec tgieb tgiea tsr_3 ?? ??? ? ?? ?? ? tcfv tgfd tgfc tgfb tgfa tcnt_3 tgra_3 tgrb_3 tgrc_3 tgrd_3 r64cnt ? 1hz 2hz 4hz 8hz 16hz 32hz 64hz rtc rseccnt ? rmincnt ? rhrcnt ?? rwkcnt ?? ??? rdaycnt ?? rmoncnt ?? ? ryrcnt rsecar enb rminar enb rhrar enb ? rwkar enb ? ??? rdayar enb ? rmonar enb ?? rev. 1.0, 11/02, page 608 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module rcr1 cf ?? cie aie ?? af rtc rcr2 pef pes2 pes1 pes0 rtcen adj reset start ryrar rcr3 yaen ? ??? ? ?? scsmr_0 ?? ??? src2 src1 src0 scif_0 c/a chr pe o/e stop ? cks1 cks0 scbrr_0 scbrd7 scbrd6 scbrd5 scbrd4 scbrd3 scbrd2 scbrd1 scbrd0 scscr_0 ?? ? ? tsie erie brie drie tie rie te re ?? cke1 cke0 sctdsr_0 scfer_0 ?? per5 per4 per3 per2 per1 per0 ?? fer5 fer4 fer3 fer2 fer1 fer0 scssr_0 ?? ??? ? orer tsf er tend tdfe brk fer per rdf dr scfcr_0 tse tcrst ??? rstrg2 rstrg1 rstrg0 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop scfdr_0 ? t6 t5 t4 t3 t2 t1 t0 ? r6 r5 r4 r3 r2 r1 r0 scftdr_0 scftd7 scftd6 scftd5 scftd4 scftd3 scftd2 scftd1 scftd0 scfrdr_0 scfrd7 scfrd6 scfrd5 scfrd4 scfrd3 scfrd2 scfrd1 scfrd0 scsmr_2 ?? ??? src2 src1 src0 scif_2 c/a chr pe o/e stop ? cks1 cks0 scbrr_2 scbrd7 scbrd6 scbrd5 scbrd4 scbrd3 scbrd2 scbrd1 scbrd0 scscr_2 ?? ? ? tsie erie brie drie tie rie te re ?? cke1 cke0 sctdsr_2 scfer_2 ?? per5 per4 per3 per2 per1 per0 ?? fer5 fer4 fer3 fer2 fer1 fer0 scssr_2 ?? ??? ? orer tsf er tend tdfe brk fer per rdf dr scfcr_2 tse tcrst ??? rstrg2 rstrg1 rstrg0 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop rev. 1.0, 11/02, page 609 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module scfdr_2 ? t6 t5 t4 t3 t2 t1 t0 scif_2 ? r6 r5 r4 r3 r2 r1 r0 scftdr_2 scftd7 scftd6 scftd5 scftd4 scftd3 scftd2 scftd1 scftd0 scfrdr_2 scfrd7 scfrd6 scfrd5 scfrd4 scfrd3 scfrd2 scfrd1 scfrd0 scsmr_ir ?? ?? ? ? ? ? irda irmod ick3 ick2 ick1 ick0 psel ?? epdr0i d7 d6 d5 d4 d3 d2 d1 d0 usb epdr0o d7 d6 d5 d4 d3 d2 d1 d0 epdr0s d7 d6 d5 d4 d3 d2 d1 d0 epdr1 d7 d6 d5 d4 d3 d2 d1 d0 epdr2 d7 d6 d5 d4 d3 d2 d1 d0 epdr3 d7 d6 d5 d4 d3 d2 d1 d0 ifr0 brst ep1full ep2tr ep2empty setupts ep0ots ep0itr ep0its ifr1 ?? ?? vbusmn ep3tr ep3ts vbus trg ? ep3pkte ep1rdfn ep2pkte ? ep0srdfn ep0ordfn ep0ipkte fclr ? ep3clr ep1clr ep2clr ?? ep0oclr ep0iclr epsz0o d7 d6 d5 d4 d3 d2 d1 d0 dasts ?? ep3de ep2de ?? ? ep0ide epstl ?? ?? ep3stl ep2stl ep1stl ep0stl ier0 brst ep1full ep2tr ep2empty setupts ep0ots ep0itr ep0its ier1 ?? ?? ? ep3tr ep3ts vbus epsz1 d7 d6 d5 d4 d3 d2 d1 d0 dmar ?? ?? ? ? ep2dmae ep1dmae isr0 brst ep1full ep2tr ep2empty setupts ep0ots ep0itr ep0its isr1 ?? ?? ? ep3tr ep3ts vbus xvercr ?? ?? ? ? ? xveroff pacr pa7md1 pa7md0 pa6md1 pa6md0 pa5md1 pa5md0 pa4md1 pa4md0 pfc pa3md1 pa3md0 pa2md1 pa2md0 pa1md1 pa1md0 pa0md1 pa0md0 pbcr pb7md1 pb7md0 pb6md1 pb6md0 pb5md1 pb5md0 pb4md1 pb4md0 pb3md1 pb3md0 pb2md1 pb2md0 pb1md1 pb1md0 pb0md1 pb0md0 pccr pc7md1 pc7md0 pc6md1 pc6md0 pc5md1 pc5md0 pc4md1 pc4md0 pc3md1 pc3md0 pc2md1 pc2md0 pc1md1 pc1md0 pc0md1 pc0md0 rev. 1.0, 11/02, page 610 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module pdcr pd7md1 pd7md0 pd6md1 pd6md0 pd5md1 pd5md0 pd4md1 pd4md0 pfc pd3md1 pd3md0 pd2md1 pd2md0 pd1md1 pd1md0 pd0md1 pd0md0 pecr pe7md1 pe7md0 pe6md1 pe6md0 pe5md1 pe5md0 pe4md1 pe4md0 pe3md1 pe3md0 pe2md1 pe2md0 pe1md1 pe1md0 pe0md1 pe0md0 pecr2 ? pe6md2 pe5md2 pe4md2 ???? pfcr pf7md1 pf7md0 pf6md1 pf6md0 pf5md1 pf5md0 pf4md1 pf4md0 pf3md1 pf3md0 pf2md1 pf2md0 pf1md1 pf1md0 pf0md1 pf0md0 pfcr2 ? ??? pf3md2 pf2md2 pf1md2 pf0md2 pgcr pg7md1 pg7md0 pg6md1 pg6md0 pg5md1 pg5md0 pg4md1 pg4md0 pg3md1 pg3md0 pg2md1 pg2md0 pg1md1 pg1md0 pg0md1 pg0md0 phcr ?? ph6md1 ph6md0 ph5md1 ph5md0 ph4md1 ph4md0 ph3md1 ph3md0 ph2md1 ph2md0 ph1md1 ph1md0 ph0md1 ph0md0 pjcr pj7md1 pj7md0 pj6md1 pj6md0 pj5md1 pj5md0 pj4md1 pj4md0 pj3md1 pj3md0 pj2md1 pj2md0 pj1md1 pj1md0 pj0md1 pj0md0 pkcr pk7md1 pk7md0 pk6md1 pk6md0 pk5md1 pk5md0 pk4md1 pk4md0 pk3md1 pk3md0 pk2md1 pk2md0 pk1md1 pk1md0 pk0md1 pk0md0 plcr ? ???? ? ? ? pl3md1 pl3md0 pl2md1 pl2md0 pl1md1 pl1md0 pl0md1 pl0md0 scpcr ? ??? scp5md1 scp5md0 scp4md1 scp4md0 scp3md1 scp3md0 scp2md1 scp2md0 scp1md1 scp1md0 scp0md1 scp0md0 pmcr ?? pm6md1 pm6md0 ?? pm4md1 pm4md0 pm3md1 pm3md0 pm2md1 pm2md0 pm1md1 pm1md0 pm0md1 pm0md0 pncr pn7md1 pn7md0 pn6md1 pn6md0 pn5md1 pn5md0 pn4md1 pn4md0 pn3md1 pn3md0 pn2md1 pn2md0 pn1md1 pn1md0 pn0md1 pn0md0 pncr2 ? pn6md2 pn5md2 pn4md2 pn3md2 pn2md2 pn1md2 pn0md2 padr pa7dt pa6dt pa5dt pa4dt pa3dt pa2dt pa1dt pa0dt port pbdr pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt pcdr pc7dt pc6dt pc5dt pc4dt pc3dt pc2dt pc1dt pc0dt pddr pd7dt pd6dt pd5dt pd4dt pd3dt pd2dt pd1dt pd0dt pedr pe7dt pe6dt pe5dt pe4dt pe3dt pe2dt pe1dt pe0dt pfdr pf7dt pf6dt pf5dt pf4dt pf3dt pf2dt pf1dt pf0dt pgdr pg7dt pg6dt pg5dt pg4dt pg3dt pg2dt pg1dt pg0dt rev. 1.0, 11/02, page 611 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module phdr ? ph6dt ph5dt ph4dt ph3dt ph2dt ph1dt ph0dt port pjdr pj7dt pj6dt pj5dt pj4dt pj3dt pj2dt pj1dt pj0dt pkdr pk7dt pk6dt pk5dt pk4dt pk3dt pk2dt pk1dt pk0dt pldr ? ??? pl3dt pl2dt pl1dt pl0dt scpdr ?? scp 5dt scp 4dt scp 3dt scp 2dt scp 1dt scp 0dt pmdr ? pm6dt ? pm4dt pm3dt pm2dt pm1dt pm0dt pndr pn7dt pn6dt pn5dt pn4dt pn3dt pn2dt pn1dt pn0dt addra adc ??? ? ? ? addrb ??? ? ? ? addrc ??? ? ? ? addrd ??? ? ? ? adcsr adf adie adst dmasl ???? cks1 cks0 multi1 multi0 ?? ch1 ch0 bdrb bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 ubc bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 bdmrb bdmb31 bdmb30 bdmb29 bdmb28 bdmb27 bdmb26 bdmb25 bdmb24 bdmb23 bdmb22 bdmb21 bdmb20 bdmb19 bdmb18 bdmb17 bdmb16 bdmb15 bdmb14 bdmb13 bdmb12 bdmb11 bdmb10 bdmb9 bdmb8 bdmb7 bdmb6 bdmb5 bdmb4 bdmb3 bdmb2 bdmb1 bdmb0 brcr ????? ? ? ? ?? basma basmb ???? scmfca scmfcb scmfda scmfdb pcte pcba ?? dbeb pcbb ?? seq ?? etbe betr ???? bet11 bet10 bet9 bet8 bet7 bet6 bet5 bet4 bet3 bet2 bet1 bet0 rev. 1.0, 11/02, page 612 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module barb bab31 bab30 bab29 bab28 bab27 bab26 bab25 bab24 ubc bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 bamrb bamb31 bamb30 bamb29 bamb28 bamb27 bamb26 bamb25 bamb24 bamb23 bamb22 bamb21 bamb20 bamb19 bamb18 bamb17 bamb16 bamb15 bamb14 bamb13 bamb12 bamb11 bamb10 bamb9 bamb8 bamb7 bamb6 bamb5 bamb4 bamb3 bamb2 bamb1 bamb0 bbrb ? ???? ? ? ? cdb1 cdb0 idb1 idb0 rwb1 rwb0 szb1 szb0 brsr svf ??? bsa27 bsa26 bsa25 bsa24 bsa23 bsa22 bsa21 bsa20 bsa19 bsa18 bsa17 bsa16 bsa15 bsa14 bsa13 bsa12 bsa11 bsa10 bsa9 bsa8 bsa7 bsa6 bsa5 bsa4 bsa3 bsa2 bsa1 bsa0 bara baa31 baa30 baa29 baa28 baa27 baa26 baa25 baa24 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 bamra bama31 bama30 bama29 bama28 bama27 bama26 bama25 bama24 bama23 bama22 bama21 bama20 bama19 bama18 bama17 bama16 bama15 bama14 bama13 bama12 bama11 bama10 bama9 bama8 bama7 bama6 bama5 bama4 bama3 bama2 bama1 bama0 bbra ? ???? ? ? ? cda1 cda0 ida1 ida0 rwa1 rwa0 sza1 sza0 brdr dvf ??? bda27 bda26 bda25 bda24 bda23 bda22 bda21 bda20 bda19 bda18 bda17 bda16 bda15 bda14 bda13 bda12 bda11 bda10 bda9 bda8 bda7 bda6 bda5 bda4 bda3 bda2 bda1 bda0 basra basa7 basa6 basa5 basa4 basa3 basa2 basa1 basa0 basrb basb7 basb6 basb5 basb4 basb3 basb2 basb1 basb0 rev. 1.0, 11/02, page 613 of 690 register abbreviation bit 31/ 23/15/7 bit 30/ 22/14/6 bit 29/ 21/13/5 bit 28/ 20/12/4 bit 27/ 19/11/3 bit 26/ 18/10/2 bit 25/ 17/9/1 bit 24/ 16/8/0 module ti7 ti6 ti5 ti4 ti3 ti2 ti1 ti0 sdir ? ???? ? ? ? h-udi did31 did30 did29 did28 did27 did26 did25 did24 sdid/sdidh did23 did22 did21 did20 did19 did18 did17 did16 did15 did14 did13 did12 did11 did10 did9 did8 sdidl did7 did6 did5 did4 did3 did2 did1 did0 rev. 1.0, 11/02, page 614 of 690 24.3 register states in each operating mode register abbreviation power-on reset manual reset software standby module standby sleep module mmucr initialized * 6 initialized * 6 retained retained retained mmu pteh undefined undefined retained retained retained ptel undefined undefined retained retained retained ttb undefined undefined retained retained retained ccr1 initialized initialized retained retained retained cache ccr2 initialized initialized retained retained retained ccr3 initialized initialized retained retained retained intevt2 undefined undefined retained retained retained tra undefined undefined retained retained retained exception handling expevt initialized * 7 initialized * 7 retained retained retained intevt undefined undefined retained retained retained tea undefined undefined retained retained retained ipra initialized initialized retained retained retained intc iprb initialized initialized retained retained retained iprc initialized initialized retained retained retained iprd initialized initialized retained retained retained ipre initialized initialized retained retained retained iprf initialized initialized retained retained retained iprg initialized initialized retained retained retained iprh initialized initialized retained retained retained icr0 initialized * 8 initialized * 8 retained retained retained icr1 initialized initialized retained retained retained icr2 initialized initialized retained retained retained irr0 initialized initialized retained retained retained irr1 initialized initialized retained retained retained irr2 initialized initialized retained retained retained pinter initialized initialized retained retained retained cmncr initialized * 9 retained retained retained retained bsc cs0bcr initialized retained retained retained retained cs2bcr initialized retained retained retained retained cs3bcr initialized retained retained retained retained cs4bcr initialized retained retained retained retained rev. 1.0, 11/02, page 615 of 690 register abbreviation power-on reset manual reset software standby module standby sleep module cs5abcr initialized retained retained retained retained bsc cs5bbcr initialized retained retained retained retained cs6abcr initialized retained retained retained retained cs6bbcr initialized retained retained retained retained cs0wcr initialized retained retained retained retained cs2 wcr initialized retained retained retained retained cs3 wcr initialized retained retained retained retained cs4 wcr initialized retained retained retained retained cs5a wcr initialized re4ained retained retained retained cs5b wcr initialized retained retained retained retained cs6a wcr initialized retained retained retained retained cs6b wcr initialized retained retained retained retained sdcr initialized retained retained retained retained rtcsr initialized retained retained retained retained rtcnt initialized retained retained retained retained rtcor initialized retained retained retained retained sdmr2 ????? sdmr3 ????? sar_0 undefined undefined retained retained retained dmac dar_0 undefined undefined retained retained retained dmatcr_0 undefined undefined retained retained retained chcr_0 initialized initialized retained retained retained sar_1 undefined undefined retained retained retained dar_1 undefined undefined retained retained retained dmatcr_1 undefined undefined retained retained retained chcr_1 initialized initialized retained retained retained sar_2 undefined undefined retained retained retained dar_2 undefined undefined retained retained retained dmatcr_2 undefined undefined retained retained retained chcr_2 initialized initialized retained retained retained sar_3 undefined undefined retained retained retained dar_3 undefined undefined retained retained retained rev. 1.0, 11/02, page 616 of 690 register abbreviation power-on reset manual reset software standby module standby sleep module dmatcr_3 undefined undefined retained retained retained dmac chcr_3 initialized initialized retained retained retained dmaor initialized initialized retained retained retained dmars0 initialized initialized retained retained retained dmars1 initialized initialized retained retained retained uclkcr initialized retained retained retained retained cpg frqcr initialized * 5 retained retained retained retained wtcnt initialized * 5 retained retained retained retained wdt wtcsr initialized * 5 retained retained retained retained stbcr initialized retained retained retained retained stbcr2 initialized retained retained retained retained stbcr3 initialized retained retained retained retained power-down modes tstr initialized initialized initialized initialized retained tmu tcor_0 initialized initialized retained retained retained tcnt_0 initialized initialized retained retained retained tcr_0 initialized initialized retained retained retained tcor_1 initialized initialized retained retained retained tcnt_1 initialized initialized retained retained retained tcr_1 initialized initialized retained retained retained tcor_2 initialized initialized retained retained retained tcnt_2 initialized initialized retained retained retained tcr_2 initialized initialized retained retained retained tcpr_2 undefined undefined retained retained retained cmstr initialized initialized retained retained retained cmt cmcsr initialized initialized retained retained retained cmcnt initialized initialized retained retained retained cmcor initialized initialized retained retained retained rev. 1.0, 11/02, page 617 of 690 register abbreviation power-on reset manual reset software standby module standby sleep module tstr initialized initialized retained retained retained tpu tcr_0 initialized initialized retained retained retained tmdr_0 initialized initialized retained retained retained tior_0 initialized initialized retained retained retained tier_0 initialized initialized retained retained retained tsr_0 initialized initialized retained retained retained tcnt_0 initialized initialized retained retained retained tgra_0 initialized initialized retained retained retained tgrb_0 initialized initialized retained retained retained tgrc_0 initialized initialized retained retained retained tgrd_0 initialized initialized retained retained retained tcr_1 initialized initialized retained retained retained tmdr_1 initialized initialized retained retained retained tior_1 initialized initialized retained retained retained tier_1 initialized initialized retained retained retained tsr_1 initialized initialized retained retained retained tcnt_1 initialized initialized retained retained retained tgra_1 initialized initialized retained retained retained tgrb_1 initialized initialized retained retained retained tgrc_1 initialized initialized retained retained retained tgrd_1 initialized initialized retained retained retained tcr_2 initialized initialized retained retained retained tmdr_2 initialized initialized retained retained retained tior_2 initialized initialized retained retained retained tier_2 initialized initialized retained retained retained tsr_2 initialized initialized retained retained retained tcnt_2 initialized initialized retained retained retained tgra_2 initialized initialized retained retained retained tgrb_2 initialized initialized retained retained retained tgrc_2 initialized initialized retained retained retained tgrd_2 initialized initialized retained retained retained rev. 1.0, 11/02, page 618 of 690 register abbreviation power-on reset manual reset software standby module standby sleep module tcr_3 initialized initialized retained retained retained tpu tmdr_3 initialized initialized retained retained retained tior_3 initialized initialized retained retained retained tier_3 initialized initialized retained retained retained tsr_3 initialized initialized retained retained retained tcnt_3 initialized initialized retained retained retained tgra_3 initialized initialized retained retained retained tgrb_3 initialized initialized retained retained retained tgrc_3 initialized initialized retained retained retained tgrd_3 initialized initialized retained retained retained r64cnt operation continued operation continued operation continued retained operation continued rtc rseccnt operation continued operation continued operation continued retained operation continued rmincnt operation continued operation continued operation continued retained operation continued rhrcnt operation continued operation continued operation continued retained operation continued rwkcnt operation continued operation continued operation continued retained operation continued rdaycnt operation continued operation continued operation continued retained operation continued rmoncnt operation continued operation continued operation continued retained operation continued ryrcnt operation continued operation continued operation continued retained operation continued rsecar retained * 1 retained retained retained retained rminar retained * 1 retained retained retained retained rhrar retained * 1 retained retained retained retained rwkar retained * 1 retained retained retained retained rdayar retained * 1 retained retained retained retained rmonar retained * 1 retained retained retained retained rcr1 initialized * 2 initialized * 2 retained retained retained rcr2 initialized * 10 initialized * 10 retained retained retained ryrar retained retained retained retained retained rcr3 initialized retained retained retained retained rev. 1.0, 11/02, page 619 of 690 register abbreviation power-on reset manual reset software standby module standby sleep module scsmr_0 initialized initialized retained retained retained scif_0 scbrr_0 initialized initialized retained retained retained scscr_0 initialized initialized retained retained retained sctdsr_0 initialized initialized retained retained retained scfer_0 initialized initialized retained retained retained scssr_0 initialized initialized retained retained retained scfcr_0 initialized initialized retained retained retained scfdr_0 initialized initialized retained retained retained scftdr_0 undefined undefined retained retained retained scfrdr_0 undefined undefined retained retained retained scsmr_2 initialized initialized retained retained retained scif_2 scbrr_2 initialized initialized retained retained retained scscr_2 initialized initialized retained retained retained sctdsr_2 initialized initialized retained retained retained scfer_2 initialized initialized retained retained retained scssr_2 initialized initialized retained retained retained scfcr_2 initialized initialized retained retained retained scfdr_2 initialized initialized retained retained retained scftdr_2 undefined undefined retained retained retained scfrdr_2 undefined undefined retained retained retained scsmr_ir initialized initialized retained retained retained irda epdr0i undefined undefined retained retained retained usb epdr0o undefined undefined retained retained retained epdr0s undefined undefined retained retained retained epdr1 undefined undefined retained retained retained epdr2 undefined undefined retained retained retained epdr3 undefined undefined retained retained retained ifr0 initialized initialized retained retained retained ifr1 initialized initialized retained retained retained trg undefined undefined retained retained retained fclr undefined undefined retained retained retained epsz0o initialized initialized retained retained retained dasts initialized initialized retained retained retained rev. 1.0, 11/02, page 620 of 690 register abbreviation power-on reset manual reset software standby module standby sleep module epstl initialized initialized retained retained retained usb ier0 initialized initialized retained retained retained ier1 initialized initialized retained retained retained epsz1 initialized initialized retained retained retained dmar initialized initialized retained retained retained isr0 initialized initialized retained retained retained isr1 initialized initialized retained retained retained xvercr initialized initialized retained retained retained pacr initialized retained retained retained retained pfc pbcr initialized retained retained retained retained pccr initialized retained retained retained retained pdcr initialized retained retained retained retained pecr initialized retained retained retained retained pecr2 initialized retained retained retained retained pfcr initialized retained retained retained retained pfcr2 initialized retained retained retained retained pgcr initialized retained retained retained retained phcr initialized retained retained retained retained pjcr initialized retained retained retained retained pkcr initialized retained retained retained retained plcr initialized retained retained retained retained scpcr initialized retained retained retained retained pmcr initialized retained retained retained retained pncr initialized retained retained retained retained pncr2 initialized retained retained retained retained padr initialized retained retained retained retained port pbdr initialized retained retained retained retained pcdr initialized retained retained retained retained pddr initialized retained retained retained retained pedr initialized retained retained retained retained pfdr initialized retained retained retained retained pgdr initialized retained retained retained retained rev. 1.0, 11/02, page 621 of 690 register abbreviation power-on reset manual reset software standby module standby sleep module phdr initialized retained retained retained retained port pjdr initialized retained retained retained retained pkdr initialized retained retained retained retained pldr initialized retained retained retained retained scpdr initialized retained retained retained retained pmdr initialized retained retained retained retained pndr initialized retained retained retained retained addra initialized initialized initialized initialized retained adc addrb initialized initialized initialized initialized retained addrc initialized initialized initialized initialized retained addrd initialized initialized initialized initialized retained adcsr initialized initialized initialized initialized retained bdrb initialized retained retained retained retained ubc bdmrb initialized retained retained retained retained brcr initialized retained retained retained retained betr initialized retained retained retained retained barb initialized retained retained retained retained bamrb initialized retained retained retained retained bbrb initialized retained retained retained retained brsr initialized * 3 retained retained retained retained bara initialized retained retained retained retained bamra initialized retained retained retained retained bbra initialized retained retained retained retained brdr initialized * 3 retained retained retained retained basra undefined retained retained retained retained basrb undefined retained retained retained retained sdir retained retained retained retained retained h-udi sdid/sdidh * 4 ? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ? sdidl * 4 ? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ? notes: * 1 the enb bit is initialized. other bits are retained. * 2 the cf bit is undefined. * 3 although the flag is initialized, other bits are not initialized (except the reserved bits). * 4 values of these resisters are fixed. * 5 these registers are not initialized by a power-on reset caused by the wdt. rev. 1.0, 11/02, page 622 of 690 * 6 the sv bit is undefined. * 7 expevt[11:0] = h 000 at a power-on reset and expevt[11:0] = h 020 at a manual reset. * 8 the nmil bit = 1 when the nmi input is high, and the nmil bit = 0 when the nmi input is low. * 9 the endian bit indicates the md5 pin input sampled at a power-on reset. * 10 at a power-on reset, this register is initialized to h 09. at a manual reset, bits other than the rtcen and start bits are initialized. rev. 1.0, 11/02, page 623 of 690 section 25 electrical characteristics 25.1 absolute maximum ratings table 25.1 shows the absolute maximum ratings. table 25.1 absolute maximum ratings item symbol rating unit power supply voltage (i/o) v cc q v cc -rtc ?0.3 to 4.2 v power supply voltage (internal) v cc v cc -pll1 v cc -pll2 ?0.3 to 2.1 v input voltage (except port l) v in ?0.3 to v cc q + 0.3 v input voltage (port l) v in ?0.3 to av cc + 0.3 v analog power supply voltage (ad) av cc ?0.3 to 4.2 v analog input voltage (ad) v an ?0.3 to av cc + 0.3 v analog power supply voltage (usb) v cc -usb ?0.3 to 4.2 v analog input voltage (usb) v in ?0.3 to (v cc -usb) + 0.3 v operating temperature t opr ?20 to 75 c storage temperature t stg ?55 to 125 c caution: ? operating the chip in excess of the absolute maximum rating may result in permanent damage. ? order of turning on 1.5 v power (vcc, vcc-pll1, vcc-pll2) and 3.3 v power (vccq, vcc- rtc, avcc, vcc-usb): 1. the 3.3 v power and the 1.5 v power should be turned on simultaneously or the 3.3 v power should be tuned on first. when the 3.3 v is turned on first, turn on the 1.5 v power within 1 ms. it is recommended that this interval will be as short as possible. 2. until voltage is applied to all power supplies and a low level is input at the resetp pin, internal circuits remain unsettled, and so pin states are also undefined. the system design must ensure that these undefined states do not cause erroneous system operation. 3. when the power is turned on, make sure that the voltage of the 1.5 v power is lower than that of the 3.3 v power. rev. 1.0, 11/02, page 624 of 690 ? power-off order 1. in the reverse order of powering-on, first turn off the 1.5 v power, then turn off the 3.3 v power within 1 ms. it is recommended that this interval will be as short as possible. 2. pin states are undefined while only the 1.5 v power is off. the system design must ensure that these undefined states do not cause erroneous system operation. 3. when the power is turned off, make sure that the voltage of the 1.5 v power is lower than that of the 3.3 v power. waveforms and recommended times at power on/off are shown in figure 25.1. tpwu vccq: 3.3 v power vccq (min) voltage vccq (min) attain time vcc (min) attain time vcc: 1.5 v power vcc (min) voltage vcc/2 level voltage normal operation term states undefined term operation stopped clock oscillation started oscillation settling time cancel the power-on reset and go to normal operation tunc gnd tpwd figure 25.1 power on/off sequence recommended power on/off times item symbol max. permitted value unit vccq to vcc power-on time interval tpwu 1 ms vccq to vcc power-off time interval tpwd 1 ms state undefined term tunc 10 ms the recommended times shown above do not require strict settings. the state undefined term indicates that pins are at the power rising stage. the pin state is stabilized at vccq (min) attain time. however, a power-on reset ( resetp ) is accepted successfully only after vccq (min) attain time and clock oscillation settling time. set the state undefined term less than 10 ms. rev. 1.0, 11/02, page 625 of 690 25.2 dc characteristics tables 25.2 and 25.3 list dc characteristics. table 25.2 dc characteristics (1) [common items] (condition: ta = ?20 to 75c) item symbol min typ max unit measurement conditions v cc q, v cc -rtc 3.0 3.3 3.6 v power supply voltage v cc , v cc -pll1 v cc -pll2 1.4 1.5 1.6 ? 133 200 v cc = 1.5 v i = 133 mhz i cc ? 105 150 v cc = 1.5 v i = 100 mhz normal operation i cc q ? 20 40 ma v cc q = 3.3 v b = 33 mhz i cc ?2540ma in sleep mode * i cc q ? 10 20 b = 33 mhz i cc ? 150 500 a i cc q ? 10 30 t a = 25c (rtc on) v cc q = 3.3 v v cc = 1.5 v i cc ? 150 500 a current consumption in standby mode i cc q ? 10 30 t a = 25c (rtc off) v cc q = 3.3 v v cc = 1.5 v input leak current all input pins | i in | ? ? 1.0 av in = 0.5 to v cc q ? 0.5 v three-state leak current i/o, all output pins (off condition) | i tsi | ? ? 1.0 a vin = 0.5 to v cc q ? 0.5 v pull-up resistance port pin r pull 30 60 120 k ? rev. 1.0, 11/02, page 626 of 690 item symbol min typ max unit measurement conditions pin capacitance all pins other than the usb transceiver pins (d+, d-) and ptm3 to ptm0 c??10pf usb transceiver pins (d+, d?) and ptm3 to ptm0 c an ? ? 20 pf analog power-supply voltage (ad) av cc 3.0 3.3 3.6 v analog power-supply voltage (usb) v cc -usb 3.0 3.3 3.6 v analog power-supply current (ad) during a/d conversion ai cc ?0.82 ma idle ? 0.01 5.0 a note: * no external bus cycles except refresh cycles. rev. 1.0, 11/02, page 627 of 690 table 25.2 dc characteristics (2-a) [excluding usb-related pins] (condition: ta = ?20 to 75c) item symbol min typ max unit measurement conditions input high voltage resetp , resetm , nmi irq5 to irq0, pint15 to pint0, rxd0, md6 to md0, asemd0 , trst , extal, ckio, ca v ih v cc q 0.9 ? v cc q + 0.3 extal2 ? ? ? when this pin is not connected to the crystal resonator, this pin should be connected to the v cc q pin (pulled up). port l 2.0 ? av cc + 0.3 other input pins 2.0 ? v cc q + 0.3 v input low voltage resetp , resetm , nmi irq5 to irq0, pint15 to pint0, rxd0, md6 to md0, asemd0 , trst , extal, ckio, ca v il ?0.3 ? v cc q 0.1 extal2 ? ? ? when this pin is not connected to the crystal resonator, this pin should be connected to the v cc q pin (pulled up). port l ?0.3 ? av cc 0.2 v rev. 1.0, 11/02, page 628 of 690 item symbol min typ max unit measurement conditions input low voltage other input pins v il ?0.3 ? v cc q 0.2 v output high voltage all output pins v oh 2.4 ? ? v cc q = 3.0 v, i oh = ?200 a 2.0 ? ? v v cc q = 3.0 v, i oh = ?2 ma output low voltage all output pins v ol ? ? 0.55 v v cc q = 3.6 v, i ol = 1.6 ma notes: 1. even when the rtc is not used, power must be supplied between v cc -rtc and v ss - rtc. 2. av cc must satisfy the condition: v cc q ? 0.2 v av cc v cc q + 0.2 v. do not leave the av cc and av ss pins open if the a/d converter is not used; connect av cc to v cc q, and av ss to v ss q. 3. current consumption values are for v ih min = v cc q ? 0.5 v and v il max = 0.5 v with all output pins unloaded. table 25.2 dc characteristics (2-b) [usb-related pins*] (condition: ta = ?20 to 75c) item symbol min typ max unit measurement conditions power supply voltage v cc q 3.0 3.3 3.6 v input high voltage v ih 2.0 ? v cc q + 0.3 v input low voltage v il ?0.3 ? v cc q 0.2 v input high voltage (extal_usb) v ih (extal_usb) v cc q ? 0.3 ? v cc q + 0.3 v input low voltage (extal_usb) v il (extal_usb) ?0.3 ? v cc q 0.2 v output high voltage v oh 2.4 ? ? v v cc q = 3.0 v, i oh = ?200 a 2.0 ? ? v cc q = 3.0 v, i oh = ?2 ma output low voltage v ol ? ? 0.55 v v cc q = 3.6 v, i ol = 1.6 ma note: * xvdata, dpls, dmns, txdpls, txdmns, txenl, vbus, suspnd, and extal_usb pins rev. 1.0, 11/02, page 629 of 690 table 25.2 dc characteristics (2-c) [usb transceiver-related pins* 1 ] (condition: ta = ?20 to 75c) item symbol min typ max unit measurement conditions power supply voltage * 2 v cc -usb 3.0 3.3 3.6 v differential input sensitivity v di 0.2 ? ? v ? (dp)?(dm) ? differential common mode range v cm 0.8 ? 2.5 v single ended receiver threshold voltage v se 0.8 ? 2.0 v output high voltage v oh 2.8 ? v cc -usb v output low voltage v ol ??0.3 v tri-state leak current i lo ?10 ? 10 a0v rev. 1.0, 11/02, page 631 of 690 25.3.1 clock timing table 25.5 clock timing (condition: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c, maximum external bus operating frequency: 66.67 mhz) item symbol min max unit figure extal clock input frequency f ex 10 66.67 mhz 25.2 extal clock input cycle time t excyc 15 100 ns extal clock input low pulse width t exl 1.5 ? ns extal clock input high pulse width t exh 1.5 ? ns extal clock input rise time t exr ?6ns extal clock input fall time t exf ?6ns ckio clock input frequency f cki 20 66.67 mhz 25.3 ckio clock input cycle time t ckicyc 15 50 ns ckio clock input low pulse width t ckil 3?ns ckio clock input high pulse width t ckih 3?ns ckio clock input rise time t ckir ?4ns ckio clock input fall time t ckif ?4ns ckio clock output frequency t op 20 66.67 mhz 25.4 ckio clock output cycle time t cyc 15 50 ns ckio clock output low pulse width t ckol 3?ns ckio clock output high pulse width t ckoh 3?ns ckio clock output rise time t ckor ?5ns ckio clock output fall time t ckof ?5ns power-on oscillation settling time t osc1 10 ? ms 25.5 resetp setup time t resps 20 ? ns 25.5 resetp assert time t respw 20 ? t cyc 25.5, 25.6 resetm assert time t resmw 20 ? t cyc 25.6 standby return oscillation settling time 1 t osc2 10 ? ms 25.6 standby return oscillation settling time 2 t osc3 10 ? ms 25.7 standby return oscillation settling time 3 t osc4 11 ? ms 25.8 rev. 1.0, 11/02, page 632 of 690 item symbol min max unit figure pll synchronization settling time 1 t pll1 100 ? s 25.9, 25.10 pll synchronization settling time 2 t pll2 100 ? s 25.11 interrupt determination time (rtc used and standby mode) t irlstb 100 ? s 25.10 t exh t exf t exr t exl t excyc v ih v ih v ih 1/2 v cc q 1/2 v cc q v il v il extal * (input) note: * the clock input from the extal pin. figure 25.2 extal clock input timing t ckih t ckif t ckir t ckil t ckicyc v ih 1/2 v cc q 1/2 v cc q v ih v il v ih v il ckio (input) figure 25.3 ckio clock input timing t ckoh t ckof t ckor t ckol t cyc v oh 1/2 v cc q 1/2 v cc q v oh v oh v ol v ol ckio (output) figure 25.4 ckio clock output timing rev. 1.0, 11/02, page 633 of 690 v cc min t respw t resps t osc1 v cc ckio, internal clock stable oscillation note: oscillation settling time when built-in oscillator is used figure 25.5 power-on oscillation settling time ckio, internal clock stable oscillation standby t osc2 t respw t resmw note: oscillation settling time when built-in oscillator is used figure 25.6 oscillation settling time at standby return (return by reset) ckio, internal clock stable oscillation standby t osc3 nmi note: oscillation settling time when built-in oscillator is used figure 25.7 oscillation settling time at standby return (return by nmi) rev. 1.0, 11/02, page 634 of 690 ckio, internal clock stable oscillation standby t osc4 to irq5 to irq0 pint15 to pint0 note: oscillation settling time when built-in oscillator is used in oscillation stop mode figure 25.8 oscillation settling time at standby return (return by irq5 to irq0, pint15 to pint0, and irl3 irl3 irl3 irl3 to irl0 irl0 irl0 irl0 ) extal input, ckio input stable input clock reset or nmi interrupt request stable input clock normal normal standby pll output, ckio output internal clock status 0 status 1 pll synchronization note: pll oscillation settling time when clock is input from extal pin t pll1 pll synchronization figure 25.9 pll synchronization settling time by reset or nmi rev. 1.0, 11/02, page 635 of 690 extal input or ckio input stable input clock pint15 to pint0, irq5 to irq0/ to interrupt request stable input clock normal normal pll output, ckio output internal clock status 0 status 1 note: pll oscillation settling time when clock is input from extal pin or ckio pin in oscillation continuous mode. t pll1 pll synchronization standby pll synchronization t irlstb figure 25.10 pll synchronization settling time by irq/irl, pint interrupts extal input * 1 (ckio input) ckio output * 2 (pll output) internal clock multiplication ratio modified t pll2 notes: * 1 ckio input in clock mode 7 * 2 pll output except in clock mode 7 figure 25.11 pll synchronization settling time when frequency multiplication ratio modified rev. 1.0, 11/02, page 636 of 690 25.3.2 control signal timing table 25.6 control signal timing (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c) 66.67 mhz * 2 item symbol min max unit figure resetp pulse width t respw 20 * 3 ?t cyc 25.12 resetp setup time * 1 t resps 20 ? ns resetm pulse width t resmw 20 * 4 ?t cyc resetm setup time t resms 10 ? ns breq setup time t breqs 1/2 t cyc +10 ? ns 25.14 breq hold time t breqh 1/2 t cyc +3 ? ns nmi setup time * 1 t nmis 10 ? ns 25.13 nmi hold time t nmih 3?ns irq5 to irq0 setup time * 1 t irqs 10 ? ns irq5 to irq0 hold time t irqh 3?ns back delay time t backd ? 1/2 t cyc +13 ns 25.14 status1, status0 delay time t std ? 18 ns 25.15 bus tri-state delay time 1 t boff1 0 30 ns 25.14, bus tri-state delay time 2 t boff2 0 30 ns 25.15 bus buffer-on time 1 t bon1 030ns bus buffer-on time 2 t bon2 030ns notes: t cyc is the external bus clock cycle (b clock cycle). * 1 resetp , nmi, and irq5 to irq0 are asynchronous. changes are detected at the clock rise when the setup shown is kept. when the setup cannot be kept, detection can be delayed until the next clock rises. * 2 the upper limit of the external bus clock is 66.67 mhz. * 3 in standby mode, t respw = t osc2 (10 ms). when the crystal oscillation continues or the clock multiplication ratio is changed in standby mode, t respw = t pll1 (100 s). * 4 in standby mode, t resmw = t osc2 (10 ms). when the crystal oscillation continues or the clock multiplication ratio is changed in standby mode, resetm must be kept low until status (0-1) changes to reset (hh). rev. 1.0, 11/02, page 637 of 690 ckio t resps t resms t resps t resms t respw t resmw figure 25.12 reset input timing ckio nmi t nmih t nmis v ih v il irq5 to irq0 t irqh t irqs v ih v il figure 25.13 interrupt signal input timing ckio a25 to a0, d31 to d0 , rd/ , , , , , , cke breqh t breqs t backd t backd t breqh t breqs t bon1 t boff1 t boff2 t bon2 t figure 25.14 bus release timing rev. 1.0, 11/02, page 638 of 690 ckio t std t boff2 t boff1 t std t bon2 t bon1 status 0 status 1 a25 to a0, d31 to d0 , rd/ , , , , , , cke normal mode normal mode standby mode figure 25.15 pin drive timing at standby 25.3.3 ac bus timing table 25.7 bus timing (1) (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c, clock mode 0/1/2/4/5/6/7) 66.67 mhz item symbol min max unit figure address delay time 1 t ad1 1 12 ns 25.16 to 25.38 address delay time 2 t ad2 ? 1/2 t cyc +12 ns 25.21 address setup time t as 0 ? ns 25.16 to 25.19 address hold time t ah 0 ? ns 25.16 to 25.19 bs delay time t bsd ? 10 ns 25.16 to 25.35 cs delay time 1 t csd1 1 10 ns 25.16 to 25.38 read/write delay time 1 t rwd1 1 10 ns 25.16 to 25.38 read strobe delay time t rsd ? 1/2 t cyc +10 ns 25.16 to 25.21 read data setup time 1 t rds1 1/2 t cyc +6 ? ns 25.16 to 25.20 read data setup time 2 t rds2 6 ? ns 25.22 to 25.25, 25.30 to 25.32 read data setup time 3 t rds3 1/2 t cyc +6 ? ns 25.21 read data hold time 1 t rdh1 0 ? ns 25.16 to 25.20 read data hold time 2 t rdh2 2 ? ns 25.22 to 25.25, 25.30 to 25.32 read data hold time 3 t rdh3 0 ? ns 25.21 rev. 1.0, 11/02, page 639 of 690 66.67 mhz item symbol min max unit figure write enable delay time t wed ? 1/2 t cyc +10 ns 25.16 to 25.21 write data delay time 1 t wdd1 ? 12 ns 25.16 to 25.20 write data delay time 2 t wdd2 ? 12 ns 25.26 to 25.29, 25.33 to 25.35 write data hold time 1 t wdh1 1 ? ns 25.16 to 25.20 write data hold time 2 t wdh2 1 ? ns 25.26 to 25.29, 25.33 to 25.35 write data hold time 4 t wdh4 0 ? ns 25.16 to 25.19 wait setup time t wts 1/2 t cyc +6 ? ns 25.17 to 25.21 wait hold time t wth 1/2 t cyc +2 ? ns 25.17 to 25.21 ras delay time 1 t rasd1 1 10 ns 25.22 to 25.38 cas delay time 1 t casd1 1 10 ns 25.22 to 25.38 dqm delay time 1 t dqmd1 1 10 ns 25.22 to 25.35 cke delay time 1 t cked1 1 10 ns 25.37 ah delay time t ahd 1/2 t cyc 1/2 t cyc +10 ns 25.20 multiplex address delay time t mad ? 12 ns 25.20 multiplex address hold time t mah 0 ? ns 25.20 dack delay time t dacd ? 10 ns 25.16 to 25.35 rev. 1.0, 11/02, page 640 of 690 25.3.4 basic timing t1 t ad1 t ad1 t as t csd1 t csd1 t2 t rwd1 t rwd1 t rsd t rsd t ah t ah t rdh1 t rds1 t wed t wed t bsd t bsd t dacd t dacd t wdh1 t wdh4 t wdd1 ckio a25 to a0 rd/ d31 to d0 dackn * d31 to d0 read write note: * dackn is a waveform when active-low is specified. figure 25.16 basic bus cycle (no wait) rev. 1.0, 11/02, page 641 of 690 t1 t ad1 t ad1 t as t csd1 t csd1 tw t2 t rwd1 t rwd1 t rsd t rsd t rdh1 t rds1 t wed t wed t ah t ah t bsd t bsd t wth t wts t dacd t dacd t wdh1 t wdh4 t wdd1 ckio a25 to a0 rd/ d31 to d0 dackn * d31 to d0 note: * dackn is a waveform when active-low is specified. read write figure 25.17 basic bus cycle (one software wait) rev. 1.0, 11/02, page 642 of 690 t1 t ad1 t ad1 t as t csd1 t csd1 tw x t2 t rwd1 t rwd1 t rsd t rsd t ah t ah t rdh1 t rds1 t wed t wed t bsd t bsd t wth t wth t wts t wts t dacd t dacd t wdh1 t wdh4 t wdd1 ckio a25 to a0 rd/ d31 to d0 dackn * d31 to d0 read write note: * dackn is a waveform when active-low is specified. figure 25.18 basic bus cycle (one external wait) rev. 1.0, 11/02, page 643 of 690 t ad1 t ad1 t1 t rwd1 t rsd t wed t wed t wed t rds1 t rds1 t rdh1 t rdh1 t as t rsd t rsd t ah t rsd t ah t wed t ah t ah t csd1 t wdd1 t wdh1 t wdh4 t wdh1 t wdh4 t wdd1 t bsd t bsd t dacd t dacd t dacd t dacd t bsd t bsd t rwd1 t rwd1 t rwd1 t csd1 t csd1 t csd1 t as t ad1 t ad1 tw t2 tnop t1 tw t2 tnop dackn * a25 to a0 d15 to d0 rd/ d15 to d0 n ckio t wth t wts t wth t wts read write note: * dackn is a waveform when active-low is specified. figure 25.19 basic bus cycle (one software wait, external wait enabled (wm bit = 0), no idle cycle setting) rev. 1.0, 11/02, page 644 of 690 t wdd1 ta 1 ta 2 ta 3 t1 tw tw t2 t ad1 t csd1 t ad1 t rwd1 t rwd1 t csd1 t rsd t rsd t rdh1 t rds1 t wed t wed data data t bsd t bsd t wth t wts t ahd t ahd t wth t wts t dacd t dacd address t wdh1 t mah t mad ckio a25 to a0 rd/ d15 to d0 dackn * d15 to d0 address t mah t mad read write note: * dackn is a waveform when active-low is specified. figure 25.20 address/data multiplex i/o bus cycle (three address cycles, one software wait, one external wait) rev. 1.0, 11/02, page 645 of 690 25.3.5 burst rom timing t1 tw twx t2b twb t2b t ad1 t csd1 t ad2 t ad2 t rwd1 t rwd1 t csd1 t rsd t rsd t wed t wed t bsd t bsd t wth t wts t wth t wts t dacd t dacd t rds3 t rdh3 t rds3 t rdh3 ckio a25 to a0 rd/ dackn d31 to d0 notes: 1. t rdh3 is specified by earlier one of change of a25 to a0 or the rising edge. 2. dackn is a waveform when active-low is specified. figure 25.21 burst rom read cycle (one access wait, one external wait, one burst wait, two bursts) rev. 1.0, 11/02, page 646 of 690 25.3.6 synchronous dram timing tc1 tr tcw td1 tde t ad1 t ad1 t csd1 t ad1 t rwd1 t rwd1 t csd1 t ad1 t ad1 t ad1 t rdh2 t rds2 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rasd1 row address read a command column address t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.22 synchronous dram single read bus cycle (auto precharge, cas latency = = = = 2, trcd = = = = 1 cycle, trp = = = = 1 cycle) rev. 1.0, 11/02, page 647 of 690 tr w tr tc1 tcw td1 tde tap t ad1 t ad1 t csd1 t ad1 t rwd1 t rwd1 t csd1 t ad1 t ad1 t ad1 t rdh2 t rds2 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rasd1 row address read a command column address t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.23 synchronous dram single read bus cycle (auto precharge, cas latency = = = = 2, trcd = = = = 2 cycle, trp = = = = 2 cycle) rev. 1.0, 11/02, page 648 of 690 tc1 tc2 td1 td2 td3 td4 tr tc3 tc4 tde t ad1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t csd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rasd1 row address read a command read command column address (1 to 4) t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t rdh2 t rds2 t rdh2 t rds2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.24 synchronous dram burst read bus cycle (single read 4), (auto precharge, cas latency = = = = 2, trcd = = = = 1 cycle, trp = = = = 2 cycle) rev. 1.0, 11/02, page 649 of 690 tc1 tc2 td1 td2 td3 td4 tr trw tc3 tc4 tde t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rasd1 row address read a command read command column address (1 to 4) t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t rdh2 t rds2 t rdh2 t rds2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.25 synchronous dram burst read bus cycle (single read 4), (auto precharge, cas latency = = = = 2, trcd = = = = 2 cycle, trp = = = = 1 cycle) rev. 1.0, 11/02, page 650 of 690 tr w l tr t c 1 t csd1 t csd1 t rwd1 t rwd1 t rwd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rasd1 row address write a command column address t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdd2 t wdh2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.26 synchronous dram single write bus cycle (auto precharge, trwl = 2 cycle) rev. 1.0, 11/02, page 651 of 690 trw tc1 trwl tr tr w t csd1 t csd1 t casd1 t casd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 row address write a command column address t bsd t bsd (high) cke t dqmd1 t rwd1 t rwd1 t rasd1 t rasd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdd2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.27 synchronous dram single write bus cycle (auto precharge, trcd = = = = 3 cycle, trwl = 2 cycle) rev. 1.0, 11/02, page 652 of 690 tc2 tc3 tc4 trwl tr tc1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rasd1 row address write a command write command column address (1-4) t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdh2 t wdd2 t wdd2 t rasd1 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.28 synchronous dram burst write bus cycle (single write 4), (auto precharge, trcd = = = = 1 cycle, trwl = 2 cycle) rev. 1.0, 11/02, page 653 of 690 tc2 tc3 tc4 trwl tr tc1 tr w t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rasd1 row address write a command write command column address (1-4) t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdh2 t wdd2 t wdd2 t rasd1 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.29 synchronous dram burst write bus cycle (single write 4), (auto precharge, trcd = = = = 2 cycle, trwl = 2 cycle) rev. 1.0, 11/02, page 654 of 690 tc3 tc4 tde tr tc2 td1 td2 td3 td4 tc1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rasd1 row address read command column address (1-4) t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t rdh2 t rds2 t rdh2 t rds2 t ad1 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.30 synchronous dram burst read bus cycle (single read 4) (bank active mode: actv + read commands, cas latency = 2, trcd = 1 cycle) rev. 1.0, 11/02, page 655 of 690 tc2 tc4 tde tc1 tc3 td1 td2 td3 td4 t csd1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rasd1 read command column address (1-4) t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t rdh2 t rds2 t rdh2 t rds2 t ad1 t dqmd1 t dacd t bsd t casd1 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.31 synchronous dram burst read bus cycle (single read 4) (bank active mode: read command, same row address, cas latency = 2, trcd = 1 cycle) rev. 1.0, 11/02, page 656 of 690 tc3 tc4 tde tc2 td1 td2 td3 td4 tc1 tr tpw tp t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rasd1 t rasd1 t rasd1 read command column address row address (1-4) t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t rdh2 t rds2 t rdh2 t rds2 t csd1 t rasd1 t casd1 t dqmd1 t bsd t dacd notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.32 synchronous dram burst read bus cycle (single read 4) (bank active mode: pre + actv + read commands, different row address, cas latency = 2, trcd = 1 cycle) rev. 1.0, 11/02, page 657 of 690 tc2 tc3 tc4 tr tc1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd1 t rwd1 t rwd1 t rasd1 row address write command column address (1-4) t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdh2 t wdd2 t wdd2 t rasd1 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.33 synchronous dram burst write bus cycle (single write 4) (bank active mode: actv + write commands, trcd = 1 cycle, trwl = 1 cycle) rev. 1.0, 11/02, page 658 of 690 tc2 tc3 tc4 tnop tc1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 write command column address (1-4) t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdh2 t wdd2 t wdd2 t rasd1 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.34 synchronous dram burst write bus cycle (single write 4) (bank active mode: write command, same row address, trcd = 1 cycle, trwl = 1 cycle) rev. 1.0, 11/02, page 659 of 690 tc2 tc3 tc4 tr tpw tp tc1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 t rwd1 t rasd1 t rasd1 t rasd1 t rasd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 write command row address (1-4) column address t casd1 t casd1 t bsd t bsd (high) cke t dqmd1 t dqmd1 dqmxx t dacd t dacd dackn * 2 t wdh2 t wdd2 t wdh2 t wdd2 t rasd1 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.35 synchronous dram burst write bus cycle (single write 4) (bank active mode: pre + actv + write commands, different row address, trcd = 1 cycle, trwl = 1 cycle) rev. 1.0, 11/02, page 660 of 690 tr c tr c tr r tpw tp trc t csd1 t csd1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 t rasd1 t rasd1 t rasd1 t rasd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t casd1 t casd1 (high) (hi-z) cke dqmxx dackn * 2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.36 synchronous dram auto-refresh timing (trp = 2 cycle) rev. 1.0, 11/02, page 661 of 690 tr c tr c tr c tr c tr r tpw tp trc t csd1 t csd1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t rwd1 t rwd1 t rwd1 t rasd1 t rasd1 t rasd1 t rasd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t casd1 t casd1 (hi-z) cke dqmxx dackn * 2 t cked1 t cked1 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.37 synchronous dram self-refresh timing (trp = 2 cycle) rev. 1.0, 11/02, page 662 of 690 trc trc trc tmw tde tr r tr r tpw tp trc t csd1 t csd1 t csd1 t csd1 t csd1 t csd1 t csd1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 pall ref ref mrs t rwd1 t rwd1 t rwd1 t rwd1 t rwd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t casd1 t casd1 t casd1 t casd1 t casd1 t casd1 (hi-z) cke dqmxx dackn * 2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.38 synchronous dram mode register write timing (trp = 2 cycle) rev. 1.0, 11/02, page 663 of 690 table 25.8 bus timing (2) (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c, clock mode 0/1/2/4/5/6/7) item symbol min max unit figure address delay time 3 t ad3 1/2 t cyc 1/2 t cyc +12 ns 25.39 to 25.42 cs delay time 2 t csd2 1/2 t cyc 1/2 t cyc +10 ns 25.39 to 25.42 read/write delay time 2 t rwd2 1/2 t cyc 1/2 t cyc +10 ns 25.39 to 25.42 read data setup time 4 t rds4 1/2 t cyc +6 ? ns 25.39 read data hold time 4 t rdh4 0 ? ns 25.39 write data delay time 3 t wdd3 ? 1/2 t cyc +12 ns 25.39 write data hold time 3 t wdh3 1/2 t cyc ? ns 25.39 ras delay time 2 t rasd2 1/2 t cyc 1/2 t cyc +10 ns 25.39 to 25.42 cas delay time 2 t casd2 1/2 t cyc 1/2 t cyc +10 ns 25.39 to 25.42 dqm delay time 2 t dqmd2 1/2 t cyc 1/2 t cyc +10 ns 25.39 cke delay time 2 t cked2 1/2 t cyc 1/2 t cyc +10 ns 25.41 rev. 1.0, 11/02, page 664 of 690 tr td1 tde tap trwl tap tnop tc1 tr tc1 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t ad3 t csd2 t csd2 t csd2 t csd2 t rwd2 t rwd2 t rwd2 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t rasd2 t rasd2 t rasd2 t rasd2 t casd2 t casd2 t casd2 t casd2 t bsd t bsd t bsd t rds4 t rdh4 t bsd cke t dqmd2 t dqmd2 t dqmd2 t dqmd2 dqmxx t dacd t dacd t dacd t dacd dackn * 2 t wdh3 t wdd3 tw (high) notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.39 access timing in low-frequency mode (auto precharge) rev. 1.0, 11/02, page 665 of 690 tr c tr c tr r tpw tp trc t csd2 t csd2 t csd2 t csd2 t ad3 t ad3 t ad3 t ad3 t rwd2 t rwd2 t rwd2 t rasd2 t rasd2 t rasd2 t rasd2 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t casd2 t casd2 (high) (hi-z) cke dqmxx dackn * 2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.40 synchronous dram auto-refresh timing (trp = 2 cycle, low-frequency mode) rev. 1.0, 11/02, page 666 of 690 tr c tr c tr c tr c tr r tpw tp trc t csd2 t csd2 t csd2 t csd2 t ad3 t ad3 t ad3 t ad3 t rwd2 t rwd2 t rwd2 t rasd2 t rasd2 t rasd2 t rasd2 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t casd2 t casd2 (hi-z) cke dqmxx dackn * 2 t cked2 t cked2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.41 synchronous dram self-refresh timing (trp = 2 cycle, low-frequency mode) rev. 1.0, 11/02, page 667 of 690 trc trc trc tmw tde tr r tr r tpw tp trc t csd2 t csd2 t csd2 t csd2 t csd2 t csd2 t csd2 t csd2 t ad3 t ad3 t ad3 t ad3 t ad3 pall ref ref mrs t rwd2 t rwd2 t rwd2 t rwd2 t rwd2 t rasd2 t rasd2 t rasd2 t rasd2 t rasd2 t rasd2 t rasd2 t rasd2 ckio a25 to a0 rd/ a12/a11 * 1 d31 to d0 t casd2 t casd2 t casd2 t casd2 t casd2 t casd2 (hi-z) cke dqmxx dackn * 2 notes: * 1 address pin to be connected to a10 of sdram. * 2 dackn is a waveform when active-low is specified. figure 25.42 synchronous dram mode register write timing (trp = 2 cycle, low-frequency mode) rev. 1.0, 11/02, page 668 of 690 25.3.7 dmac signal timing table 25.9 dmac signal timing (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c) module item symbol min max unit figure dmac dreq setup time t drqs 10 ? ns 25.43 dreq hold time t drqh 3? dack, tend delay time t dacd ? 10 25.44 t drqs t drqh ckio dreqn figure 25.43 dreq input timing ckio tend0 dackn t dacd t dacd figure 25.44 dack, tend output timing rev. 1.0, 11/02, page 669 of 690 25.3.8 tmu signal timing table 25.10 tmu signal timing (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c) module item symbol min max unit figure b:p clock ratio = 1:1 15 ? b:p clock ratio = 2:1 t cyc +15 ? tmu timer input setup time b:p clock ratio = 4:1 t tclks 3 t cyc +15 ? ns 25.45 timer clock input setup time t tcks 15 ? 25.46 timer clock pulse width edge specification t tckwh/l 2.0 ? t pcyc * both edge specification t tckwh/l 3.0 ? note: * t pcyc indicates a peripheral clock (p ) cycle. t tclks ckio tclk (input) figure 25.45 tclk input timing t tcks t tcks t tckwh t tckwl ckio tclk (input) figure 25.46 tclk clock input timing rev. 1.0, 11/02, page 670 of 690 25.3.9 rtc signal timing table 25.11 rtc signal timing (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c) module item symbol min max unit figure rtc oscillation settling time t rosc 3 ? s 25.47 v cc v ccmin t rosc rtc crystal oscillator stable oscillation figure 25.47 oscillation settling time when rtc crystal oscillator is turned on 25.3.10 16-bit timer pulse unit (tpu) signal timing table 25.12 16-bit timer pulse unit (tpu) signal timing (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c) item symbol min max unit figure timer output delay time t tod ? 15 ns 25.48 ckio to0, to1 t tod to2, to3 figure 25.48 tpu output timing rev. 1.0, 11/02, page 671 of 690 25.3.11 scif module signal timing table 25.13 scif module signal timing (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c) module item symbol min max unit figure clock synchronization 12 ? scif0, scif2 input clock cycle asynchroniza- tion t scyc 4? t pcyc 25.49 25.50 input clock rise time t sckr ? 1.5 25.49 input clock fall time t sckf ?1.5 input clock pulse width t sckw 0.4 0.6 t scyc transmission data delay time t txd ?3 t pcyc * + 50 ns 25.50 receive data setup time (clock synchronization) t rxs 2 t pcyc * ? receive data hold time (clock synchronization) t rxh 2 t pcyc * ? rts delay time t rtsd ? 100 cts setup time (clock synchronization) t ctss 100 ? cts hold time (clock synchronization) t ctsh 100 ? note: * t pcyc indicates a peripheral clock (p ) cycle. t sckw t sckr t sckf t scyc sck figure 25.49 sck input clock timing rev. 1.0, 11/02, page 672 of 690 t scyc t txd t rxh t rxs t rtsd t ctsh t ctss sck txd (data trans- mission) rxd (data reception) figure 25.50 scif input/output timing in clock synchronous mode 25.3.12 usb module signal timing table 25.14 usb module clock timing (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c) item symbol min max unit figure frequency (48 mhz) * t freq 47.9 48.1 mhz 25.51 clock rise time * t r48 ?4 ns clock fall time * t f48 ?4 ns duty (t high /t low ) * t duty 90 110 % oscillation settling time t uosc 10 ? ms 25.52 note: * when the usb is operated by supplying a clock to the extal_usb pin from off-chip, the supplied clock must satisfy the above clock specifications. t high t low t freq 10% t r48 t f48 90% extal_usb figure 25.51 usb clock timing rev. 1.0, 11/02, page 673 of 690 v cc v ccmin t uosc usb crystal oscillator state oscillation figure 25.52 oscillation settling time when usb crystal oscillator is turned on 25.3.13 usb transceiver timing table 25.15 usb transceiver timing (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av s = 0 v, t a = ?20 to 75c) item symbol min typ max unit measurement condition rising time t r 4 ? 20 ns c l = 50pf falling time t f 4 ? 20 ns c l = 50pf rising/falling time ratio t r / t f 90 ? 110 % output signal crossover voltage v crs 1.3 ? 2.0 v c l = 50pf note: this transceiver complies with the full-speed specifications. t r , t f 90% 10% crossover voltage dp dm measured element vcc-usb dp dm vcc v ss rs = 33 ? r l = 15k ? r l = 15k ? c l c l r l = 1.5k ? rs = 33 ? 1. t r and t f are judged by the time taken for the transitions between 10% and 90% amplitude. 2. the electrostatic capacitance, c l , includes the floating capacitance of the wiring connection and the input capacitance of the probe. measurement circuit rev. 1.0, 11/02, page 674 of 690 25.3.14 port input/output timing table 25.16 port input/output timing (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c) module item symbol min max unit figure output data delay time t portd ?17 b:p clock ratio = 1:1 15 ? b:p clock ratio = 2:1 t cyc +15 ? input data setup time b:p clock ratio = 4:1 t ports 3 t cyc +15 ? port input data hold time t porth 8? ns 25.53 t ports ckio t porth t portd port 7 to 0 (read) port 7 to 0 (write) figure 25.53 i/o port timing rev. 1.0, 11/02, page 675 of 690 25.3.15 h-udi related pin timing table 25.17 h-udi related pin timing (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c) item symbol min max unit figure tck cycle time t tckcyc 50 ? ns 25.54, 25.56 tck high-pulse width t tckh 12 ? ns 25.54 tck low-pulse width t tckl 12 ? ns tck rise/fall time t tckf ?4ns trst setup time t trsts 12 ? ns 25.55 trst hold time t trsth 50 ? t cyc tdi setup time t tdis 10 ? ns 25.56 tdi hold time t tdih 10 ? ns tms setup time t tmss 10 ? ns tms hold time t tmsh 10 ? ns tdo delay time t tdod ?15ns asemd0 setup time t asemd0s 12 ? ns 25.57 asemd0 hold time t asemd0h 12 ? ns t tckh t tckf t tckf t tckl t tckcyc v ih v ih v ih 1/2 v cc q 1/2 v cc q v il v il figure 25.54 tck input timing rev. 1.0, 11/02, page 676 of 690 t trsts t trsth figure 25.55 trst trst trst trst input timing (reset hold) t tmss t tmsh t tdod t tckcyc t tdih t tdis tck tdi tms tdo figure 25.56 h-udi data transfer timing t asemd0h t asemd0s figure 25.57 asemd0 asemd0 asemd0 asemd0 input timing rev. 1.0, 11/02, page 677 of 690 25.3.16 ac characteristics measurement conditions ? i/o signal reference level: v cc q/2 (v cc q = 3.0 to 3.6 v, v cc = 1.4 to 1.6 v) ? input pulse level: v ss q to 3.0 v (where resetp , resetm , asemd0 , nmi, irq5 to irq0, ckio, and md6 to md0 are within v ss q to v cc q) ? input rise and fall times: 1 ns i ol i oh c l v ref lsi output pin reference voltage notes: c l is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30 pf: ckio, , , , to , 50 pf: all other pins i ol =1.6 ma, i oh = ?200a 1. 2. v figure 25.58 output load circuit rev. 1.0, 11/02, page 678 of 690 25.4 a/d converter characteristics table 25.18 lists the a/d converter characteristics. table 25.18 a/d converter characteristics (conditions: v cc q = v cc -rtc = v cc -usb = 3.0 to 3.6 v, v cc = v cc -pll1 = v cc -pll2 = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, v ss q = v ss = v ss -rtc = v ss -usb = v ss -pll1 = v ss -pll2 = av ss = 0 v, t a = ?20 to 75c) item min typ max unit resolution 10 10 10 bits conversion time 8.5 ? ? s analog input capacitance ? ? 20 pf permissible signal-source impedance (single-source) ??5 k ? nonlinearity error ? ? 3.0 lsb offset error ? ? 2.0 lsb full-scale error ? ? 2.0 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb rev. 1.0, 11/02, page 679 of 690 appendix a. i/o port states in each processing state table a.1 i/o port states in each processing state reset power-down states category pin power-on reset manual reset software standby sleep bus mastership released i/o handling of unused pins clock extal i i i i i i pull-up xtal o o o o o o open extal2 i i i i i i pull-up xtal2 o o o o o o open ckio i o * 1 i o * 1 i o * 1 i o * 1 i o * 1 i o open resetp i i i i i i must be used system control resetm i i i i i i pull-up breq /ptg[6] z i p * 2 i k * 3 i p * 2 i i/io pull-up back /ptg[5] o o p * 2 o k * 3 o p * 2 l p * 2 o/io open md6iizii ipull-down md[2:0] i i i i i i must be used md[5:3] i i z i i i must be used ca i i i i i i pull-up status0/ pte[4]/ rts0 hh p * 2 z * 6 h k * 3 z * 6 l p * 2 ol p * 2 o o/io/ o open status1/ pte[5]/ cts0 hh p * 2 z * 6 l k * 3 z * 7 h p * 2 il p * 2 i o/io/ i open interrupt irq[3:0]/ irl[3:0] / pth[3:0] zi p * 2 i k * 3 i p * 2 i p * 2 i/i/io pull-up irq4/pth[4] z i p * 2 i k * 3 i p * 2 i p * 2 i/io pull-up irq5/pte[2] z i p * 2 i k * 3 i p * 2 i p * 2 i/io pull-up nmiiiiii ipull-up address a[25:19,0]/ ptk[7:0] oo p * 2 zo * 8 k * 3 o p * 2 z p * 2 o/io open a[18:1] o o zo * 8 o z o open rev. 1.0, 11/02, page 680 of 690 reset power-down states category pin power-on reset manual reset software standby sleep bus mastership released i/o handling of unused pins data d[15:0] z z z io z io pull-up d[23:16]/ pta[7:0]/ pint[7:0] zz p * 2 z p * 2 io p * 2 z p * 2 io/io /i pull-up d[31:24]/ ptb[7:0]/ pint[15:8] zz p * 2 z p * 2 io p * 2 z p * 2 io/io /i pull-up cs0 hozh * 6 o z o open bus control cs2 /ptc[3] h o p * 2 zh * 6 k * 3 o p * 2 z p * 2 o/io open cs3 /ptc[4] h o p * 2 zh * 6 k * 3 o p * 2 z p * 2 o/io open cs4 /ptc[5] h o p * 2 zh * 6 k * 3 o p * 2 z p * 2 o/io open cs5a /ptc[6] z o p * 2 zh * 6 k * 3 o p * 2 z p * 2 o/io pull-up cs5b /ptd[6] z o p * 2 zh * 6 k * 3 o p * 2 z p * 2 o/io pull-up cs6a /ptc[7] z o p * 2 zh * 6 k * 3 o p * 2 z p * 2 o/io pull-up cs6b /ptd[7] z o p * 2 zh * 6 k * 3 o p * 2 z p * 2 o/io pull-up bs /ptc[0] h o p * 2 zh * 6 k * 3 o p * 2 z p * 2 o/io open rasl /ptd[0] h o p * 2 zh * 6 k * 3 o p * 2 zh * 6 p * 2 o/io open rasu /ptd[1] z o p * 2 zh * 6 k * 3 o p * 2 zh * 6 p * 2 o/io pull-up casl /ptd[2] h o p * 2 zh * 6 k * 3 o p * 2 zh * 6 p * 2 o/io open casu /ptd[3] z o p * 2 zh * 6 k * 3 o p * 2 zh * 6 p * 2 o/io pull-up we0 /dqmll h o zh * 6 o z o/o open we1 /dqmlu h o zh * 6 o z o/o open we2 /dqmul/ ptc[1] ho p * 2 zh * 6 k * 3 o p * 2 z p * 2 o/o/i o open we3 /dqmuu/ ah /ptc[2] ho p * 2 zh * 6 k * 3 o p * 2 z p * 2 o/o/ o/io open rd/ wr hozh * 6 o z o open rd hozh * 6 o z o open cke/ptd[4] h o p * 2 ok * 3 o p * 2 op * 2 o/io open wait /ptg[7] i i p * 2 i k * 3 i p * 2 i p * 2 i/io pull-up rev. 1.0, 11/02, page 681 of 690 reset power-down states category pin power-on reset manual reset software standby sleep bus mastership released i/o handling of unused pins dmac dreq0/ pth[5] zz p * 2 z k * 3 i p * 2 i p * 2 i/io pull-up dack0/ pte[0] vo p * 2 z k * 3 o p * 2 o p * 2 o/io open tend0/ pte[3] vo p * 2 z k * 3 o p * 2 o p * 2 o/io open dreq1/ pth[6] zz p * 2 z k * 3 i p * 2 i p * 2 i/io pull-up dack1/ pte[1] vo p * 2 z k * 3 o p * 2 o p * 2 o/io open timer tclk/pte[6] v i p * 2 z k * 3 i p * 2 i p * 2 i/io open scif rxd0/ scpt[0]/irrx zz i * 4 z i i i/i/i pull-up txd0/ scpt[0]/irtx zz o * 5 z o * 5 o o o/o/ o open sck0/ scpt[1] zz p * 2 z k * 3 io p * 2 io p * 2 io/io pull-up rxd2/ scpt[2] zz i * 4 z i i i/i pull-up txd2/ scpt[2] zz o * 5 z o * 5 o o o/o open sck2/ scpt[3] zz p * 2 z k * 3 io p * 2 io p * 2 io/io pull-up rts2 / scpt[4] vz p * 2 z k * 3 o p o p o/io open cts2 / scpt[5] zz p * 2 z k * 3 i p * 2 i p * 2 i/io pull-up analog an[3:0]/ ptl[3:0] iz i * 4 i i i i/i open usb vbus/ ptm[6] vi p * 2 z k * 2 i p * 2 i p * 2 i/io open suspnd/ ptn[0] vo p * 2 o k * 3 o p * 2 o p * 2 o/io open txenl/ ptn[1] vo p * 2 o k * 3 o p * 2 o p * 2 o/io open xvdata/ ptn[2] vi p * 2 v k * 3 i p * 2 i p * 2 i/io open rev. 1.0, 11/02, page 682 of 690 reset power-down states category pin power-on reset manual reset software standby sleep bus mastership released i/o handling of unused pins usb txdmns/ ptn[3] vo p * 2 o k * 3 o p * 2 o p * 2 o/io open txdpls/ ptn[4] vo p * 2 o k * 3 o p * 2 o p * 2 o/io open dmns/ ptn[5] vi p * 2 v k * 3 i p * 2 i p * 2 i/io open dpls/ptn[6] v i p * 2 v k * 3 i p * 2 i p * 2 i/io open extal_usb i i i i i i pull-up xtal_usb o o o o o o open d+ z io * 9 zio * 9 io * 9 io open d- z io * 9 zio * 9 io * 9 io open port nf/ptd[5] i i z i i i/i pull-up pte[7] v p k p p io open nf/ptj[7] l o o o o o/o open nf/ptj[6:0] h o o o o o/o open nf/ptm[4] i i z i i i/i pull-up ptm[3:0] v p k p p io open ptn[7] v p k p p io open audsync/ ptf[4] v/v * 10 o p * 2 o k * 3 o p * 2 o p * 2 o/io open audata[3:0]/ ptf[3:0]/ to[3:0] v/v * 10 o p * 2 z * 8 o k * 3 z * 8 o p * 2 o p * 2 o/io/ o open advanced user debugger audck/ ptg[4] o/v * 10 o p * 2 o k * 3 o p * 2 o p * 2 o/io open tdi/ptg[0] i * 11 i * 11 p * 2 i * 11 k 3 i * 11 p * 2 i * 11 p * 2 i/io open tck/ptg[1] i * 11 i * 11 p * 2 i * 11 k 3 i * 11 p * 2 i * 11 p * 2 i/io open tms/ptg[2] i * 11 i * 11 p * 2 i * 11 k 3 i * 11 p * 2 i * 11 p * 2 i/io open hitachi user debugg- ing interface trst /ptg[3] i * 11 i * 11 p * 2 i * 11 k 3 i * 11 p * 2 i * 11 p * 2 i/io must be used tdo/ptf[5] oz o p * 2 z k * 3 o p * 2 o p * 2 o/io open asebrkak / ptf[6] v/v * 10 o p * 2 o k * 3 o p * 2 o p * 2 o/io open asemd0 / ptf[7] i * 11 i * 11 p * 2 v k * 3 i * 11 p * 2 i * 11 p * 2 i/io must be used rev. 1.0, 11/02, page 683 of 690 reset power-down states category pin power-on reset manual reset software standby sleep bus mastership released i/o handling of unused pins vcc_usb ????? ? vccq vss_usb ????? ? vssq power supply voltage vcc-rtc ????? ? vccq vss-rtc ????? ? vssq avcc ????? ? vccq avss ????? ? vssq vccq ????? ? vccq vssq ????? ? vssq vcc-pll1 ????? ? vcc * 12 vss-pll1 ????? ? vss * 12 vcc-pll2 ????? ? vcc * 12 vss-pll2 ????? ? vss * 12 vcc ????? ? vcc vss ????? ? vss legend: i : input state i : input state (however, input is fixed by the internal logic.) o : output state (high or low, undefined) l : low-level output h : high-level output z : high impedance (input/output buffer off) v : input/output buffer off, pull-up on k : the high-level output or low-level output/input becomes high impedance. p : input or output depending on the register settings. notes: * 1 depends on clock mode. * 2 the state is p when the port function is used. * 3 the state is k when the port function is used. * 4 the state is i when the port function is used. * 5 the state is o when the port function is used. * 6 the state is z or h depending on the register settings. * 7 the state is z or l depending on the register settings. * 8 the state is z or o depending on the register settings. * 9 the state is i when the usb is not used. * 10 the initial value (power-on reset) changes depending on the input level of the asemd0 pin. first, this list shows the value when the asemd0 pin is 0, then the value when the asemd0 pin is 1. rev. 1.0, 11/02, page 684 of 690 * 11 pull-up mos open * 12 to avoid the power friction, vcc-pll1, vcc-pll2, and vss-pll1, vss-pll2, and other digital vcc, vss should be arranged in three independent patterns from the board power-supply source. connect the pull-up pins shown in table a.1 to 3.3 v power through the pull-up resistor. rev. 1.0, 11/02, page 685 of 690 b. package dimensions figures b.1 and b.2 show the package dimensions. hitachi code jedec eiaj weight (reference value) fp-208c ? conforms 2.7 g unit: mm * dimension including the plating thickness base material dimension 30.0 0.2 30.0 0.2 0.5 1.70 max 0 ? 8 * 0.17 0.05 156 105 104 52 1 157 208 53 * 0.22 0.05 0.08 m 0.08 1.40 0.5 0.1 1.0 28 0.10 0.05 1.25 0.20 0.04 0.15 0.04 figure b.1 package dimensions (fp-208c) rev. 1.0, 11/02, page 686 of 690 0.65 0.80 0.80 12.00 12.00 0.15 4 0.2 c c 0.10 c 0.65 0.31 0.05 1.20max b a d c f e h g k j m l p n t r u 17 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 0.20 c a 0.20 c b b c 0.08 ab 208 0.40 0.05 m a unit: mm hitachi code jedec jeita mass (reference value) tbp-208a ? ? 0.26 g figure b.2 package dimensions (tbp-208a) rev. 1.0, 11/02, page 687 of 690 index 16-bit timer pulse unit............................. 329 16-bit/32-bit displacement ...................... 41 a/d conversion time............................... 534 a/d converter ......................................... 527 absolute addresses................................... 41 access wait control................................. 192 address multiplexing.............................. 200 address space identifier ........................... 71 address transition.................................... 71 address-array read ............................... 104 address-array write (associative operation) .......................... 104 address-array write (non-associative operation)................... 104 advanced user debugger......................... 583 alarm function........................................ 371 asynchronous mode ............................... 402 auto-reload count operation.................. 319 auto-request mode ................................ 254 big endian......................................... 38, 180 boundary scan mode............................... 581 buffer operation...................................... 346 bulk-in transfer ....................................... 462 bulk-out transfer ..................................... 461 burst mode.............................................. 265 burst read................................................ 212 burst rom interface............................... 231 bus arbitration ........................................ 235 bus clock (b ) ........................................ 271 bus state controller................................ 149 byte-selection sram interface .............. 233 clock pulse generator ............................ 271 clock synchronous mode........................ 396 compare match counter operation .......... 326 compare match timer.............................. 323 control registers ...................................... 29 control transfer ....................................... 455 crystal resonator .....................................273 cycle-steal mode ....................................264 data stage................................................457 data-array read .....................................105 data-array write ....................................105 delayed branching....................................40 direct memory access controller.............239 dual address mode .................................261 emulator..................................................567 exception handling..................................109 exception handling state..........................25 external request mode.............................265 fixed mode..............................................257 free-running count ..................................344 general registers ......................................29 global base register (gbr) ....................36 hitachi user debugging interface.............567 i/o ports ..................................................507 infrared data association (irda) .............431 input capture function .............................320 instruction length .....................................40 internal clock (i )....................................271 interrupt controller .................................125 interrupt sources......................................136 interrupt-in transfer .................................463 interval timer mode .................................291 irda interface .........................................431 irl interrupts..........................................137 irq interrupts .........................................136 jtag.......................................................567 literal constant.........................................41 little endian ......................................39, 180 rev. 1.0, 11/02, page 688 of 690 load/store architecture............................ 40 low-frequency mode.............................. 228 low-power consumption state ................ 25 mmu ........................................................ 65 module standby function....................... 301 multi mode ............................................. 533 multiple interrupts .................................. 147 multiple virtual memory mode ............... 71 multiply and accumulate registers.......... 33 nmi interrupt.......................................... 136 on-chip peripheral module interrupts..... 138 on-chip peripheral module request modes ................................................................ 256 p0/u0 area ............................................... 27 p1 area ..................................................... 27 p2 area ..................................................... 27 p3 area ..................................................... 27 p4 area ..................................................... 27 peripheral clock (p ) .............................. 271 physical address space ............................ 70 pin function controller ............................ 475 pint interrupt......................................... 138 power-down modes................................ 293 priority.................................................... 137 procedure register.................................... 33 processing modes ..................................... 26 program counter....................................... 29 pwm mode............................................. 348 realtime clock ........................................ 351 receive margin ....................................... 429 refreshing............................................... 225 register adcsr....................... 530, 594, 611, 621 addr......................... 530, 594, 611, 621 bamra...................... 544, 594, 612, 621 bamrb...................... 546, 594, 612, 621 bara ......................... 543, 594, 612, 621 barb ......................... 545, 594, 612, 621 basra ....................... 553, 594, 612, 621 basrb ....................... 554, 594, 612, 621 bbra.......................... 544, 594, 612, 621 bbrb.......................... 547, 594, 612, 621 bdmrb ...................... 547, 594, 611, 621 bdrb.......................... 546, 594, 611, 621 betr .......................... 552, 594, 611, 621 brcr.......................... 549, 594, 611, 621 brdr.......................... 553, 594, 612, 621 brsr .......................... 552, 594, 612, 621 ccr1 .................................. 586, 596, 614 ccr2 .................................. 586, 596, 614 ccr3 .................................. 586, 596, 614 chcr.......................... 243, 588, 601, 615 cmcnt ...................... 326, 589, 604, 616 cmcor ...................... 326, 589, 604, 616 cmcsr....................... 325, 589, 604, 616 cmncr ...................... 156, 587, 598, 614 cmstr ....................... 324, 589, 604, 616 cs0bcr.............................. 587, 598, 614 cs0wcr............................. 587, 599, 615 csnbcr.............................................. 158 csnwcr............................................. 161 dar ............................ 242, 588, 601, 615 dasts........................ 449, 592, 609, 619 dmaor...................... 248, 588, 603, 616 dmar......................... 450, 592, 609, 620 dmars ...................... 250, 588, 603, 616 dmatcr ................... 243, 588, 601, 615 epdr0i ....................... 445, 592, 609, 619 epdr0o ...................... 445, 592, 609, 619 epdr0s....................... 445, 592, 609, 619 epdr1 ........................ 446, 592, 609, 619 epdr2 ........................ 446, 592, 609, 619 epdr3 ........................ 446, 592, 609, 619 epstl......................... 453, 592, 609, 620 epsz0o ....................... 447, 592, 609, 619 epsz1 ......................... 447, 592, 609, 620 expevt ............................. 586, 596, 614 fclr........................... 449, 592, 609, 619 frqcr ....................... 279, 588, 603, 616 icr0.................... 110, 129, 587, 597, 614 icr1............................ 130, 587, 597, 614 rev. 1.0, 11/02, page 689 of 690 icr2............................ 132, 587, 597, 614 ier0............................ 444, 592, 609, 620 ier1............................ 444, 592, 609, 620 ifr0 ............................ 441, 592, 609, 619 ifr1 ............................ 442, 592, 609, 619 intevt.............................. 586, 596, 614 intevt2............................ 586, 596, 614 ipr .............................. 128, 586, 597, 614 irr0............................ 133, 587, 597, 614 irr1............................ 134, 587, 597, 614 irr2............................ 135, 587, 597, 614 isr0 ............................ 443, 592, 609, 620 isr1 ............................ 443, 592, 609, 620 mmucr ............................. 586, 595, 614 pacr.......................... 480, 593, 609, 620 padr.......................... 508, 593, 610, 620 pbcr .......................... 481, 593, 609, 620 pbdr.......................... 509, 593, 610, 620 pccr .......................... 483, 593, 609, 620 pcdr.......................... 510, 593, 610, 620 pdcr.......................... 485, 593, 610, 620 pddr.......................... 511, 593, 610, 620 pecr .......................... 487, 593, 610, 620 pecr2 ........................ 488, 593, 610, 620 pedr .......................... 513, 593, 610, 620 pfcr........................... 489, 593, 610, 620 pfcr2......................... 490, 593, 610, 620 pfdr .......................... 514, 593, 610, 620 pgcr.......................... 491, 593, 610, 620 pgdr.......................... 516, 593, 610, 620 phcr.......................... 493, 593, 610, 620 phdr.......................... 517, 593, 611, 621 pinter ...................... 132, 587, 597, 614 pjcr ........................... 494, 593, 610, 620 pjdr........................... 518, 593, 611, 621 pkcr.......................... 496, 593, 610, 620 pkdr.......................... 519, 593, 611, 621 plcr .......................... 498, 593, 610, 620 pldr .......................... 521, 593, 611, 621 pmcr ......................... 499, 593, 610, 620 pmdr ......................... 522, 593, 611, 621 pncr.......................... 500, 593, 610, 620 pncr2........................ 502, 593, 610, 620 pndr.......................... 523, 593, 611, 621 pteh................................... 586, 595, 614 ptel ................................... 586, 595, 614 r64cnt ...................... 354, 591, 607, 618 rcr1........................... 365, 591, 608, 618 rcr2........................... 366, 591, 608, 618 rcr3........................... 368, 591, 608, 618 rdayar.................... 362, 591, 607, 618 rdaycnt ................. 357, 591, 607, 618 rhrar....................... 360, 591, 607, 618 rhrcnt .................... 355, 591, 607, 618 rminar..................... 359, 591, 607, 618 rmincnt .................. 355, 591, 607, 618 rmonar ................... 363, 591, 607, 618 rmoncnt................. 357, 591, 607, 618 rsecar ..................... 358, 591, 607, 618 rseccnt................... 354, 591, 607, 618 rtcnt ....................... 179, 587, 600, 615 rtcor ....................... 179, 587, 600, 615 rtcsr ........................ 177, 587, 600, 615 rwkar...................... 361, 591, 607, 618 rwkcnt ................... 356, 591, 607, 618 ryrar....................... 364, 591, 608, 618 ryrcnt .................... 358, 591, 607, 618 sar............................. 242, 588, 601, 615 scbrr........................ 395, 591, 608, 619 scfcr ........................ 398, 591, 608, 619 scfdr ........................ 401, 591, 608, 619 scfer ........................ 389, 591, 608, 619 scfrdr ..................... 380, 591, 608, 619 scftdr...................... 381, 591, 608, 619 scpcr ........................ 503, 593, 610, 620 scpdr ........................ 525, 593, 611, 621 scrsr ................................................380 scscr ........................ 385, 591, 608, 619 scsmr (scif) ........... 381, 591, 608, 619 scsmr_ir (irda)....... 432, 592, 609, 619 scssr......................... 390, 591, 608, 619 sctdsr...................... 401, 591, 608, 619 sctsr ................................................380 sdbpr................................................569 sdbsr ................................................570 sdcr .......................... 174, 587, 600, 615 rev. 1.0, 11/02, page 690 of 690 sdid................................................... 577 sdid/sdidh...................... 594, 613, 621 sdidl ................................ 594, 613, 621 sdir ........................... 569, 594, 613, 621 sdmr2....................... 229, 587, 601, 615 sdmr3....................... 230, 587, 601, 615 stbcr........................ 296, 588, 603, 616 stbcr2...................... 297, 588, 603, 616 stbcr3...................... 298, 588, 603, 616 tcnt (tmu) ............. 317, 589, 603, 616 tcnt (tpu)............... 341, 589, 605, 617 tcor.......................... 317, 589, 603, 616 tcpr .......................... 317, 589, 604, 616 tcr (tmu)................ 313, 589, 603, 616 tcr (tpu) ................. 334, 589, 605, 617 tea .................................... 586, 597, 614 tgr ............................ 341, 589, 605, 617 tier ........................... 339, 589, 605, 617 tior........................... 338, 589, 605, 617 tmdr......................... 337, 589, 605, 617 tra .................................... 586, 596, 614 trg ............................ 448, 592, 609, 619 tsr............................. 340, 589, 605, 617 tstr (tmu).............. 312, 589, 603, 616 tstr (tpu) ............... 341, 589, 605, 617 ttb..................................... 586, 595, 614 uclkcr .................... 281, 588, 603, 616 wtcnt ...................... 286, 588, 603, 616 wtcsr ...................... 287, 588, 603, 616 xvercr .................... 453, 592, 609, 620 reset state ................................................ 25 round-robin mode................................. 258 rtc crystal oscillator circuit.................. 372 save program counter (spc) ................... 36 save status register (ssr) ....................... 36 scan mode............................................... 534 sdram interface ................................... 198 sequential break...................................... 558 serial communication interface with fifo ................................................................ 375 setup stage .............................................. 456 shadow space.......................................... 155 signal-source impedance........................ 538 single address mode .............................. 262 single mode ............................................ 533 single virtual memory mode ................... 71 sleep mode.............................................. 299 software standby mode........................... 300 stall operations........................................ 465 status register (sr) .................................. 35 status stage.............................................. 459 synonym problem..................................... 83 system registers ....................................... 29 t bit .......................................................... 40 tap controller ........................................ 578 timer unit............................................... 309 trapa exception register .................... 110 usb function module.............................. 437 usb standard commands ........................ 464 user break controller............................... 541 user break exception processing............. 554 vector base register (vbr).................... 37 virtual address space............................... 67 watchdog timer....................................... 285 watchdog timer mode............................. 291 sh7705 hardware manual publication date: 1st edition, november 2002 published by: business operation division semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 2002. all rights reserved. printed in japan. |
Price & Availability of HD6417705
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |